Chip structure, preparation method thereof and mass spectrometer
By covering the conductive layer on the lower surface of the chip base, ensuring that the substrate to be detected is located at the same equipotential surface, the detection problem caused by uneven electric field in the prior art is solved, and the detection accuracy and accuracy are improved.
Patent Information
- Application Number
- CN202411618948.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-02-25
AI Technical Summary
The chip structure in existing mass spectrometers causes the electric field of the matrix to be detected to be uneven and cannot be located in the same equipotential plane, resulting in high quality repeatability, low ionization degree and low accuracy of detection results.
A chip structure is adopted, in which the lower surface of the chip base is covered with a conductive layer, and the conductive layer comes into contact with the abutment part of the bracket. When the bracket is powered on, the conductive layer is charged to generate a uniform electric field to ensure that the substrate to be detected is located in the same equal potential plane.
The uniform electric field ensures the detection accuracy of the matrix to be detected, reduces the mass repeatability, improves the degree of ionization and detection accuracy.
Smart Images
Figure CN119517724A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of mass spectrometry instruments, and more specifically, to a chip structure and a preparation method thereof, and a mass spectrometry instrument. Background Art
[0002] The mass spectrometer of the prior art has a low mass number detection accuracy. Taking the matrix-assisted laser desorption ionization time-of-flight mass spectrometer as an example, its main operating principle is: by irradiating a sample containing a matrix to be detected with a laser, the matrix to be detected is ionized and charged. Then, through the action of the electric field, the ionized charged ions pass through the time-of-flight mass analyzer and finally reach the detector. By analyzing the difference in flight time between ions, ions of different mass numbers can be distinguished, thereby achieving the purpose of detecting mass numbers. According to the detection operating principle, the uniformity of the distribution of the electric field will affect the final mass number detected and the degree of ionization of the matrix to be detected.
[0003] When using a matrix-assisted laser desorption ionization time-of-flight mass spectrometer, it is necessary to package the chip preform and the matrix to be detected as finished products, and then ionize the packaged chip so that the matrix to be detected inside it is ionized. Before ionization, the chip will be placed inside the chip holder, and it is necessary to ensure that there is a certain gap between the bottom of the chip and the inner wall of the chip holder for placing the remaining devices. Therefore, the inner bottom wall of the chip holder needs to be provided with an abutment portion to support the chip. When the matrix-assisted laser desorption ionization time-of-flight mass spectrometer is used for nucleic acid detection, the chip used is an insulating material, such as a silicon-based chip.
[0004] Please refer to Figure 1 At this time, the inner bottom wall of the chip holder is usually lower than the upper surface of the abutting portion, and there may also be a height difference between the inner bottom walls of the chip holder, so the electric field strength formed by the final chip structure is different in different places, that is, the electric field lines formed on the abutting portion have a higher initial position, and the initial position of the electric field lines on the inner bottom wall of the chip holder is lower than that of the abutting portion, and the matrix to be detected on the chip cannot be located on the same equipotential surface in the electric field.
[0005] In summary, during the detection process, the electric field of the matrix to be detected in the existing chip structure is uneven and cannot be located on the same equipotential surface, which leads to high quality repeatability of the detection results, low ionization degree and low accuracy. Summary of the invention
[0006] In order to solve the above technical problems, the embodiments of the present application adopt the following solutions:
[0007] A chip structure, comprising:
[0008] A chip substrate, wherein the chip substrate is used to carry a matrix to be detected;
[0009] A conductive layer covers the lower surface of the chip substrate.
[0010] Furthermore, the chip structure further comprises a bracket, the bracket is provided with a receiving groove and a contact portion located in the receiving groove, the chip substrate is located in the receiving groove, and the conductive layer contacts the contact portion.
[0011] Further, the accommodating groove includes a first sub-accommodating groove and a second sub-accommodating groove, and the abutting portion is located between the first sub-accommodating groove and the second sub-accommodating groove, and is used to separate the first sub-accommodating groove and the second sub-accommodating groove.
[0012] Furthermore, the conductive layer further includes a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer covers the lower surface of the chip substrate, and the second sub-conductive layer covers the side wall of the chip substrate and abuts against the side wall of the receiving groove.
[0013] Furthermore, the chip structure further includes a first magnetic member and a second magnetic member, wherein the first magnetic member is connected to the chip substrate or the bottom of the conductive layer, and the second magnetic member is disposed in the receiving groove, and along the direction from the chip substrate to the receiving groove, the first magnetic member and the second magnetic member are disposed opposite to each other; and / or,
[0014] The resistance of the conductive layer is 5 to 10 ohms; and / or,
[0015] The material of the chip substrate includes at least one of silicon-based glass, polyetheretherketone, polytetrafluoroethylene, and ceramic composite materials; and / or,
[0016] The material of the conductive layer includes at least one of indium tin oxide, graphene, conductive metal, and carbon nanotubes.
[0017] Furthermore, the chip structure further comprises a hydrophobic layer and a hydrophilic layer which are stacked in sequence, and a projected area of the hydrophilic layer on the chip substrate is smaller than a projected area of the hydrophobic layer on the chip substrate.
[0018] Further, the thickness of the hydrophobic layer is 200nm to 1000nm; and / or,
[0019] The thickness of the hydrophilic layer is 200 nm to 1000 nm, and / or,
[0020] The thickness of the conductive layer is 100 nm to 300 nm; and / or,
[0021] The material of the hydrophobic layer includes at least one of silicon dioxide, cellulose and its derivatives and polyvinyl alcohol; and / or,
[0022] The material of the hydrophobic layer includes at least one of polydimethylsiloxane, fluorine-containing polymer and polystyrene.
[0023] Furthermore, the hydrophilic layer comprises a plurality of sub-hydrophilic layers, and the plurality of sub-hydrophilic layers are distributed on the hydrophobic layer at equal intervals;
[0024] Wherein, the diameter of the sub-hydrophilic layer is 200 μm to 500 μm; and / or,
[0025] The distance between adjacent sub-hydrophilic layers is 2 mm to 10 mm.
[0026] Accordingly, the present application also provides a method for preparing a chip structure, the method comprising:
[0027] Providing a chip substrate;
[0028] forming a conductive layer on the lower surface of the chip substrate;
[0029] Forming a hydrophobic layer on the upper surface of the chip substrate, wherein the hydrophobic layer is provided with a sample point area and a mask area;
[0030] Performing masking treatment on the hydrophobic layer to cover the masking area;
[0031] A hydrophilic layer is formed in the sample point area.
[0032] Correspondingly, the present application also provides a mass spectrometer, which includes the chip structure as described in any one of the above embodiments.
[0033] Compared with the prior art, the embodiments of the present application have the following beneficial effects:
[0034] Because the conductive layer covers the lower surface of the chip substrate, when the chip substrate is placed on the bracket, the abutment portion of the bracket will abut against the conductive layer. When the bracket is powered, the conductive layer will also be charged, and the charged conductive layer will generate a uniform electric field, and the electric field lines of the electric field have the same initial position. Therefore, after multiple substrates to be detected are placed on the upper surface of the chip substrate, each substrate to be detected can be located on the same equipotential surface, thereby ensuring the detection accuracy of the substrate to be detected and avoiding high repeatability due to the substrates to be detected being located on different equipotential surfaces. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the solutions in the present application or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0036] Figure 1is a cross-sectional view of a chip structure of the prior art;
[0037] Figure 2 is a schematic diagram of the structure of a chip according to an embodiment of the present application;
[0038] Figure 3 is a cross-sectional view of the chip structure of an embodiment of the present application;
[0039] Figure 4 is another schematic diagram of the chip structure of an embodiment of the present application;
[0040] Figure 5 It is a flow chart of the method for preparing the chip structure of an embodiment of the present application.
[0041] Reference numerals:
[0042] The chip structure 10 , the chip substrate 100 , the bracket 200 , the abutting portion 210 , the receiving groove 220 , the conductive layer 300 , the hydrophobic layer 400 , and the hydrophilic layer 500 . DETAILED DESCRIPTION
[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application.
[0044] In this application, unless otherwise stated, directional words such as "upper" and "lower" generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. In addition, in the description of this application, the term "including" means "including but not limited to". The terms first, second, third, etc. are used only as labels and do not impose numerical requirements or establish an order.
[0045] In this application, "and / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.
[0046] In the present application, "at least one" means one or more, and "plurality" means two or more. "At least one", "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, "at least one of a, b, or c", or "at least one of a, b, and c" can all mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, c can be single or multiple, respectively.
[0047] Various embodiments of the present application may be presented in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity, and should not be understood as a rigid limitation on the scope of the present application; therefore, the range description should be considered to have specifically disclosed all possible sub-ranges and single numerical values within the range. For example, the range description from 1 to 6 should be considered to have specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which apply regardless of the range. In addition, whenever a numerical range is indicated herein, it is meant to include any cited number (fractional or integer) within the indicated range.
[0048] Please refer to Figure 2 and Figure 3 , Figure 3 The Z direction is the up-down direction. The present application provides a chip structure 10, which includes:
[0049] A chip substrate 100, the chip substrate 100 is used to carry a matrix to be detected;
[0050] The conductive layer 300 covers the lower surface of the chip substrate 100 .
[0051] In this embodiment, since the conductive layer 300 covers the lower surface of the chip substrate 100, when the chip substrate 100 is placed on the bracket 200, the abutting portion 210 of the bracket 200 will abut against the conductive layer 300. When the bracket 200 is powered, the conductive layer 300 will also be charged, and the charged conductive layer 300 will produce the following Figure 3 The uniform electric field shown has the same initial position of the electric field lines, so after a plurality of substrates to be detected are placed on the upper surface of the chip substrate 100, each substrate to be detected can still be located on the same equipotential surface, thereby ensuring the detection accuracy of the substrate to be detected and avoiding high repeatability caused by the substrates to be detected being located on different equipotential surfaces.
[0052] For further information, please refer to Figure 2 and Figure 3The chip structure 10 further includes a bracket 200 , which is provided with a receiving groove 220 and an abutting portion 210 located in the receiving groove 220 . The chip substrate 100 is located in the receiving groove 220 , and the conductive layer 300 abuts against the abutting portion 210 .
[0053] In this embodiment, the bracket 200 can accommodate and fix the chip substrate 100 to prevent it from shaking and leaving the preset position, thereby improving the detection accuracy of the substrate to be detected.
[0054] For further information, please refer to Figure 2 and Figure 3 The receiving groove 220 includes a first sub-receiving groove and a second sub-receiving groove, and the abutting portion 210 is located between the first sub-receiving groove and the second sub-receiving groove, and is used to separate the first sub-receiving groove and the second sub-receiving groove.
[0055] In this embodiment, the first receiving groove and the second receiving groove can allow the bracket 200 to accommodate devices of different heights, so that the chip structure 10 can be equipped with modules of different functions, such as magnets or conductive devices of different heights. The abutment portion 210 is located between the first sub-accommodation groove and the second sub-accommodation groove, which can make the chip substrate 100 evenly stressed and avoid tilting toward the first sub-accommodation groove or the second sub-accommodation groove. It should be understood that when the devices placed in the first sub-accommodation groove and the second sub-accommodation groove do not affect each other, the abutment portion 210 can be set as a plurality of convex structures arranged side by side and spaced apart, such as a columnar structure. Compared with the continuous structure of the abutment portion 210, the abutment portion 210 of a plurality of columnar structures can reduce the contact area between the abutment portion 210 and the conductive layer 300, thereby avoiding the contact area between the abutment portion 210 and the conductive layer 300 being too large to affect the electric field and the equipotential surface.
[0056] For further information, please refer to Figure 2 and Figure 3 The conductive layer 300 further includes a first sub-conductive layer and a second sub-conductive layer. The first sub-conductive layer covers the lower surface of the chip substrate 100 , and the second sub-conductive layer covers the side wall of the chip substrate 100 and abuts against the side wall of the receiving groove 220 .
[0057] In this embodiment, after the second sub-conductive layer covers the side wall of the chip substrate 100, it can play a role in fixing the chip substrate 100 to a certain extent. At the same time, it can also enable the bracket 200 to transmit current to the conductive layer 300 through the side wall of the receiving groove 220, thereby improving the efficiency of the bracket 200 in transmitting current to the conductive layer 300. It should be understood that the conductive layer 300 can also include a third sub-conductive layer, and in this case, the third sub-conductive layer covers the upper surface of the chip substrate. When the chip structure 10 includes a hydrophobic layer 400 and a hydrophilic layer 500, the hydrophobic layer is disposed on the upper surface of the third sub-conductive layer.
[0058] For further information, please refer to Figure 2 and Figure 3 The chip structure 10 also includes a first magnetic member and a second magnetic member. The first magnetic member is connected to the bottom of the chip substrate 100 or the conductive layer 300, and the second magnetic member is arranged in the receiving groove 220. Along the direction from the chip substrate 100 to the receiving groove 220, the first magnetic member and the second magnetic member are arranged opposite to each other.
[0059] In the present embodiment, the chip structure 10 can fix the chip substrate 100 with the conductive layer 300 and the bracket 200 through the magnetic attraction generated between the first magnetic attraction member and the second magnetic attraction member, so as to prevent the chip substrate 100 from shaking compared to the bracket 200, causing the matrix to be detected on the chip substrate 100 to be out of the ionization position. Compared with the connection method using the snap connection, the connection method of the present embodiment does not need to be assembled, and can complete a small range of adaptive position automatic adjustment through the magnetic attraction between the first member and the second magnetic attraction member. In summary, the chip structure 10 of the present embodiment has high stability, is easy to assemble, and has high production efficiency.
[0060] For further information, please refer to Figure 2 and Figure 3 , the resistance of the conductive layer 300 is 5 to 10 ohms; and / or,
[0061] The material of the chip substrate 100 includes at least one of silicon-based glass, polyetheretherketone, polytetrafluoroethylene, and ceramic composite materials; and / or,
[0062] The material of the conductive layer 300 includes at least one of indium tin oxide, graphene, conductive metal, and carbon nanotube.
[0063] In this embodiment, the resistance range of the conductive layer 300 can make the conductive layer 300 have a relatively good conductivity. After the bracket 200 is powered on, the current can flow relatively smoothly in the conductive layer 300, thereby quickly and stably establishing an electric field. In this way, it can be ensured that the substrate to be detected on the upper surface of the chip substrate 100 can be quickly on the equipotential surface determined by the electric field, providing a stable electrical environment for detection, and improving the response speed and efficiency of detection. The material of the conductive substrate can resist the erosion of various chemical reagents, is suitable for complex sample processing and analysis environments, ensures that the chip will not be damaged during long-term use, and has good insulation properties, can effectively isolate the conductive layer 300, and ensure that the electrical performance of the chip substrate 100 is stable. The material of the conductive layer 300 has high electron mobility and conductivity, can quickly conduct current, and realize efficient electric field control; at the same time, it has high strength, high toughness and good flexibility, can withstand certain external forces and deformation, and is suitable for various complex operating environments.
[0064] For further information, please refer to Figures 2 to 4The chip structure 10 further includes a hydrophobic layer 400 and a hydrophilic layer 500 which are stacked in sequence, and a projection area of the hydrophilic layer 500 on the chip substrate 100 is smaller than a projection area of the hydrophobic layer 400 on the chip substrate 100 .
[0065] In this embodiment, since the projected area of the hydrophilic layer 500 on the chip substrate 100 is smaller than the projected area of the hydrophobic layer 400, when the substrate to be detected enters the hydrophilic layer 500, it is adsorbed on the hydrophilic layer 500 and blocked by the hydrophobic layer 400 around the hydrophilic layer 500, thereby limiting the substrate to be detected to the area where the hydrophilic layer 500 is located. The hydrophobic layer 400 can also effectively prevent cross contamination between different substrates to be detected. When multiple substrates to be detected exist on the chip substrate 100 at the same time, the hydrophobic layer 400 can serve as a physical barrier, and cooperate with the adsorption effect of the hydrophilic layer 500 to prevent mutual diffusion and mixing between the substrates to be detected. In this way, it can be ensured that each substrate to be detected can be detected independently without interference from other samples, thereby ensuring the reliability of the test results.
[0066] For further information, please refer to Figure 2 and Figure 3 , the thickness of the hydrophobic layer 400 is 200nm to 1000nm; and / or,
[0067] The thickness of the hydrophilic layer 500 is 200 nm to 1000 nm, and / or,
[0068] The thickness of the conductive layer 300 is 100 nm to 300 nm; and / or,
[0069] The material of the hydrophobic layer 400 includes at least one of silicon dioxide, cellulose and its derivatives, and polyvinyl alcohol; and / or,
[0070] The material of the hydrophobic layer 400 includes at least one of polydimethylsiloxane, fluorine-containing polymer, and polystyrene.
[0071] In the present embodiment, the thickness of the hydrophobic layer 400 can ensure that it has sufficient barrier capacity for the matrix to be detected. It can effectively prevent the matrix to be detected from diffusing to non-specified areas, and it will not take up too much space due to being too thick, affecting the compactness of the overall structure of the chip. The thickness of the hydrophilic layer 500 can ensure that the hydrophilic layer 500 has sufficient adsorption capacity. It can firmly adsorb the matrix to be detected, prevent it from accidentally falling off during the detection process, and ensure the stability and reliability of the detection. The thickness of the conductive layer 300 can save material costs while ensuring good electrical conductivity, that is, it can meet the current transmission requirements of the conductive layer 300 and ensure that the stable establishment of the electric field avoids the waste of materials caused by being too thick. The material of the hydrophobic layer 400 can improve the adsorption and enrichment efficiency of the sample, thereby improving the sensitivity of mass spectrometry detection. For example, by selecting a hydrophobic material with a specific surface property, the adsorption capacity of the matrix to be detected can be enhanced, so that more sample molecules are gathered in the detection area, and the intensity of the detection signal is improved. The material of the hydrophilic layer 500 has good biocompatibility and is suitable for the analysis of biological samples. For example, the hydrophobic layer 400 containing these materials can be used to process biological samples such as proteins, reduce nonspecific adsorption of biological molecules such as proteins, and improve detection accuracy.
[0072] Accordingly, the present application also provides a method for preparing a chip structure 10, the method comprising:
[0073] S100, providing a chip substrate 100;
[0074] S200, forming a conductive layer 300 on the lower surface of the chip substrate 100;
[0075] S300, forming a hydrophobic layer 400 on the upper surface of the chip substrate 100, wherein the hydrophobic layer 400 is provided with a sample point area and a mask area;
[0076] S400, performing mask processing on the hydrophobic layer 400 to cover the mask area;
[0077] S500 , forming a hydrophilic layer 500 in the sample point area.
[0078] In the present embodiment, the chip structure 10 prepared by the preparation method of the present application contains a conductive layer 300 on the surface of the chip substrate 100, so when the chip substrate 100 is placed on the bracket 200, the abutment portion 210 of the bracket 200 will abut against the conductive layer 300. After the bracket 200 is powered, the conductive layer 300 will also be charged, and the charged conductive layer 300 will produce a uniform electric field, and the electric field lines of the electric field have the same initial position, so after a plurality of substrates to be detected are placed on the upper surface of the chip substrate 100, each substrate to be detected can be located at the same equipotential surface, thereby ensuring the detection accuracy of the substrate to be detected, and avoiding the high repeatability caused by the substrate to be detected being located at different equipotential surfaces. At the same time, the arrangement of the hydrophobic layer 400 and the hydrophilic layer 500 can prevent the substrate to be detected from being separated from the preset position, thereby improving the accuracy of the detection of the mass spectrometer with the chip structure 10.
[0079] For further information, please refer to Figures 2 to 5 The hydrophilic layer 500 includes a plurality of sub-hydrophilic layers, and the plurality of sub-hydrophilic layers are distributed on the hydrophobic layer 400 at equal intervals;
[0080] Wherein, the diameter of the sub-hydrophilic layer is 200 μm to 500 μm; and / or,
[0081] The distance between adjacent sub-hydrophilic layers is 2 mm to 10 mm.
[0082] In this embodiment, multiple sub-hydrophilic layers are equally spaced to achieve simultaneous processing and detection of multiple substrates to be detected. On the limited area of the chip substrate 100, the spacing between the sub-hydrophilic layers of this embodiment makes it possible for each sub-hydrophilic layer to not interfere with each other, so that the hydrophilic layer 500 can simultaneously adsorb multiple or different substrates to be detected for detection, thereby improving the detection efficiency. The diameter of the sub-hydrophilic layer (200μm-500μm) can ensure that each sub-hydrophilic layer can effectively adsorb an appropriate amount of the substrate to be detected. Neither will the adsorption be insufficient due to a small diameter, affecting the sensitivity of the detection; nor will the adsorption of too much substrate be excessive due to a large diameter, affecting the accuracy of the detection.
[0083] It should be understood that when the matrix-assisted laser desorption ionization time-of-flight mass spectrometer is used for microbial identification, the material of its chip substrate can be a stainless steel sheet, which is a conductive material with a flat surface. When high voltage is applied to the mass spectrometer, the starting point of the electrostatic field is the stainless steel sheet, so the potential of the sample points at different positions on the stainless steel sheet is the same, and there is no influence on the mass repeatability of different sample points due to uneven electric field. However, when the matrix-assisted laser desorption ionization time-of-flight mass spectrometer is used for nucleic acid detection, the material of its chip substrate needs to be non-conductive silicon-based glass, so after the chip substrate is placed on the bracket, the mass number measured by it has high repeatability and poor accuracy.
[0084] In view of the high repetition rate and poor accuracy of matrix-assisted laser desorption ionization time-of-flight mass spectrometers for nucleic acid detection, stainless steel target plates can be used instead of silicon chip target plates, or software algorithms can be used to correct the mass numbers of different sample points. However, both of the above methods have certain problems: first, the chip substrate of nucleic acid mass spectrometry is disposable in order to avoid cross contamination. If a stainless steel target plate is used as a chip substrate, it will inevitably become a non-disposable chip, and it is inconvenient to pre-embed the sample matrix on the chip substrate, which ultimately leads to high production costs and low production efficiency of the chip structure; secondly, in the solution of using software algorithms for correction, it can only work when there are peaks with known mass numbers in the mass spectrum. When the peaks in the mass spectrum are unknown mass numbers, the software algorithm cannot accurately identify the true mass number of each peak, so it cannot accurately correct the deviation.
[0085] In summary, neither the stainless steel target plate replacement nor the software algorithm correction can perfectly solve the quality repeatability problem of different sample points on the chip substrate.
[0086] To solve the above problems, the present application also provides a mass spectrometer, which includes a chip structure as described in any one of the above embodiments.
[0087] In this embodiment, since the mass spectrometer includes the chip structure of any one of the above embodiments, the initial positions of the electric field lines of the electrostatic field generated by the conductive layer are consistent, and the matrixes to be detected on the chip substrate are located on the same equipotential surface, thereby avoiding the problem of high mass repeatability of the matrixes to be detected.
[0088] The chip structure of the present application is described below by way of examples.
[0089] Example
[0090] This embodiment provides a method for preparing a chip structure, which includes:
[0091] Step 1: Divide an 8-inch silicon-based glass motherboard into chip substrates with a size of 30*20 mm.
[0092] Step 2: Use magnetron sputtering vacuum coating technology to perform ITO coating operation on the lower surface of the above chip substrate. The thickness of the ITO film is 185nm and the resistance value is 6-8Ω.
[0093] Step three, coating a hydrophobic layer on the upper surface of the chip substrate coated with the ITO film.
[0094] Step 4: After the hydrophobic coating is applied, a mask tool is used to mask the chip except for the sample point, and a hydrophilic layer is applied to the sample point area.
[0095] Step 5: Use a spotting device to embed the matrix to be tested on the sample point, and package it into a finished chip after it dries.
[0096] Comparative Example
[0097] The comparative example is substantially the same as the embodiment, except that step three is omitted, and step three directly coats a hydrophobic coating on the chip and the ground.
[0098] The finished chip of the embodiment of the present application and the silicon chip of the prior art of the finished chip of the comparative example are used as components of the mass spectrometer, and the two are tested at the same time to obtain data on mass repeatability and ionization efficiency (expressed as peak intensity) of the two. The data are as follows:
[0099]
[0100] According to the table, in the case of three different characteristic peaks, the reduction in repeatability of the embodiment is greater than that of the comparative example, and the smaller the characteristic peak, the greater the reduction, which indicates that the chip structure of the present embodiment can effectively reduce the mass repeatability. At the same time, as the characteristic peak (the mass number of the ion increases), the increase in the peak intensity of the embodiment compared to the comparative example also increases, which indicates that the chip structure of the present embodiment can improve the ionization efficiency of the mass spectrometer.
[0101] Obviously, the embodiments described above are only some embodiments of the present application, rather than all embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to perform equivalent replacement of some of the technical features therein. Any equivalent structure made using the contents of the specification and drawings of this application, directly or indirectly used in other related technical fields, is similarly within the scope of patent protection of this application.
[0102] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, combinations, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present invention is defined by the claims and their equivalents.
Claims
1. A chip structure, characterized in that: The chip structure comprises: A chip substrate, wherein the chip substrate is used to carry a matrix to be detected; A conductive layer covers the lower surface of the chip substrate.
2. The chip structure according to claim 1, characterized in that: The chip structure further comprises a bracket, wherein the bracket is provided with a receiving groove and a contact portion located in the receiving groove, the chip substrate is located in the receiving groove, and the conductive layer contacts the contact portion.
3. The chip structure according to claim 2, characterized in that: The receiving groove includes a first sub-receiving groove and a second sub-receiving groove, and the abutting portion is located between the first sub-receiving groove and the second sub-receiving groove, and is used to separate the first sub-receiving groove and the second sub-receiving groove.
4. The chip structure according to claim 2, characterized in that: The conductive layer further includes a first sub-conductive layer and a second sub-conductive layer. The first sub-conductive layer covers the lower surface of the chip substrate, and the second sub-conductive layer covers the side wall of the chip substrate and abuts against the side wall of the receiving groove.
5. The chip structure according to claim 2, characterized in that: The chip structure further includes a first magnetic member and a second magnetic member, wherein the first magnetic member is connected to the chip substrate or the bottom of the conductive layer, and the second magnetic member is disposed in the receiving groove, and the first magnetic member and the second magnetic member are disposed oppositely along the direction from the chip substrate to the receiving groove; and / or, The resistance of the conductive layer is 5 to 10 ohms; and / or, The material of the chip substrate includes at least one of silicon-based glass, polyetheretherketone, polytetrafluoroethylene, and ceramic composite materials; and / or, The material of the conductive layer includes at least one of indium tin oxide, graphene, conductive metal, and carbon nanotubes.
6. The chip structure according to claim 1, characterized in that: The chip structure further comprises a hydrophobic layer and a hydrophilic layer which are stacked in sequence, and a projection area of the hydrophilic layer on the chip substrate is smaller than a projection area of the hydrophobic layer on the chip substrate.
7. The chip structure according to claim 6, characterized in that: The thickness of the hydrophobic layer is 200nm to 1000nm; and / or, The thickness of the hydrophilic layer is 200 nm to 1000 nm, and / or, The thickness of the conductive layer is 100 nm to 300 nm; and / or, The material of the hydrophobic layer includes at least one of silicon dioxide, cellulose and its derivatives and polyvinyl alcohol; and / or, The material of the hydrophobic layer includes at least one of polydimethylsiloxane, fluorine-containing polymer and polystyrene.
8. The chip structure according to claim 6, characterized in that: The hydrophilic layer comprises a plurality of sub-hydrophilic layers, and the plurality of sub-hydrophilic layers are distributed on the hydrophobic layer at equal intervals; Wherein, the diameter of the sub-hydrophilic layer is 200 μm to 500 μm; and / or, The distance between adjacent sub-hydrophilic layers is between 2 mm and 10 mm.
9. A method for preparing a chip structure, characterized in that: The method comprises: Providing a chip substrate; forming a conductive layer on the lower surface of the chip substrate; Forming a hydrophobic layer on the upper surface of the chip substrate, wherein the hydrophobic layer is provided with a sample point area and a mask area; Performing masking treatment on the hydrophobic layer to cover the masking area; A hydrophilic layer is formed in the sample point area.
10. A mass spectrometer, characterized in that: The mass spectrometer comprises the chip structure according to any one of claims 1 to 8, or the chip structure prepared by the method according to claim 9.