Non-blocking crossbar scheduling device and method in PCIe, equipment and medium

Abstract

The invention relates to the technical field of computer communication, and discloses a non-blocking crossbar scheduling device, method, equipment and medium in PCIe, and the device comprises a flow control module, an entrance arbitration module, a scheduling module and an exit arbitration module. The entrance arbitration module obtains a credit value of an exit side of the device through the flow control module, and performs order-preserving scheduling and port scheduling on the received target data according to the credit value; and after the scheduling module performs inter-module scheduling on the plurality of inlet arbitration modules, the outlet arbitration module sends the target data to the outlet port of the group outlet module through the outlet side according to the inter-module scheduling result. And scheduling the target data according to the cache condition of the exit side. According to the invention, the scheduled data can be ensured to have a corresponding cache space at the exit, so that the problem of head-of-queue blocking in scheduling is solved.

Description

Technical Field

[0001] The present invention relates to the field of computer communication technology, and in particular to a non-blocking crossbar scheduling device, method, equipment and medium in PCIe. Background Art

[0002] PCIe switch (Peripheral Component Interconnect Express switch, a high-speed serial computer expansion bus standard switch) is a hardware device that expands the expansion and aggregation capabilities of a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) port. It can allow multiple devices to exchange with the host system through the PCIe bus, and allow multiple devices to transmit data to each other.

[0003] It involves scheduling within ports, between ports, and between groups. In related technologies, due to the large number of scheduling levels and the deep combinational logic depth, the PCIe switch timing is tight. Registers are usually used to interrupt the combinational logic path to schedule the data in PCIe. However, it is easy for the intermediate register to fail to output due to the back pressure of the export, resulting in head-of-line blocking.

[0004] In view of this, there is a need for a non-blocking crossbar scheduling device in PCIe that can solve the head-of-line blocking problem in data scheduling. Summary of the invention

[0005] In view of this, the present invention provides a non-blocking crossbar scheduling device in PCIe to solve the head-of-line blocking problem in data scheduling.

[0006] In the first aspect, the present invention provides a non-blocking crossbar scheduling device in PCIe, the device includes an egress side and an ingress side; the ingress side is respectively connected to several group ingress modules outside the device; the egress side is respectively connected to several group egress modules outside the device; in the device, the ingress side is connected to an ingress arbitration module; the egress side is connected to an egress arbitration module; the ingress arbitration module is connected to the egress arbitration module through a scheduling module: the scheduling device also includes a flow control module: the flow control module is used to obtain a credit value on the egress side of the device; the credit value is used to indicate the available cache space on the egress side; the ingress arbitration module is used to perform order-preserving scheduling on the target data received by the group ingress module and schedule the ingress port in the group ingress module according to the credit value; the scheduling module is used to perform inter-module scheduling on several ingress arbitration modules; the egress arbitration module is used to receive the inter-module scheduling result of the scheduling module, and send the target data to the egress port of the group egress module through the egress side according to the inter-module scheduling result.

[0007] In an embodiment of the present invention, the device includes a flow control module, an inlet arbitration module, a scheduling module and an outlet arbitration module. The inlet arbitration module obtains the credit value of the outlet side of the device through the flow control module, and performs order-preserving scheduling and port scheduling on the received target data according to the credit value; after the scheduling module performs inter-module scheduling on several inlet arbitration modules, the outlet arbitration module sends the target data to the outlet port of the group outlet module through the outlet side according to the scheduling results between modules. Scheduling the target data according to the cache situation on the outlet side can ensure that the scheduled data has corresponding cache space at the outlet, and the intermediate scheduling no longer considers the problem of back pressure, thereby solving the head-of-line blocking problem in scheduling.

[0008] In an optional implementation, the flow control module is further configured to: stop scheduling the target data when the credit value is less than a first threshold.

[0009] In the embodiment of the present invention, when the credit value is less than the first threshold, the flow control module stops scheduling the target data, which can prevent system overload and improve the stability and security of the device.

[0010] In an optional embodiment, the ingress arbitration module includes an order-preserving scheduling unit, a type determination unit and an inter-port scheduling unit, wherein: the order-preserving scheduling unit is used to obtain a credit value, and when the credit value is not less than a first threshold, perform order-preserving scheduling on the target data received by the ingress port in the group ingress module; the type determination unit is used to determine the target data type corresponding to each ingress port according to the order-preserving scheduling result; the inter-port scheduling unit is used to schedule the ingress ports in the group ingress module based on the target data type.

[0011] In the embodiment of the present invention, when the credit value is not less than the first threshold, the target data received by the inlet port is firstly scheduled to maintain order, and then the data type corresponding to each inlet port is determined according to the result of the scheduling to perform scheduling between the inlet ports. The possibility of head-of-line blocking and delay can be reduced to improve system performance.

[0012] In an optional embodiment, the entry arbitration module also includes an acceleration ratio acquisition unit and a correspondence confirmation unit, wherein: the acceleration ratio acquisition unit is used to obtain the acceleration ratio information of the scheduling module; the correspondence confirmation unit is used to confirm the correspondence between the exit arbitration module and the cross switch in the scheduling module based on the acceleration ratio information; wherein the acceleration ratio information represents the ratio of the same time of parallel execution to serial transmission in the scheduling module.

[0013] In the embodiment of the present invention, the corresponding relationship between the egress arbitration module and the cross switch in the scheduling module is determined according to the acceleration ratio information, so that the data transmission efficiency and resource utilization can be improved.

[0014] In an optional embodiment, the scheduling module includes a queue construction unit, a target acquisition unit and an inter-module scheduling unit, wherein: the queue construction unit is used to construct several virtual queues, wherein the virtual queues correspond to the export arbitration modules; the target acquisition unit is used to receive target data sent by several import arbitration modules and obtain the target export arbitration module of the target data; the inter-module scheduling unit is used to store the target data to the target virtual queue according to the target export arbitration module to complete the scheduling between modules.

[0015] In an embodiment of the present invention, by receiving target data sent by several inlet arbitration modules and storing the target data in a target virtual queue corresponding to the target outlet arbitration module, the queuing delay during data transmission can be reduced to avoid head-of-line blocking problems that may occur in a shared queue.

[0016] In a second aspect, the present invention provides a non-blocking crossbar scheduling method in PCIe, the method comprising: obtaining target data of several inlet ports in a group inlet module; obtaining a credit value on the device outlet side, and according to the credit value, performing order-preserving scheduling on the target data received by the group inlet module, and scheduling the inlet port of the group inlet module; wherein the credit value is used to indicate the available cache space on the device outlet side; performing inter-module scheduling on several inlet arbitration modules, and according to the inter-module scheduling result, sending the target data to the outlet port of the group outlet module through the device outlet side.

[0017] In an optional embodiment, the target data received by the group entry module is scheduled in an order-preserving manner based on the credit value, and the entry port of the group entry module is scheduled including: obtaining the credit value, and if the credit value is not less than a first threshold, scheduling the target data received by the entry port in the group entry module in an order-preserving manner; determining the target data type based on the order-preserving scheduling results of each entry port; and scheduling the entry port of the group entry module based on the target data type of each entry port.

[0018] In an optional embodiment, inter-module scheduling of several inlet arbitration modules includes: constructing several virtual queues, where the virtual queues correspond to the outlet arbitration modules; receiving target data sent by several inlet arbitration modules, and obtaining the target outlet arbitration module of the target data; according to the target outlet arbitration module, storing the target data in the target virtual queue to complete the inter-module scheduling.

[0019] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute a non-blocking crossbar scheduling method in PCIe according to the second aspect or any corresponding embodiment thereof.

[0020] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a non-blocking crossbar scheduling method in PCIe according to the second aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 is a structural schematic diagram of a non-blocking crossbar scheduling device in PCIe according to an embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of connection between a scheduling module, an inlet arbitration module and an outlet arbitration module according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of a cross switch connection according to an embodiment of the present invention;

[0025] Figure 4 is a structural diagram of an inlet arbitration module according to an embodiment of the present invention;

[0026] Figure 5 It is a flow chart of a non-blocking crossbar scheduling method in PCIe according to an embodiment of the present invention;

[0027] Figure 6 is a flow chart of another non-blocking crossbar scheduling method in PCIe according to an embodiment of the present invention;

[0028] Figure 7 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0030] The PCIe protocol contains three types of messages: p (posted), cpl (completion), and np (non-posted). There is an order relationship between these three types of messages, and they can surpass each other. For example, np messages and cpl messages can surpass blocked p messages through specific enable switches and message identifiers. Therefore, when p messages are blocked, np messages and cpl messages are not blocked, and the head-of-line blocking problem in scheduling needs to be considered.

[0031] In a PCIe switch, it is necessary to ensure that the three types of messages, p, cpl, and np, within the same port will not block each other, ports within the same group will not block each other, and ports in different groups will not block each other.

[0032] In related technologies, virtual output queue technology is usually used or the acceleration ratio is increased in scheduling to schedule messages within a port, between ports in the same group, and between different groups. Among them, if the virtual output queue technology is used directly in each group, the resource consumption is too large. In an actual application, there are N groups in PCIe, each group has 8 ports, and can receive data of three types of messages, then (8*3)*N queues need to be set. N groups require 24N 2During the scheduling process, the scheduling results may not be output due to the back pressure at the egress, blocking the scheduling of other queues.

[0033] Common methods to increase the speedup ratio in scheduling include placing messages with different destinations in different caches, and when scheduling messages for one destination, using the same scheduling structure to start scheduling and transmitting messages for another destination in parallel. However, this will increase the data line width for data exchange, and there will be congestion problems in the wiring under a certain area.

[0034] An embodiment of the present invention provides a non-blocking crossbar scheduling device in PCIe, and the device includes a flow control module, an inlet arbitration module, a scheduling module and an outlet arbitration module. The inlet arbitration module obtains the credit value of the device outlet side through the flow control module, and performs order-preserving scheduling and port scheduling on the received target data according to the credit value; after the scheduling module performs inter-module scheduling on several inlet arbitration modules, the outlet arbitration module sends the target data to the outlet port of the group outlet module through the outlet side according to the scheduling results between modules. Scheduling the target data according to the cache situation on the outlet side can ensure that the scheduled data has corresponding cache space at the outlet, thereby solving the head-of-line blocking problem in scheduling.

[0035] In this embodiment, a non-blocking crossbar scheduling device in PCIe is provided, and the device includes an egress side and an ingress side; the ingress side is respectively connected to several group ingress modules outside the device; the egress side is respectively connected to several group egress modules outside the device; in the device, the ingress side is connected to an ingress arbitration module; the egress side is connected to an egress arbitration module; the ingress arbitration module is connected to the egress arbitration module through a scheduling module: the scheduling device also includes a flow control module, wherein the group ingress module and the group egress module each include several ports.

[0036] Figure 1 is a structural diagram of a non-blocking crossbar scheduling device in PCIe according to an embodiment of the present invention, such as Figure 1As shown, the Group_0 entry module to the Group_N-1 entry module represent N group entry modules, which are used to send data to Crossbar. Crossbar represents a non-blocking crossbar scheduling device in PCIe, including a flow control module, N entry arbitration modules, a scheduling module and N exit arbitration modules. After receiving the target data transmitted by the group entry module, the entry arbitration module needs to send a credit query to the flow control module, and according to the credit query result, schedule the data in the target data port and the data between ports, and update the credit information in the flow control module according to the result of the data scheduling, wherein the credit information represents the available cache space on the exit side of the device. After the entry arbitration module schedules the target data in the port and between ports, the scheduled target data is sent to the scheduling module for scheduling between modules. After the scheduling between modules, the scheduling result between modules is sent to the corresponding exit arbitration module to send the target data to the exit port of the group exit module through the exit side. After the exit arbitration module sends the target data to the corresponding group exit module, the group exit module sends a signal to the flow control module to recover the credit and update the credit information in the flow control module.

[0037] In an actual application, the group entry module is used to process messages of several ports connected to the group, query routing information, extract information, etc.

[0038] In a practical application, the group export module is used to process the messages on the export side of the device and transmit the corresponding data to the corresponding export port.

[0039] The flow control module is used to obtain the credit value on the egress side of the device; the credit value is used to indicate the available cache space on the egress side.

[0040] The flow control module may obtain the available cache space on the device outlet side by reading the data in the cache register on the device outlet side.

[0041] The user can determine the credit value on the export side of the flow control module according to the actual situation to avoid the problem of computing resource overflow.

[0042] In some optional embodiments, the flow control module manages the cache situation on the device outlet side, and based on the cache situation, initiates corresponding scheduling in the inlet arbitration module, and applies for the cache occupancy on the device outlet side based on the scheduling result, and updates the credit value in the flow control module, wherein, if the scheduling result is to go to the first group of outlet modules, the credit corresponding to the first group of outlet modules is reduced in the flow control module; if the first group of outlet modules has already sent the received data, the credit value is recovered and updated in the flow control module.

[0043] After the cache on the egress side of the device is occupied at the ingress side of the device, the space on the egress side can be used to accommodate scheduled messages.

[0044] The inlet arbitration module is used to schedule the target data received by the group inlet module in order according to the credit value, and schedule the inlet ports in the group inlet module.

[0045] Among them, the input arbitration module is connected to the group input module and receives the data transmitted by the group input module. After receiving the data transmitted by the group input module, it needs to communicate with the flow control module to obtain the credit value on the device outlet side and determine whether there is enough cache space on the outlet side to avoid data packet loss.

[0046] When the credit value is less than the target threshold, there is not enough buffer space on the egress side and data cannot be scheduled. The ingress arbitration module needs to stop scheduling data.

[0047] When the credit value is not less than the target threshold, there is enough cache space on the egress side to schedule data. First, the data in the port of the group entry module is scheduled in order, and then the ports of the group entry module are scheduled. Among them, the order-preserving scheduling needs to comply with the order requirements specified in the PCIe protocol to avoid deadlock and other conditions in data transmission, which affects the data transmission efficiency. Among them, the target threshold can be determined by the staff according to the actual situation.

[0048] After the group inlet module completes the inter-port scheduling, it can determine the first cache space required for the target data based on the inter-port scheduling result, and update the credit value in the flow control module based on the first cache space to complete the occupation of the cache space on the egress side.

[0049] In a practical application, a queue needs to be established to store the target data to be scheduled in the corresponding inlet port. For each target data entering the queue, its message type and queue entry order are recorded; then, according to the message type at the head of the queue and the provisions on the message order in the PCIe protocol, the target data is scheduled in order within the port, and the first message type of the inlet port is determined according to the order-preserving scheduling result. Based on the first message type of the inlet port in the group inlet module, the inlet port in the group inlet module is scheduled.

[0050] In an actual application, the PCIe protocol stipulates the order of messages as follows: p messages can surpass cpl messages and np messages, cpl messages and np messages can surpass p messages in the scenarios specified by the protocol, and cpl messages and np messages are allowed to surpass each other.

[0051] After the inlet arbitration module completes the order-preserving scheduling of the target data and the scheduling between the inlet ports, it can determine the cache required for the target data scheduling based on the scheduling results, and update the credit value of the flow control module based on the cache required for the target data scheduling to complete the cache space occupancy on the egress side.

[0052] The scheduling module is used to perform inter-module scheduling on several entry arbitration modules.

[0053] Among them, the inter-module scheduling can select a suitable VOQ (virtual output queue) scheduling algorithm according to different target data to schedule several inlet arbitration modules between modules, wherein the VOQ scheduling algorithm can be PIM (Protocol Independent Multicast), iSLIP (Iterative Round-Robin Matching with Slip), RPA (Round-Robin Scheduling Algorithm), FIRM (First-Come, First-Served in Round-Robin Matching) or DRRM (Dual Round-Robin Matching) and other algorithms.

[0054] The scheduling module can obtain several sub-cross switches by splitting the cross switch. The sub-cross switches can process information in parallel, thereby reducing the timing complexity of the scheduling, increasing the speedup ratio, and alleviating the back-end winding pressure. The number of sub-cross switches and the connection relationship between the sub-cross switches and the inlet arbitration module and the outlet arbitration module can be determined by the system's speedup ratio requirements, the number of switching orders, etc.

[0055] In some optional embodiments, the switching order of the device is N, that is, the device connects N group inlet modules and N group outlet modules, and the device includes N inlet arbitration modules and N outlet arbitration modules. The switching plane is N*N. The acceleration ratio is A, and the switching plane can be divided into A*B sub-switching planes, where A and B are both factors of N. One sub-switching plane corresponds to M group inlet modules and group outlet modules, and the switching size of the sub-plane is (A*M)*(B*M).

[0056] In an actual application, the switching order of the device is 12, that is, there are 12 inlet arbitration modules and 12 outlet arbitration modules, the speedup ratio is 2, and the scheduling module is divided into 4 submodules, one submodule corresponds to 3 groups, and the size of the final 4 submodules is 6*6, where the size of the submodule is (the product of the speedup ratio and the number of groups corresponding to the submodule)*((the number of submodules / speedup ratio)*the number of groups corresponding to the submodule). The connection relationship between the cross switch in the scheduling module and the inlet arbitration module and the outlet arbitration module is as follows: Figure 2 As shown in . Group0 inlet arbitration module - Group11 inlet arbitration module represent the inlet arbitration module of the device, Group0 outlet arbitration module - Group11 outlet arbitration module represent the outlet arbitration module of the device; Xbar0 - Xbar3 represent four cross switches; In_0 - In_5 in the cross switch represent 6 input ports, which are used to connect with the corresponding outlet arbitration module and receive the data transmitted by the inlet arbitration module; Out_0 - Out_5 represent the six output ports of the cross switch, which are used to connect with the corresponding outlet arbitration module. Group0 inlet arbitration module corresponds to xbar0 and xbar1. If the data of Group0 inlet arbitration module needs to go to any inlet arbitration module of Group0 outlet arbitration module - Group2 outlet arbitration module and Group6 outlet arbitration module - Group8 outlet arbitration module, the data in Group0 inlet arbitration module is sent to Xbar0. If the data of Group0 inlet arbitration module needs to go to any inlet arbitration module of Group3 outlet arbitration module - Group5 outlet arbitration module and Group9 outlet arbitration module - Group11 outlet arbitration module, the data in Group0 inlet arbitration module is sent to Xbar1.

[0057] In some optional embodiments, on the input side of the cross switch, each input port includes a first number of virtual output queues, and the virtual output queues are numbered according to the egress arbitration modules corresponding to the virtual output queues, wherein the first number is the number of corresponding egress arbitration modules, and virtual output queues with the same number correspond to the same egress arbitration module; on the output side, even-numbered outputs correspond to M egress arbitration modules on the input side, and odd-numbered outputs correspond to another M egress arbitration modules, and the connection relationship within the cross switch can be determined according to the size of the sub-switching plane.

[0058] The connection relationship within the cross switch is as follows Figure 3As shown, a 6×6 cross switch, In_0-In_5 in the cross switch represents 6 input ports, which are used to connect with the corresponding egress arbitration modules and receive data transmitted by the ingress arbitration modules, wherein six VOQ queues are set in each input port, wherein VOQ_0-VOQ_5 represent 6 virtual output queues; virtual output queues with the same number correspond to the same egress arbitration module, and Out_0-Out_5 represent six output ports of the cross switch, which are used to connect with the corresponding egress arbitration modules.

[0059] In a practical application, an input port includes several VOQs. The same input port can initiate requests to multiple output port modules; the same output port arbitrates different input ports. According to the arbitration result of the output port, the VOQ in the input port is arbitrated again at the input port. Through two arbitrations, more reasonable resource allocation can be achieved.

[0060] Among them, the VOQ scheduling in the scheduling module does not need to consider the head-of-line blocking problem and can achieve non-blocking switching.

[0061] The export arbitration module is used to receive the inter-module scheduling result of the scheduling module, and send the target data to the export port of the group export module through the export side according to the inter-module scheduling result.

[0062] After receiving the inter-module scheduling result from the scheduling module, the export arbitration module needs to analyze the inter-module scheduling result to determine the correspondence between the target data and the export port of the group export module. Then, according to the correspondence, the target data is transmitted to the corresponding export port to complete the transmission of the target data.

[0063] After the target data is sent to the egress port of the group egress module through the egress side, a signal may be sent to the flow control module to update the credit value in the flow control module.

[0064] The present embodiment provides a non-blocking crossbar scheduling device in PCIe, and the device includes a flow control module, an inlet arbitration module, a scheduling module, and an outlet arbitration module. The inlet arbitration module obtains the credit value of the device outlet side through the flow control module, and performs order-preserving scheduling and port scheduling on the received target data according to the credit value; after the scheduling module performs inter-module scheduling on several inlet arbitration modules, the outlet arbitration module sends the target data to the outlet port of the group outlet module through the outlet side according to the scheduling results between modules. Scheduling the target data according to the cache situation on the outlet side can ensure that the scheduled data has corresponding cache space at the outlet, and the intermediate scheduling no longer considers the problem of back pressure, thereby solving the head-of-line blocking problem in scheduling.

[0065] In this embodiment, a non-blocking crossbar scheduling device in PCIe is provided, the device includes an egress side and an ingress side; the ingress side is respectively connected to a plurality of group ingress modules outside the device; the egress side is respectively connected to a plurality of group egress modules outside the device; in the device, the ingress side is connected to an ingress arbitration module; the egress side is connected to an egress arbitration module; the ingress arbitration module is connected to the egress arbitration module through a scheduling module; the scheduling device also includes a flow control module:

[0066] The flow control module is used to obtain the credit value on the egress side of the device; the credit value is used to indicate the available cache space on the egress side.

[0067] For details, please see Figure 1 The flow control module of the illustrated embodiment will not be described in detail here.

[0068] In some optional implementations, the flow control module is further configured to: stop scheduling the target data when the credit value is less than a first threshold.

[0069] When the credit value is less than the first threshold, the flow control module stops scheduling the target data, thereby preventing the system from being overloaded and improving the stability and safety of the device.

[0070] An inlet arbitration module, used to schedule the target data received by the group inlet module in order according to the credit value, and schedule the inlet ports in the group inlet module;

[0071] The ingress arbitration module includes an order-preserving scheduling unit, a type determination unit, and an inter-port scheduling unit:

[0072] The order-preserving scheduling unit is used to obtain a credit value, and when the credit value is not less than a first threshold, perform order-preserving scheduling on target data received by an ingress port in the group ingress module.

[0073] After receiving the target data, the order-preserving scheduling unit may send a credit query request to the flow control module to obtain a credit value. And determine the relationship between the credit value and the first threshold. If the credit value is less than the first threshold, the scheduling of the target data may be stopped. If the credit value is not less than the first threshold, the queueing order and data type of the data in the target data are received and recorded, and then the target data is scheduled in an order-preserving manner according to the order requirements specified in the PCIe protocol.

[0074] The type determination unit is used to determine the target data type corresponding to each ingress port according to the order-preserving scheduling result.

[0075] Among them, after obtaining the order-preserving scheduling result of the entry port in the group entry module, the data type of the first data in the order-preserving scheduling result can be used as the target data type, or the data type with the largest number in the target data can be used as the target data type.

[0076] The inter-port scheduling unit is used to schedule the ingress ports within the group ingress module based on the target data type.

[0077] After obtaining the target data type corresponding to the inlet port in the group inlet module, the target data type of the inlet port in the group inlet module can be polled or weighted.

[0078] In a practical application, a weight value is assigned to each port in the group entry module, where the weight value can be set by the staff according to the priority of the entry port; the polling counter of each entry port is initialized according to the weight value of each port, and then in each scheduling cycle, the corresponding polling counter value is increased according to the weight value of the port, and the entry port with the highest counter value is selected for data transmission, and the corresponding data is sent to the scheduling module. After the sending is completed, the polling counter value of the port is reset, and the next port is polled.

[0079] In a practical application, the entry arbitration module is as follows Figure 4 As shown, the entry arbitration module includes n order-preserving scheduling units, the number of which is the same as the number of entry ports of the group entry module corresponding to the entry arbitration module, and the structures of the order-preserving scheduling units are the same. Port_0 represents the order-preserving scheduling unit corresponding to the first entry port in the group entry module. Port_n-1 represents the order-preserving scheduling unit corresponding to the nth entry port in the group entry module. After Port_0 receives the data information transmitted by the first entry port in the group entry module, it reads the control information sent by the credit control component, and determines whether to perform order-preserving scheduling processing on the received data information based on the control information. Among them, the credit control component obtains credit information, and generates control information based on the credit information to control whether the order-preserving scheduling component schedules the data information, and the credit information is the cache space on the exit side.

[0080] When the control information is to allow scheduling, the data information is processed 1to3, where 1to3 represents dividing a group of data information into three queues of p, cpl, and np according to different message types; the three queues all send requests to the order-preserving scheduling component to perform order-preserving scheduling processing on the port data.

[0081] After the order-preserving scheduling process is completed, the reference message type corresponding to the ingress port is determined according to the order-preserving scheduling result; then a request message containing the reference message type is generated and sent to the Port scheduling unit to perform scheduling between ingress ports and generate the arbitration result of the ingress arbitration module. After the Port scheduling unit obtains the reference message type of the target ingress port in the ingress arbitration module, it can perform weighted polling on the target ingress port to obtain the arbitration result.

[0082] In an actual application, the reference message type is the message type of the first message in the queue obtained after the data information is scheduled in order.

[0083] In some optional implementations, the entry arbitration module further includes a speedup ratio acquisition unit and a corresponding relationship confirmation unit, wherein:

[0084] The acceleration ratio acquisition unit is used to obtain the acceleration ratio information of the scheduling module.

[0085] The acceleration ratio information can be directly obtained according to the system's acceleration ratio requirements for the scheduling module.

[0086] The corresponding relationship confirmation unit is used to confirm the corresponding relationship between the export arbitration module and the cross switch in the scheduling module based on the acceleration ratio information; wherein the acceleration ratio information represents the ratio of the same parallel execution time to serial transmission in the scheduling module.

[0087] The speedup ratio refers to the use of parallel processing or a specific scheduling algorithm to improve the efficiency of task execution, which is characterized by the ratio of the same time of parallel execution in the scheduling module to serial transmission. When the speedup ratio is 1, no acceleration processing is performed. When the speedup ratio is greater than 1, the cross switch connected to the target output address of the target data is determined according to the target output address of the target data. Then the entry arbitration module can send the target data to the corresponding cross switch for inter-module scheduling.

[0088] like Figure 2 As shown, one inlet arbitration module corresponds to two cross switches, and the two cross switches can process the scheduling of the corresponding outlet target data in parallel. There is a certain degree of parallelism in the entire scheduling, so a certain speedup ratio can also be achieved in the scheduling.

[0089] According to the acceleration ratio information, the corresponding relationship between the export arbitration module and the cross switch in the scheduling module is determined, which can improve the data transmission efficiency and resource utilization.

[0090] A scheduling module, used for inter-module scheduling of several entry arbitration modules;

[0091] For details, please see Figure 1 The scheduling module of the illustrated embodiment will not be described in detail here.

[0092] The export arbitration module is used to receive the inter-module scheduling result of the scheduling module, and send the target data to the export port of the group export module through the export side according to the inter-module scheduling result.

[0093] For details, please see Figure 1 The export arbitration module of the illustrated embodiment will not be described in detail here.

[0094] The non-blocking crossbar scheduling device in PCIe provided in this embodiment first performs order-preserving scheduling on the target data received by the inlet port when the credit value is not less than the first threshold value, and then determines the data type corresponding to each inlet port according to the order-preserving scheduling result to perform scheduling between inlet ports. The possibility of head-of-line blocking problems can be reduced, delays can be reduced, and system performance can be improved. Among them, the VOQ scheduling algorithm is not applicable to the order-preserving scheduling of target data and the scheduling between inlet ports. The use of the VOQ scheduling algorithm in scheduling between modules can increase the scheduling throughput and reduce the use of cache.

[0095] In this embodiment, a non-blocking crossbar scheduling device in PCIe is provided, the device includes an egress side and an ingress side; the ingress side is respectively connected to a plurality of group ingress modules outside the device; the egress side is respectively connected to a plurality of group egress modules outside the device; in the device, the ingress side is connected to an ingress arbitration module; the egress side is connected to an egress arbitration module; the ingress arbitration module is connected to the egress arbitration module through a scheduling module; the scheduling device also includes a flow control module:

[0096] A flow control module, used to obtain a credit value on the outlet side of the device; the credit value is used to indicate the available cache space on the outlet side;

[0097] For details, please see Figure 1 The flow control module of the illustrated embodiment will not be described in detail here.

[0098] An inlet arbitration module, used to schedule the target data received by the group inlet module in order according to the credit value, and schedule the inlet ports in the group inlet module;

[0099] For details, please see Figure 1 The inlet arbitration module of the illustrated embodiment will not be described in detail here.

[0100] A scheduling module, used for inter-module scheduling of several entry arbitration modules;

[0101] Among them, the scheduling module includes a queue construction unit, a target acquisition unit, and an inter-module scheduling unit:

[0102] The queue construction unit is used to construct a plurality of virtual queues, wherein the virtual queues correspond to the egress arbitration modules.

[0103] The number of egress arbitration modules connected to the crossbar switch in the scheduling module is obtained, and the same number of virtual queues are constructed according to the number of egress arbitration modules.

[0104] In an actual application, the cross switch in the scheduling module connects six egress arbitration modules, and six virtual queues need to be constructed.

[0105] The target acquisition unit is used to receive target data sent by several input arbitration modules and acquire the target output arbitration module of the target data.

[0106] The inter-module scheduling unit is used to store the target data into the target virtual queue according to the target export arbitration module to complete the scheduling between modules.

[0107] After receiving the target data sent by the inlet arbitration module, the target export arbitration module of the target data is obtained, and according to the target export arbitration module of the target data, the target data is placed in the virtual queue corresponding to the target export arbitration unit to complete the scheduling between modules. This reduces the problem that other queues cannot send data due to blocking in one queue.

[0108] The export arbitration module is used to receive the inter-module scheduling result of the scheduling module, and send the target data to the export port of the group export module through the export side according to the inter-module scheduling result.

[0109] For details, please see Figure 1 The export arbitration module of the illustrated embodiment will not be described in detail here.

[0110] The non-blocking crossbar scheduling device in PCIe provided in this embodiment can reduce the queuing delay during data transmission by receiving target data sent by several inlet arbitration modules and storing the target data in the target virtual queue corresponding to the target outlet arbitration module, so as to avoid the head-of-line blocking problem that may occur in the shared queue.

[0111] The non-blocking crossbar scheduling device in PCIe in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0112] According to an embodiment of the present invention, an embodiment of a non-blocking crossbar scheduling method in PCIe is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0113] In this embodiment, a non-blocking crossbar scheduling method in PCIe is provided. Figure 5 is a flowchart of a non-blocking crossbar scheduling method in PCIe according to an embodiment of the present invention. Figure 5 As shown, the process includes the following steps:

[0114] Step S101, obtaining target data of several inlet ports in a group inlet module.

[0115] The target data may include three types of messages, namely, p messages, np messages and cpl messages. After receiving the target data, it is necessary to obtain the available cache space on the device egress side to determine whether the target data can be scheduled to avoid head-of-line blocking.

[0116] Step S102, obtaining the credit value on the device egress side, and scheduling the target data received by the group inlet module in order and scheduling the inlet port of the group inlet module according to the credit value; wherein the credit value is used to indicate the available cache space on the device egress side.

[0117] After obtaining the target data of several inlet ports in the group inlet module, the target data needs to be parsed to determine the target group outlet module of the target data. Then, the credit value of the corresponding group outlet module in the device outlet side is obtained by accessing the flow control module.

[0118] When the credit value is less than the first threshold, that is, when the cache space of the corresponding group egress module is insufficient, the scheduling of the target data is stopped.

[0119] When the credit value is not less than the first threshold, that is, the cache space of the corresponding group egress module is sufficient, the target data is scheduled in order, and the ingress port of the group ingress module is scheduled according to the result of the order-preserving scheduling. The ingress port scheduling of the group ingress module can use polling, weighted polling, etc. After the scheduling is completed, the scheduling result needs to be sent to the target cross switch in the scheduling module, wherein the target cross switch is the cross switch of the group egress module connected to the target data.

[0120] Step S103, performing inter-module scheduling on a plurality of inlet arbitration modules, and sending the target data to the egress port of the group egress module through the device egress side according to the inter-module scheduling result.

[0121] After obtaining the target data of several inlet arbitration modules, algorithms such as PIM, iSLIP, RPA, FIRM and DRRM can be used to schedule the inlet arbitration modules among modules. Then, according to the scheduling results among modules, the target data is sent to the egress port of the corresponding group of egress modules.

[0122] When the scheduling module includes multiple cross switches, it is easy for multiple cross switches to send data to the same group egress module. The egress arbitration module needs to aggregate and sort the acquired data and transmit the data according to the sorting result. The data can be sorted by weight sorting or other methods.

[0123] The non-blocking crossbar scheduling method in PCIe provided in this embodiment obtains the credit value on the device outlet side to determine the cache situation on the device outlet side after receiving the target data of several inlet ports in the group inlet module, and then schedules the target data according to the cache situation on the outlet side. This can ensure that the scheduled data has corresponding cache space at the outlet, thereby solving the head-of-line blocking problem in scheduling.

[0124] In this embodiment, a non-blocking crossbar scheduling method in PCIe is provided. Figure 6 is a flowchart of a non-blocking crossbar scheduling method in PCIe according to an embodiment of the present invention. Figure 6 As shown, the process includes the following steps:

[0125] Step S201, obtaining target data of several inlet ports in the group inlet module.

[0126] For details, please see Figure 5 Step S101 of the illustrated embodiment will not be described in detail here.

[0127] Step S202, obtaining the credit value on the device export side, and scheduling the target data received by the group entry module in order according to the credit value, and scheduling the entry port of the group entry module; wherein the credit value is used to indicate the available cache space on the device export side.

[0128] Specifically, the above step S202 includes:

[0129] Step S2021, obtaining a credit value, and when the credit value is not less than a first threshold, performing order-preserving scheduling on the target data received by the ingress port in the group ingress module.

[0130] When the credit value is not less than the first threshold, it indicates that the available cache space on the device egress side can meet the cache occupancy required for data scheduling. The target data received by the ingress port in the group ingress module can be scheduled in order. The order is the order specified in the PCIe protocol.

[0131] In some optional implementations, when the credit value is less than a first threshold, scheduling of the target data is stopped.

[0132] Step S2022: Determine the target data type according to the order-preserving scheduling results of each ingress port.

[0133] After obtaining the order-preserving scheduling results of each ingress port, the data type of the first data in the order-preserving scheduling results may be used as the target data type.

[0134] Step S2023, scheduling the inlet ports of the group inlet module according to the target data type of each inlet port.

[0135] After obtaining the target data type of each inlet port, the target data type of the inlet port in the group inlet module can be polled or weighted.

[0136] In some optional implementations, step S202 further includes:

[0137] Step S2024, obtaining acceleration ratio information.

[0138] The acceleration ratio information can be directly obtained according to the system's acceleration ratio requirements for the scheduling module.

[0139] Step S2025, based on the acceleration ratio information, confirm the correspondence between the egress arbitration module and the cross switch in the scheduling module, wherein the acceleration ratio information represents the ratio of the same parallel execution time to the serial transmission in the scheduling module.

[0140] When the acceleration ratio is 1, no acceleration processing is performed. When the acceleration ratio is greater than 1, the crossbar switch connected to the target output address of the target data is determined according to the target output address of the target data. Then the entry arbitration module can send the target data to the corresponding crossbar switch for inter-module scheduling.

[0141] Step S203, performing inter-module scheduling on a plurality of inlet arbitration modules, and sending the target data to the egress port of the group egress module through the device egress side according to the inter-module scheduling result.

[0142] For details, please see Figure 5 Step S103 of the illustrated embodiment will not be described in detail here.

[0143] In some optional implementations, the above step S203 includes:

[0144] Step S2031, constructing several virtual queues, wherein the virtual queues correspond to the egress arbitration modules.

[0145] The number of egress arbitration modules connected to the crossbar switch in the scheduling module is obtained, and the same number of virtual queues are constructed according to the number of egress arbitration modules.

[0146] Step S2032, receiving target data sent by a plurality of inlet arbitration modules, and obtaining a target outlet arbitration module of the target data.

[0147] The target data is parsed to obtain a target export arbitration module of the target data.

[0148] Step S2033: According to the target egress arbitration module, the target data is stored in the target virtual queue to complete the scheduling between modules.

[0149] According to the target export arbitration module, the target data is stored in the target virtual queue corresponding to the target export arbitration module, so as to complete the scheduling of the target data among the modules.

[0150] The non-blocking crossbar scheduling method in PCIe provided in this embodiment first performs order-preserving scheduling on the target data received by the ingress port when the credit value is not less than the first threshold, and then determines the data type corresponding to each ingress port according to the order-preserving scheduling result to perform scheduling between the ingress ports. The possibility of head-of-line blocking problem can be reduced, delay can be reduced, and system performance can be improved.

[0151] The embodiment of the present invention also provides a computer device having the above Figure 1 A non-blocking crossbar scheduling arrangement in PCIe is shown.

[0152] See also Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0153] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0154] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0155] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0156] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0157] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0158] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0159] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0160] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0161] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A non-blocking crossbar scheduling device in PCIe, characterized in that: The device includes an outlet side and an inlet side; the inlet side is respectively connected to a plurality of inlet modules outside the device; the outlet side is respectively connected to a plurality of outlet modules outside the device; in the device, the inlet side is connected to an inlet arbitration module; the outlet side is connected to an outlet arbitration module; the inlet arbitration module is connected to the outlet arbitration module through a scheduling module; the scheduling device also includes a flow control module: The flow control module is used to obtain a credit value on the outlet side of the device; the credit value is used to indicate the available cache space on the outlet side; The ingress arbitration module is used to schedule the target data received by the group ingress module in order according to the credit value, and schedule the ingress ports in the group ingress module; The scheduling module is used to perform inter-module scheduling on a plurality of inlet arbitration modules; The egress arbitration module is used to receive the inter-module scheduling result of the scheduling module, and send the target data to the egress port of the group egress module through the egress side according to the inter-module scheduling result.

2. The device according to claim 1, characterized in that The flow control module is further configured to: stop scheduling the target data when the credit value is less than a first threshold.

3. The device according to claim 2, characterized in that The ingress arbitration module includes an order-preserving scheduling unit, a type determination unit, and an inter-port scheduling unit, wherein: The order-preserving scheduling unit is used to obtain the credit value, and when the credit value is not less than a first threshold, perform order-preserving scheduling on the target data received by the ingress port in the group of ingress modules; The type determination unit is used to determine the target data type corresponding to each ingress port according to the order-preserving scheduling result; The inter-port scheduling unit is used to schedule the ingress ports in the group ingress module based on the target data type.

4. The device according to any one of claims 1 to 3, characterized in that: The entry arbitration module further includes a speedup ratio acquisition unit and a corresponding relationship confirmation unit, wherein: The acceleration ratio acquisition unit is used to acquire the acceleration ratio information of the scheduling module; The correspondence confirmation unit is used to confirm the correspondence between the egress arbitration module and the cross switch in the scheduling module based on the acceleration ratio information; wherein the acceleration ratio information represents the ratio of the same parallel execution time to serial transmission in the scheduling module.

5. The device according to any one of claims 1 to 3, characterized in that: The scheduling module includes a queue construction unit, a target acquisition unit and an inter-module scheduling unit, wherein: The queue construction unit is used to construct a plurality of virtual queues, wherein the virtual queues correspond to the egress arbitration modules; The target acquisition unit is used to receive target data sent by a plurality of inlet arbitration modules and acquire a target outlet arbitration module of the target data; The inter-module scheduling unit is used to store the target data into the target virtual queue according to the target egress arbitration module to complete the inter-module scheduling.

6. A non-blocking crossbar scheduling method in PCIe, applied to the non-blocking crossbar scheduling device in PCIe as claimed in any one of claims 1 to 5, characterized in that: The method comprises: Obtaining target data of a plurality of inlet ports in the group of inlet modules; Acquire a credit value on the device egress side, and according to the credit value, perform order-preserving scheduling on the target data received by the group ingress module, and schedule the ingress port of the group ingress module; wherein the credit value is used to indicate the available cache space on the device egress side; Inter-module scheduling is performed on a plurality of inlet arbitration modules, and according to the inter-module scheduling result, the target data is sent to the outlet port of the group of outlet modules through the device outlet side.

7. The method according to claim 6, characterized in that The step of performing order-preserving scheduling on the target data received by the group entry module according to the credit value and scheduling the entry port of the group entry module comprises: Acquire the credit value, and when the credit value is not less than a first threshold, perform order-preserving scheduling on the target data received by the ingress port in the group of ingress modules; Determine the target data type based on the order-preserving scheduling results of each ingress port; The ingress ports of the group ingress module are scheduled according to the target data type of each ingress port.

8. The method according to claim 6, characterized in that The inter-module scheduling of a plurality of inlet arbitration modules includes: Constructing a plurality of virtual queues, wherein the virtual queues correspond to the egress arbitration modules; Receiving target data sent by a plurality of input arbitration modules, and obtaining a target output arbitration module of the target data; According to the target egress arbitration module, the target data is stored in a target virtual queue to complete scheduling between modules.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes a non-blocking crossbar scheduling method in PCIe according to any one of claims 6 to 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute a non-blocking crossbar scheduling method in PCIe according to any one of claims 6 to 8.

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