Circuit board and manufacturing method thereof

Abstract

A circuit board comprises an upper circuit structure, a lower circuit structure and a middle circuit structure arranged between the upper circuit structure and the lower circuit structure. The middle line structure comprises a middle shielding structure, a middle power supply conduction part penetrating through the middle shielding structure, a first middle signal conduction part, a second middle signal conduction part, a first middle grounding wire and a second middle grounding wire. The intermediate shielding structure has a first surface and a second surface. The first middle signal conduction part and the first middle grounding wire are arranged on the first surface, and the first middle grounding wire is located between the middle power supply conduction part and the first middle signal conduction part. The second middle signal conduction part and the second middle grounding wire are arranged on the second surface, and the second middle grounding wire is located between the middle power supply conduction part and the second middle signal conduction part. According to the circuit board, the power conduction part and the signal conduction part are designed on the same layer, so that the integration of the circuit board can be improved.

Description

Technical Field

[0001] The invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board in which a power conducting part and a signal conducting part are designed on the same layer and a manufacturing method thereof. Background Art

[0002] In a circuit board, power lines and signal lines are usually located on different layers to reduce the electromagnetic interference of the power lines on the signal lines when working with high currents. Both the power lines and the signal lines need to be grounded to avoid mutual interference, which results in a decrease in the utilization rate of the circuit board wiring and an increase in the wiring space. In addition, if you want to set up multiple groups of signal lines in a circuit board, you also need to increase the number of circuit board layers and set up grounding wires to shield electromagnetic interference. However, as electronic products develop towards lightweight and miniaturization, more and more products require circuit boards with high integration, which limits the number of circuit board layers and makes it difficult to set up enough grounding wires. Summary of the invention

[0003] The object of the present invention is to provide a circuit board in which a power supply conducting part and a signal conducting part are designed on the same layer, so as to improve the integration of the circuit board.

[0004] Another object of the present invention is to provide a method for manufacturing the above-mentioned circuit board to help improve the integration of the above-mentioned circuit board.

[0005] A circuit board proposed in at least one embodiment of the present invention comprises an upper circuit structure, a lower circuit structure and an intermediate circuit structure disposed between the upper circuit structure and the lower circuit structure. The intermediate circuit structure comprises an intermediate shielding structure, a plurality of intermediate power conducting parts, a plurality of first intermediate signal conducting parts, a plurality of second intermediate signal conducting parts, a plurality of first intermediate grounding wires and a plurality of second intermediate grounding wires. The intermediate shielding structure has a first surface and a second surface opposite to the first surface. The plurality of intermediate power conducting parts penetrate the intermediate shielding structure. The plurality of first intermediate signal conducting parts are disposed on the first surface, and the plurality of second intermediate signal conducting parts are disposed on the second surface. The plurality of first intermediate grounding wires are disposed on the first surface and are respectively located between the plurality of intermediate power conducting parts and the plurality of first intermediate signal conducting parts. The plurality of second intermediate grounding wires are disposed on the second surface and are respectively located between the plurality of intermediate power conducting parts and the plurality of second intermediate signal conducting parts.

[0006] In at least one embodiment of the present invention, the plurality of first intermediate signal conducting portions are arranged alternately with the plurality of intermediate power conducting portions, and the plurality of second intermediate signal conducting portions are arranged alternately with the plurality of intermediate power conducting portions.

[0007] In at least one embodiment of the present invention, the upper circuit structure and the lower circuit structure respectively include a shielding structure, a plurality of signal conducting parts and a plurality of grounding wires. The shielding structure has a surface facing away from the intermediate circuit structure. A plurality of power conducting parts penetrate the shielding structure and connect the plurality of intermediate power conducting parts. A plurality of signal conducting parts are arranged on the surface and overlap with the projections of the plurality of first intermediate signal conducting parts and the plurality of second intermediate signal conducting parts in a direction perpendicular to the surface of the shielding structure. A plurality of grounding wires are arranged on the surface and are respectively located between the plurality of power conducting parts and the plurality of signal conducting parts.

[0008] In at least one embodiment of the present invention, the plurality of signal conducting portions and the plurality of power conducting portions are arranged alternately.

[0009] In at least one embodiment of the present invention, the intermediate shielding structure and the shielding structure respectively include an absorbing material layer and a dielectric layer, and the dielectric loss of the dielectric layer is less than 0.004.

[0010] In at least one embodiment of the present invention, the intermediate shielding structure further includes another dielectric layer, and the absorbing material layer is disposed between the two dielectric layers.

[0011] In at least one embodiment of the present invention, the intermediate power conducting portion includes a first metal layer and a second metal layer, and the conductivity of the first metal layer is greater than the conductivity of the second metal layer.

[0012] In at least one embodiment of the present invention, the intermediate power conducting portion further includes another second metal layer, and the first metal layer is disposed between the two second metal layers.

[0013] In at least one embodiment of the present invention, the plurality of first intermediate signal conducting parts, the plurality of second intermediate signal conducting parts, and the plurality of signal conducting parts respectively include a signal line and a cavity, and the signal line is disposed in the cavity.

[0014] In at least one embodiment of the present invention, the thickness of each of the plurality of first intermediate ground lines is greater than the thickness of the signal line of each of the plurality of first intermediate signal conducting parts, the thickness of each of the plurality of second intermediate ground lines is greater than the thickness of the signal line of each of the plurality of second intermediate signal conducting parts, and the thickness of each of the plurality of ground lines is greater than the thickness of the signal line of each of the plurality of signal conducting parts.

[0015] In at least one embodiment of the present invention, the thickness of each of the multiple first intermediate ground lines is not less than twice the thickness of the signal line of each of the multiple first intermediate signal conducting parts, the thickness of each of the multiple second intermediate ground lines is not less than twice the thickness of the signal line of each of the multiple second intermediate signal conducting parts, and the thickness of each of the multiple ground lines is not less than twice the thickness of the signal line of each of the multiple signal conducting parts.

[0016] A method for manufacturing a circuit board according to at least one embodiment of the present invention comprises providing a metal structure, the metal structure comprising a first initial metal layer and two second initial metal layers respectively located on both sides of the first initial metal layer. Patterning the two second initial metal layers to form two second metal layers. Forming a release film on one of the two second metal layers. Patterning the first initial metal layer to form a first metal layer. Forming an intermediate shielding structure on the release film, the intermediate shielding structure having a first surface and a second surface opposite to the first surface and contacting the release film. Forming a plurality of first intermediate signal conducting parts and a plurality of first intermediate grounding wires on the first surface. After forming the plurality of first intermediate signal conducting parts and the plurality of first intermediate grounding wires on the first surface, removing the release film and exposing the second surface. Forming a plurality of second intermediate signal conducting parts and a plurality of second intermediate grounding wires on the second surface. Forming two shielding structures respectively on the plurality of first intermediate signal conducting parts and the plurality of second intermediate signal conducting parts, the two shielding structures respectively having surfaces facing away from the intermediate shielding structure. Forming a plurality of signal conducting parts and a plurality of grounding wires respectively on the two surfaces of the two shielding structures. Forming two build-up structures respectively on the plurality of signal conducting parts and the plurality of grounding wires. After forming two build-up structures on the plurality of signal conducting parts and the plurality of grounding lines respectively, a plurality of through holes are formed to expose the two second metal layers, and a plurality of power conducting parts are formed to fill the plurality of through holes and connect the two second metal layers.

[0017] In at least one embodiment of the present invention, the two second initial metal layers are patterned by acid etching, and the first initial metal layer is patterned by alkaline etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a partial cross-sectional schematic diagram of a circuit board according to at least one embodiment of the present invention;

[0019] Figure 2 is a partial top view schematic diagram of a circuit structure of at least one embodiment of the present invention;

[0020] as well as

[0021] Figures 3A to 3U It is a partial cross-sectional view of a circuit board in different process stages according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0022] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be enlarged in a non-proportional manner, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes and deviations of the two caused by actual processes and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, and the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.

[0023] Secondly, the words "about", "approximately" or "substantially" used in the present invention not only cover the numerical values ​​and numerical ranges clearly recorded, but also cover the permissible deviation range that can be understood by the technicians in the technical field to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and the error is caused by the limitation of the measurement system or process conditions. For example, two objects (such as the planes or traces of the substrate) are "substantially parallel" or "substantially perpendicular", wherein "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects may include the non-parallelism and non-perpendicularity caused by the permissible deviation range.

[0024] The spatially relative terms used in the present invention, such as "below", "under", "above", "on", etc., are for the purpose of facilitating the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped up and down 180 degrees, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in the present invention should also be interpreted in the same way.

[0025] It should be understood that, although the present invention may use the terms "first", "second", "third" and the like to describe various elements or features, these elements or features should not be limited by these terms. These terms are mainly used to distinguish one element from another element, or one feature from another feature. In addition, the term "or" used in the present invention may include any one or more combinations of the associated listed items depending on the actual situation.

[0026] Although a series of operations or steps are utilized in the present invention to illustrate the manufacturing method, the order shown in these operations or steps should not be interpreted as a limitation of the present invention. For example, some operations or steps can be performed in different orders and / or simultaneously with other steps. In addition, each operation or step described herein can include several sub-steps or actions.

[0027] In addition, the present invention may be implemented or applied through other different specific embodiments, and the details of the present invention may also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0028] Figure 1 FIG. 1 is a partial cross-sectional view of a circuit board according to at least one embodiment of the present invention. Figure 1 The circuit board 1 includes an upper circuit structure 10, a lower circuit structure 20, and an intermediate circuit structure 30 disposed between the upper circuit structure 10 and the lower circuit structure 20. The intermediate circuit structure 30 includes an intermediate shielding structure 310, a plurality of intermediate power conducting parts 320, a plurality of first intermediate signal conducting parts 331, a plurality of second intermediate signal conducting parts 332, a plurality of first intermediate grounding lines 341, and a plurality of second intermediate grounding lines 342.

[0029] The intermediate shield structure 310 has a first surface S1 and a second surface S2 opposite to the first surface S1, and a plurality of intermediate power conducting portions 320 penetrate the intermediate shield structure 310. A plurality of first intermediate signal conducting portions 331 are disposed on the first surface S1, and a plurality of second intermediate signal conducting portions 332 are disposed on the second surface S2. A plurality of first intermediate ground lines 341 are disposed on the first surface S1, and are respectively located between the plurality of intermediate power conducting portions 320 and the plurality of first intermediate signal conducting portions 331. A plurality of second intermediate ground lines 342 are disposed on the second surface S2, and are respectively located between the plurality of intermediate power conducting portions 320 and the plurality of second intermediate signal conducting portions 332.

[0030] Through the above structural design, multiple power transmission parts and multiple signal transmission parts can be designed on the same layer, and the ground wire is set between the power transmission part and the signal transmission part to shield electromagnetic interference, thereby improving the integration of the circuit board.

[0031] Please continue reading Figure 1 The intermediate power conducting portion 320 penetrates the intermediate shielding structure 310 in a first direction D1, the first direction D1 is perpendicular to the first surface S1 and the second surface S2 of the intermediate shielding structure 310, and the intermediate power conducting portion 320 protrudes from the first surface S1 and the second surface S2. In addition, the plurality of intermediate power conducting portions 320 are arranged at intervals along a second direction D2, the second direction D2 is perpendicular to the first direction D1, that is, the second direction D2 is parallel to the first surface S1 and the second surface S2 of the intermediate shielding structure 310.

[0032] The first intermediate signal conducting portions 331 are arranged at intervals along the second direction D2 on the first surface S1 , the second intermediate signal conducting portions 332 are arranged at intervals along the second direction D2 on the second surface S2 , and the first intermediate signal conducting portions 331 overlap the second intermediate signal conducting portions 332 in the first direction D1 .

[0033] The first middle ground lines 341 are respectively located between the middle power conducting parts 320 and the first middle signal conducting parts 331 along the second direction D2 on the first surface S1 , and the second middle ground lines 342 are respectively located between the middle power conducting parts 320 and the second middle signal conducting parts 332 along the second direction D2 on the second surface S2 .

[0034] like Figure 1 As shown, the plurality of first intermediate signal conducting portions 331 are arranged alternately with the plurality of intermediate power conducting portions 320, and the plurality of second intermediate signal conducting portions 332 are arranged alternately with the plurality of intermediate power conducting portions 320. Specifically, the plurality of first intermediate signal conducting portions 331 are arranged alternately with the plurality of intermediate power conducting portions 320 along the second direction D2 on the first surface S1, and the plurality of second intermediate signal conducting portions 332 are arranged alternately with the plurality of intermediate power conducting portions 320 along the second direction D2 on the second surface S2.

[0035] The upper circuit structure 10 and the lower circuit structure 20 respectively include a shielding structure 110, 210, a plurality of power transmission parts 120, 220, a plurality of signal transmission parts 130, 230 and a plurality of grounding lines 140, 240. The shielding structure 110, 210 has a surface S facing away from the middle circuit structure 30. The plurality of power transmission parts 120, 220 penetrate the shielding structure 110, 210 and connect the plurality of middle power transmission parts 320. The plurality of signal transmission parts 130, 230 are disposed on the surface S and overlap with the plurality of first middle signal transmission parts 331 and the plurality of second middle signal transmission parts 332. The plurality of grounding lines 140, 240 are disposed on the surface S and are respectively located between the plurality of power transmission parts 120, 220 and the plurality of signal transmission parts 130, 230.

[0036] Through the above structural design, the multiple power conducting parts of the upper circuit structure 10, the middle circuit structure 30 and the lower circuit structure 20 can be connected to increase the thickness of the power line, can carry a larger current, and are not easy to cause the circuit to heat up, thereby improving product reliability. In some embodiments, in the first direction D1, the total thickness of the middle power conducting part 320 of the middle circuit structure 30 and the power conducting parts 120 and 220 of the upper circuit structure 10 and the lower circuit structure 20 can be between 100 μm and 500 μm (including the end value).

[0037] Furthermore, the multiple signal transmission parts of the upper circuit structure 10, the middle circuit structure 30 and the lower circuit structure 20 are integrated into the same circuit board and do not interfere with each other, thereby improving the integration of the circuit board, and the power line and the signal line can share the ground line, increasing the wiring utilization rate. In addition, there is no need to set up additional via holes for the ground line, avoiding the influence of impedance discontinuity caused by the via holes.

[0038] Please continue reading Figure 1 , a plurality of signal conducting portions 130, 230 are arranged alternately with a plurality of power conducting portions 120, 220. Specifically, the power conducting portions 120, 220 penetrate the shielding structures 110, 210 in a first direction D1, the first direction D1 is perpendicular to the surface S of the shielding structures 110, 210, and the power conducting portions 120, 220 protrude from the surface S. In addition, the plurality of power conducting portions 120, 220 are arranged at intervals along a second direction D2, the second direction D2 is parallel to the surface S of the shielding structures 110, 210, the plurality of signal conducting portions 130, 230 are arranged alternately along the second direction D2 on the surface S of the shielding structures 110, 210, and the plurality of signal conducting portions 130, 230 and the plurality of power conducting portions 120, 220 are arranged alternately along the second direction D2 on the surface S of the shielding structures 110, 210, respectively.

[0039] The plurality of signal conducting portions 130, 230 overlap with the plurality of first intermediate signal conducting portions 331 and the plurality of second intermediate signal conducting portions 332 in the first direction D1. Specifically, the plurality of signal conducting portions 130, 230 overlap with the projections of the plurality of first intermediate signal conducting portions 331 and the plurality of second intermediate signal conducting portions 332 in the first direction D1. The plurality of ground lines 140, 240 are respectively located between the plurality of power conducting portions 120, 220 and the plurality of signal conducting portions 130, 230 along the second direction D2 on the surface S of the shielding structure 110, 210.

[0040] In some embodiments, in the first direction D1, the thickness of each first intermediate ground line 341 is greater than the thickness of the signal line SL of each first intermediate signal conducting portion 331, the thickness of each second intermediate ground line 342 is greater than the thickness of the signal line SL of each second intermediate signal conducting portion 332, and the thickness of each ground line 140, 240 is greater than the thickness of the signal line SL of each signal conducting portion 130, 230. In some embodiments, in the first direction D1, the thickness of each first intermediate ground line 341 is not less than twice the thickness of the signal line SL of each first intermediate signal conducting portion 331, the thickness of each second intermediate ground line 342 is not less than twice the thickness of the signal line SL of each second intermediate signal conducting portion 332, and the thickness of each ground line 140, 240 is not less than twice the thickness of the signal line SL of each signal conducting portion 130, 230. By designing the thickness of the ground line and the signal line, electromagnetic interference between the signal conducting portion and the power conducting portion can be further shielded.

[0041] like Figure 1 As shown, the plurality of first intermediate signal conducting parts 331, the plurality of second intermediate signal conducting parts 332, and the plurality of signal conducting parts 130, 230 respectively include a signal line SL and a cavity C, and the signal line SL is disposed in the cavity C. In some embodiments, the signal line SL may be a differential signal line. In some embodiments, the signal line SL is matched with the cavity C, so that the plurality of first intermediate signal conducting parts 331, the plurality of second intermediate signal conducting parts 332, and the plurality of signal conducting parts 130, 230 are used as high-speed or high-frequency signal transmission lines, for example, they can be applied to 4G or 5G electronic components, or even aviation, aerospace or terahertz electronic components.

[0042] The intermediate shielding structure 310 and the shielding structures 110 and 210 respectively include absorbing material layers 111, 211, 311 and dielectric layers 112, 212, 312. In some embodiments, the intermediate shielding structure 310 further includes another dielectric layer 312, and the absorbing material layer 311 is disposed between the two dielectric layers 312. In some embodiments, the material of the absorbing material layers 111, 211, 311 may include absorbing materials formed by mixed resin, nickel-iron alloy, two-dimensional inorganic compound nanomaterials, graphene and trace elements, such as ceramic absorbing materials or carbon-based absorbing materials. In some embodiments, the dielectric layers 112, 212, 312 may be liquid crystal polymers (LCP), graphene or polytetrafluoroethene (PTFE). In some embodiments, the dielectric loss (Df) of the dielectric layers 112, 212, 312 is less than 0.004.

[0043] For example, the material of the absorbing material layer 111, 211, 311 may include graphene or two-dimensional inorganic compound nanomaterials, such as Mxene. Since the aforementioned materials have high dielectric constant and high electromagnetic shielding properties, they are more suitable for high-frequency electronic components, such as aviation, aerospace or terahertz electronic components. In addition, graphene or two-dimensional inorganic compound nanomaterials are also suitable for formation by printing technology, and the mixing ratio and thickness can be adjusted according to different shielding requirements, and their insulation properties can also prevent short circuits from occurring.

[0044] Through the lamination design and material selection of the intermediate shielding structure 310 and the shielding structures 110 and 210, the electromagnetic interference between the multiple signal transmission parts of the upper circuit structure 10, the intermediate circuit structure 30 and the lower circuit structure 20 can be shielded, and the dielectric transmission loss can be reduced. In addition, compared with the general electromagnetic interference (EMI) shielding film, the mixing ratio and thickness of the absorbing material layers 111, 211, and 311 can be adjusted according to different shielding requirements, and its application flexibility is higher.

[0045] The intermediate power conducting portion 320 includes a first metal layer 321 and a second metal layer 322, and the conductivity of the first metal layer 321 is greater than the conductivity of the second metal layer 322. In some embodiments, the intermediate power conducting portion 320 further includes another second metal layer 322, and the first metal layer 321 is disposed between the two second metal layers 322. In some embodiments, the material of the first metal layer 321 may include silver, and the material of the second metal layer 322 may include copper. Through the stacking design and material selection of the intermediate power conducting portion 320, the skin effect of the conductor can be reduced by utilizing the higher conductivity of the metal located in the middle, and the differential etching technology can be used to reduce the situation of short circuit caused by incomplete etching due to direct etching.

[0046] Figure 2 is a partial top view of the circuit structure of at least one embodiment of the present invention. Figure 2 , taking the upper circuit structure 10 as an example, a plurality of power conducting parts 120 are arranged at intervals d along the second direction D2 on the surface S of the shielding structure 110, and the signal line SL and the ground line 140 are arranged in the interval d, and the power conducting part 120, the signal line SL, the cavity C and the ground line 140 extend along the third direction D3 perpendicular to the second direction D2. Since the power line requires a certain degree of width and thickness to carry large current and dissipate heat, a certain degree of spacing is also required between them to avoid the problem of incomplete etching. However, through the above wiring design, the signal line and the ground line are arranged in the spacing of the power line, which can increase the wiring utilization rate and improve the integration of the circuit board.

[0047] In some embodiments, in the second direction D2, the width of the plurality of intermediate power conducting portions 320 and the width of the plurality of power conducting portions 120, 220 are respectively between 100 μm and 300 μm (inclusive). In some embodiments, in the second direction D2, the spacing d between the plurality of intermediate power conducting portions 320 and the spacing d between the plurality of power conducting portions 120, 220 are respectively between 200 μm and 400 μm (inclusive). In some embodiments, in the second direction D2, the width of the plurality of signal lines SL, the width of the first intermediate ground line 341, the width of the second intermediate ground line 342, and the width of the ground lines 140, 240 are respectively between 25 μm and 100 μm (inclusive).

[0048] Figures 3A to 3U is a partial cross-sectional view of a circuit board in different process stages according to at least one embodiment of the present invention. Figure 3A , providing a metal structure 320', the metal structure 320' includes a first initial metal layer 321' and two second initial metal layers 322' respectively located on both sides of the first initial metal layer 321'. In detail, the two second initial metal layers 322' are respectively located on both sides of the first initial metal layer 321' along the first direction D1. In some embodiments, the material of the first initial metal layer 321' may include silver, and the material of the second initial metal layer 322' may include copper.

[0049] See also FIG. 3B to FIG. 3E , patterning the two second initial metal layers 322' to form two second metal layers 322. First, as Figure 3B As shown, the first photoresist film F1 and the second photoresist film F2 are respectively formed on the two second initial metal layers 322'. In some embodiments, the first photoresist film F1 and the second photoresist film F2 can be respectively formed on the two second initial metal layers 322' by a lamination process.

[0050] Then, if Figure 3C As shown, the first photoresist film F1 and the second photoresist film F2 are patterned to expose two portions of the second initial metal layer 322'. Specifically, the first photoresist film F1 and the second photoresist film F2 are patterned to form openings that are spaced apart along a second direction D2 and expose two portions of the second initial metal layer 322', and the second direction D2 is perpendicular to the first direction D1.

[0051] like Figure 3D and Figure 3EAs shown, the patterned first photoresist film F1 and the second photoresist film F2 are used as masks, and the two second initial metal layers 322' are patterned to form the two second metal layers 322, and then the first photoresist film F1 and the second photoresist film F2 are removed. In some embodiments, the first photoresist film F1 and the second photoresist film F2 can be patterned by a photolithography process. In some embodiments, the two second initial metal layers 322' can be patterned by an etching process to form the two second metal layers 322. In some embodiments, the etching process can be wet etching, and the etching solution can be an acid etching solution. In other words, the method of patterning the two second initial metal layers 322' can be acid etching.

[0052] See also Figure 3F , forming a release film R on one of the two second metal layers 322. Figure 3G , patterning the first initial metal layer 321' to form the first metal layer 321. In detail, the first initial metal layer 321' is patterned with the second metal layer 322 as a mask to form the first metal layer 321, thereby forming the intermediate power conduction portion 320. In some embodiments, the release film R can be formed on one of the two second metal layers 322 by a lamination process. In some embodiments, the first initial metal layer 321' can be patterned by an etching process to form the first metal layer 321. In some embodiments, the etching process can be wet etching, and the etching solution can be an alkaline etching solution. In other words, the method of patterning the first initial metal layer 321' can be alkaline etching.

[0053] By selecting the materials of the first initial metal layer 321 ′ and the second initial metal layer 322 ′ and using a differential etching process, the short circuit caused by incomplete etching due to direct etching can be reduced.

[0054] See also Figure 3H to Figure 3J , an intermediate shielding structure 310 is formed on the release film R, and the intermediate shielding structure 310 has a first surface S1 and a second surface S2 opposite to the first surface S1 and contacting the release film R. Figure 3H As shown, a dielectric layer 312 is formed on the portion of the release film R exposed by the first metal layer 321. Fig. 3I As shown, a wave absorbing material layer 311 is formed on the dielectric layer 312. Figure 3J As shown, another dielectric layer 312 is formed on the absorbing material layer 311 to form an intermediate shielding structure 310, and in the first direction D1, the intermediate shielding structure 310 has a first surface S1 and a second surface S2 opposite to the first surface S1 and contacting the release film R. In some embodiments, the absorbing material layer 311 and the dielectric layer 312 can be formed by a printing process.

[0055] See also Figure 3K, forming a plurality of first intermediate signal conducting parts 331 and a plurality of first intermediate grounding lines 341 on the first surface S1. Specifically, a plurality of signal lines SL of the first intermediate signal conducting parts 331 and a plurality of first intermediate grounding lines 341 are formed on the first surface S1, and in the second direction D2, the first intermediate grounding lines 341 are located between the intermediate power conducting part 320 and the signal line SL of the first intermediate signal conducting part 331.

[0056] See also Figure 3L After forming a plurality of first intermediate signal conducting portions 331 and a plurality of first intermediate grounding lines 341 on the first surface S1, the release film R is removed to expose the second surface S2. Figure 3M , a plurality of second intermediate signal conducting parts 332 and a plurality of second intermediate ground lines 342 are formed on the second surface S2. Specifically, a plurality of signal lines SL of the second intermediate signal conducting parts 332 and a plurality of second intermediate ground lines 342 are formed on the second surface S2, and in the second direction D2, the second intermediate ground lines 342 are located between the intermediate power conducting part 320 and the signal line SL of the second intermediate signal conducting part 332. In addition, in the first direction D1, the first intermediate signal conducting part 331 overlaps with the signal line SL of the second intermediate signal conducting part 332, and the first intermediate ground line 341 overlaps with the second intermediate ground line 342.

[0057] In some embodiments, the material of the signal line SL of the first intermediate signal conducting portion 331 and the second intermediate signal conducting portion 332 may include metal, such as copper. In some embodiments, the signal line SL of the first intermediate signal conducting portion 331 and the second intermediate signal conducting portion 332, the first intermediate ground line 341, and the second intermediate ground line 342 may be formed by a printing process.

[0058] See also Figure 3N and Fig.3O , two shielding structures 110 and 210 are respectively formed on the plurality of first intermediate signal conducting portions 331 and the plurality of second intermediate signal conducting portions 332, and the two shielding structures 110 and 210 respectively have a surface S facing away from the intermediate shielding structure 310. Figure 3N As shown, an absorbing material layer 111 is formed on the signal line SL of the first intermediate signal conducting portion 331 and the first intermediate ground line 341, and the absorbing material layer 111 and the first surface S1 of the intermediate shielding structure 310 form a cavity C. In addition, an absorbing material layer 211 is formed on the signal line SL of the second intermediate signal conducting portion 332 and the second intermediate ground line 342, and the absorbing material layer 211 and the second surface S2 of the intermediate shielding structure 310 form a cavity C, thereby forming the intermediate line structure 30. Then, as shown in FIG. Fig.3OAs shown, dielectric layers 112 and 212 are formed on the absorbing material layers 111 and 211, respectively, thereby forming two shielding structures 110 and 210. In some embodiments, the two shielding structures 110 and 210 can be formed on the first intermediate signal conducting portions 331 and the second intermediate signal conducting portions 332, respectively, by a lamination process.

[0059] See also Figure 3P , a plurality of signal conducting parts 130, 230 and a plurality of grounding lines 140, 240 are respectively formed on the two surfaces S of the two shielding structures 110, 210. In detail, the signal lines SL of the plurality of signal conducting parts 130, 230 and the plurality of grounding lines 140, 240 are formed on the two surfaces S of the two shielding structures 110, 210, and in the second direction D2, the grounding lines 140, 240 are respectively located between the power conducting parts 120, 220 and the signal lines SL of the signal conducting parts 130, 230. In addition, in the first direction D1, the signal lines SL of the signal conducting parts 130, 230 overlap with the signal lines SL of the first intermediate signal conducting parts 331 and the second intermediate signal conducting parts 332, and the grounding lines 140, 240 overlap with the first intermediate grounding lines 341 and the second intermediate grounding lines 342.

[0060] See also Figure 3Q , two build-up structures B1 and B2 are respectively formed on a plurality of signal conducting parts 130 and 230 and a plurality of grounding lines 140 and 240. In detail, the two build-up structures B1 and B2 are respectively formed on the signal lines SL and the grounding lines 140 and 240 of the first signal conducting parts 130 and 230, and the two build-up structures B1 and B2 respectively form a cavity C with the two surfaces S of 110 and 210. In some embodiments, the build-up structures B1 and B2 may include an insulating layer and a copper foil formed on the insulating layer. In some embodiments, the two build-up structures B1 and B2 may be respectively formed on the plurality of signal conducting parts 130 and 230 and the plurality of grounding lines 140 and 240 by a lamination process.

[0061] Next, see Figure 3R After forming two build-up structures B1 and B2 on the plurality of signal conducting parts 130 and 230 and the plurality of ground lines 140 and 240, respectively, a plurality of through holes T1 and T2 are formed to expose the two second metal layers 322. Specifically, a plurality of through holes T1 and T2 extending along the first direction D1 are formed, wherein the through hole T1 penetrates the build-up structure B1 and the shielding structure 110, and the through hole T2 penetrates the build-up structure B2 and the shielding structure 210, so as to respectively expose the second metal layer 322 located on the first surface S1 and the second surface S2 of the intermediate shielding structure 310. In some embodiments, the plurality of through holes T1 and T2 may be formed by a laser process.

[0062] See also Figure 3S and Figure 3T , forming a plurality of power conducting parts 120, 220, filling a plurality of through holes T1, T2 and connecting two second metal layers 322. First, as Figure 3S As shown, initial metal layers 120', 220' are formed on two build-up structures B1, B2, respectively, and the initial metal layers 120', 220' are respectively filled into a plurality of through holes T1, T2 and connect the two second metal layers 322. In some embodiments, the material of the initial metal layers 120', 220' may include copper. In some embodiments, the initial metal layers 120', 220' may be formed by an electroplating process.

[0063] Next, see Figure 3T The initial metal layers 120' and 220' are patterned to form a plurality of power conducting portions 120 and 220, respectively, and the plurality of power conducting portions 120 and 220 are respectively filled into the plurality of through holes T1 and T2, and respectively connected to the second metal layer 322 located on the first surface S1 and the second surface S2 of the intermediate shielding structure 310, thereby forming the upper circuit structure 10 and the lower circuit structure 20. In some embodiments, the plurality of power conducting portions 120 and 220 can be formed by photolithography and etching processes.

[0064] See also Figure 3U , two electromagnetic interference shielding layers E1, E2 are respectively formed on the multiple power conducting parts 120, 220, thereby forming the circuit board 1. In some embodiments, the two electromagnetic interference shielding layers E1, E2 can be respectively formed on the multiple power conducting parts 120, 220 by a lamination process.

[0065] In summary, in at least one embodiment of the circuit board and its manufacturing method of the present invention, multiple power conduction parts and multiple signal conduction parts can be designed on the same layer, and the ground wire is set between the power conduction part and the signal conduction part to shield electromagnetic interference, thereby improving the integration of the circuit board.

[0066] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.

[0067]

Explanation of symbols

[0068] 1: Circuit board

[0069] 10: Upper line structure

[0070] 110, 210: Shielding structure

[0071] 111, 211, 311: Absorbing material layer

[0072] 112, 212, 312: dielectric layer

[0073] 120, 220: Power transmission unit

[0074] 120', 220': Initial metal layer

[0075] 130, 230: signal transmission unit

[0076] 140, 240: ground wire

[0077] 20: Lower line structure

[0078] 30: Middle line structure

[0079] 310: Intermediate shielding structure

[0080] 320: Intermediate power supply conduction unit

[0081] 320':Metal structure

[0082] 321: First metal layer

[0083] 321': first initial metal layer

[0084] 322: Second metal layer

[0085] 322': Second initial metal layer

[0086] 331: first intermediate signal transmission unit

[0087] 332: Second intermediate signal transmission unit

[0088] 341: First middle ground wire

[0089] 342: Second middle ground wire

[0090] B1, B2: Layered structure

[0091] C: Cavity

[0092] d: Spacing

[0093] D1: First direction

[0094] D2: Second direction

[0095] D3: Third direction

[0096] E1, E2: EMI shielding layer

[0097] F1: First photoresist film

[0098] F2: Second photoresist film

[0099] R: Release film

[0100] S: Surface

[0101] S1: First surface

[0102] S2: Second surface

[0103] SL:Signal Line

[0104] T1, T2: perforation.

Claims

1. A circuit board, characterized in that: include: An upper circuit structure, a lower circuit structure, and an intermediate circuit structure disposed between the upper circuit structure and the lower circuit structure, wherein the intermediate circuit structure comprises: An intermediate shielding structure having a first surface and a second surface opposite to the first surface; a plurality of intermediate power conducting portions, penetrating the intermediate shielding structure; A plurality of first intermediate signal conducting parts are disposed on the first surface; A plurality of second intermediate signal conducting parts are disposed on the second surface; a plurality of first intermediate ground lines, disposed on the first surface and respectively located between the plurality of intermediate power conducting portions and the plurality of first intermediate signal conducting portions; and A plurality of second intermediate ground lines are disposed on the second surface and are respectively located between the plurality of intermediate power conducting portions and the plurality of second intermediate signal conducting portions. 2 . The circuit board according to claim 1 , wherein the plurality of first intermediate signal conducting portions are arranged in a staggered manner with the plurality of intermediate power conducting portions, and the plurality of second intermediate signal conducting portions are arranged in a staggered manner with the plurality of intermediate power conducting portions.

3. The circuit board according to claim 1, wherein the upper circuit structure and the lower circuit structure respectively comprise: a shielding structure having a surface facing away from the intermediate line structure; a plurality of power conducting portions, penetrating the shielding structure and connecting the plurality of intermediate power conducting portions; a plurality of signal conducting portions disposed on the surface and overlapping with projections of the plurality of first intermediate signal conducting portions and the plurality of second intermediate signal conducting portions in a direction perpendicular to the surface of the shielding structure; as well as A plurality of grounding wires are disposed on the surface and respectively located between the plurality of power conducting parts and the plurality of signal conducting parts. The circuit board according to claim 3 , wherein the plurality of signal conducting portions and the plurality of power conducting portions are arranged alternately. 5 . The circuit board according to claim 3 , wherein the intermediate shielding structure and the shielding structure respectively comprise an absorbing material layer and a dielectric layer, and the dielectric loss of the dielectric layer is less than 0.

004. 6 . The circuit board according to claim 5 , wherein the intermediate shielding structure further comprises another dielectric layer, and the absorbing material layer is disposed between the two dielectric layers. 7 . The circuit board of claim 1 , wherein the intermediate power conducting portion comprises a first metal layer and a second metal layer, wherein the conductivity of the first metal layer is greater than the conductivity of the second metal layer. 8 . The circuit board of claim 7 , wherein the intermediate power conducting portion further comprises another second metal layer, the first metal layer being disposed between the two second metal layers. 9 . The circuit board according to claim 1 , wherein the plurality of first intermediate signal conducting portions, the plurality of second intermediate signal conducting portions, and the plurality of signal conducting portions respectively comprise a signal line and a cavity, and the signal line is disposed in the cavity.

10. The circuit board according to claim 9, wherein the thickness of each of the plurality of first intermediate ground lines is greater than the thickness of the signal line of each of the plurality of first intermediate signal conducting parts, the thickness of each of the plurality of second intermediate ground lines is greater than the thickness of the signal line of each of the plurality of second intermediate signal conducting parts, and the thickness of each of the plurality of ground lines is greater than the thickness of the signal line of each of the plurality of signal conducting parts.

11. The circuit board according to claim 10, wherein the thickness of each of the plurality of first intermediate ground lines is not less than twice the thickness of the signal line of each of the plurality of first intermediate signal conducting parts, the thickness of each of the plurality of second intermediate ground lines is not less than twice the thickness of the signal line of each of the plurality of second intermediate signal conducting parts, and the thickness of each of the plurality of ground lines is not less than twice the thickness of the signal line of each of the plurality of signal conducting parts.

12. A method for manufacturing a circuit board, characterized in that: include: Providing a metal structure, the metal structure comprising a first initial metal layer and two second initial metal layers respectively located on both sides of the first initial metal layer; patterning the two second initial metal layers to form two second metal layers; forming a release film on one of the two second metal layers; patterning the first initial metal layer to form a first metal layer; forming an intermediate shielding structure on the release film, wherein the intermediate shielding structure has a first surface and a second surface opposite to the first surface and contacting the release film; forming a plurality of first intermediate signal conducting portions and a plurality of first intermediate grounding lines on the first surface; After forming the plurality of first intermediate signal conducting parts and the plurality of first intermediate grounding lines on the first surface, removing the release film to expose the second surface; forming a plurality of second intermediate signal conducting portions and a plurality of second intermediate grounding lines on the second surface; forming two shielding structures on the plurality of first intermediate signal conducting portions and the plurality of second intermediate signal conducting portions respectively, the two shielding structures respectively having a surface facing away from the intermediate shielding structure; forming a plurality of signal conducting parts and a plurality of grounding lines on the two surfaces of the two shielding structures respectively; forming two build-up structures on the plurality of signal conducting portions and the plurality of grounding lines respectively; After forming the two build-up structures on the plurality of signal conducting portions and the plurality of grounding lines respectively, forming a plurality of through holes to expose the two second metal layers; as well as A plurality of power conducting portions are formed to fill the plurality of through holes and connect the two second metal layers. 13 . The method for manufacturing a circuit board according to claim 12 , wherein the two second initial metal layers are patterned by acid etching, and the first initial metal layer is patterned by alkaline etching.

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