Mask and preparation method of metal-oxide semiconductor field effect transistor
By designing a mask plate with a first semi-transmissive region, a mask region and a second semi-transmissive region, the complex lithography process in semiconductor manufacturing is solved, and the effect of reducing costs and increasing production capacity is achieved.
Patent Information
- Application Number
- CN202411602452.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2025-02-28
AI Technical Summary
In the existing semiconductor manufacturing process, the lithography process is complex, resulting in high costs and low production efficiency.
A mask plate is designed, including a first semi-transmissive region, a mask region and a second semi-transmissive region. The mask region is patterned by alternately arranged light-shifting region and light-transmissive region to reduce the use of photoresist.
By reducing the number of mask plates, the production cost of semiconductor devices is reduced and the production capacity of lithography equipment is increased.
Smart Images
Figure CN119535881A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for preparing a mask and a metal-oxide semiconductor field effect. Background Art
[0002] Masks, also known as photomasks, are key components in the microelectronics manufacturing process. They are responsible for transferring information such as design graphics and process technology to the photoresist of the silicon wafer through the photolithography step, and then to the silicon wafer through subsequent processes such as etching. At present, in the semiconductor production process, the photolithography process is complicated, which not only increases the photolithography cost and production cost, but also reduces the production efficiency of semiconductor devices. Summary of the invention
[0003] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a mask, wherein the mask comprises:
[0004] A mask body, the mask body comprising a first semi-transparent area, a mask area and a second semi-transparent area;
[0005] The first semi-transparent area is located at the center of the mask body;
[0006] The mask area surrounds the first semi-light-transmitting area, wherein the mask area includes light-shielding areas and light-transmitting areas alternately arranged in a direction away from the first semi-light-transmitting area;
[0007] The second semi-light-transmitting area is located at a side of the mask area away from the first semi-light-transmitting area and surrounds the mask area.
[0008] In a possible implementation, the light-shielding area surrounds the first semi-light-transmitting area, the light-transmitting area is located on a side of the light-shielding area away from the first semi-light-transmitting area and surrounds the light-shielding area, or,
[0009] The light-transmitting area surrounds the first semi-light-transmitting area. The light-shielding area is located on a side of the light-transmitting area away from the first semi-light-shielding area and surrounds the light-transmitting area.
[0010] In a possible implementation manner, the light-transmitting area is arranged between two adjacent light-shielding areas, and the light-shielding area is arranged between two adjacent light-transmitting areas.
[0011] In a possible implementation, the transmittance of the light-transmitting area is greater than the transmittance of the first semi-light-transmitting area, the transmittance of the first semi-light-transmitting area is greater than the transmittance of the light-shielding area, and the transmittance of the first semi-light-transmitting area is the same as the transmittance of the second semi-light-transmitting area.
[0012] In a possible implementation manner, geometric centers of the first semi-light-transmitting area, the light-transmitting area, the light-shielding area, and the second semi-light-transmitting area coincide with each other.
[0013] In a possible implementation manner, the shape of the first semi-light-transmitting area includes a circle, and the light-transmitting area, the light-shielding area, and the second semi-light-transmitting area include a ring shape.
[0014] Another object of the present application is to provide a method for preparing a metal-oxide semiconductor field effect transistor, the method comprising:
[0015] Providing a silicon wafer;
[0016] forming an oxide layer on one side of the silicon wafer;
[0017] Coating a layer of photoresist on a side of the oxide layer away from the silicon wafer;
[0018] The photoresist is patterned using the plurality of masks provided by the present application, a photoresist window is formed at a position corresponding to the mask area, and the photoresist at a position corresponding to the first semi-transparent area and the second semi-transparent area is thinned;
[0019] Etching the oxide layer exposed by the photoresist window to etch out a voltage divider ring window for forming a voltage divider ring;
[0020] Carriers are injected into the silicon wafer based on the voltage divider ring window, and a voltage divider ring is formed by a push-junction process.
[0021] In a possible implementation, in the step of injecting carriers into the silicon wafer based on the voltage divider ring window and forming a voltage divider ring by a push-junction process, the method includes:
[0022] Injecting carriers into the silicon wafer based on the voltage divider ring window;
[0023] removing the photoresist at positions corresponding to the first semi-light-transmitting area and the second semi-light-transmitting area;
[0024] Etching and removing the oxide layer at positions corresponding to the first semi-light-transmitting area and the second semi-light-transmitting area;
[0025] A voltage divider ring is formed based on the voltage divider ring window through a push-junction process.
[0026] Another object of the present application is to provide a metal-oxide semiconductor field effect transistor, which is manufactured using multiple metal-oxide semiconductor field effect transistor manufacturing methods provided in the present application.
[0027] Another object of the present application is to provide an electronic device, which includes a plurality of the metal-oxide semiconductor field effect transistors provided in the present application.
[0028] Based on any of the above aspects, the embodiments of the present application provide a method for preparing a mask and a metal-oxide semiconductor field effect transistor. In this way, in the process of preparing a semiconductor device (such as a metal-oxide semiconductor field effect transistor), the number of masks used is reduced, thereby reducing the production cost of the semiconductor device and improving the production capacity of the lithography equipment. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0030] Figure 1 One of the schematic diagrams of a mask provided in this embodiment;
[0031] Figure 2 A second schematic diagram of a mask provided in this embodiment;
[0032] Figure 3 A schematic diagram of a silicon wafer provided in this embodiment after a photolithography step;
[0033] Figure 4 A schematic diagram of steps of a method for preparing a semiconductor device provided in this embodiment;
[0034] Figure 5 for Figure 4 The corresponding process diagram;
[0035] Figure 6 for Figure 4 The process flow chart corresponding to step S160.
[0036] Icon: 1-mask, 10-mask body, 11-first semi-transparent area, 12-mask area, 120-light-shielding area, 121-transparent area, 13-second semi-transparent area, 20-silicon wafer, 21-oxide layer, 22-photoresist, 23-photoresist window, 24-voltage divider ring window, 25-voltage divider ring. DETAILED DESCRIPTION
[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0038] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0039] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0040] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0041] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0042] In order to solve the technical problems mentioned in the aforementioned background technology, the inventor innovatively designed the following technical solution, and the specific implementation solution of the present application will be described in detail below with reference to the accompanying drawings.
[0043] See also Figure 1 and Figure 2 , Figure 1 A top view of a mask plate 1 provided in this embodiment, Figure 2 A front view of a mask plate 1 provided in this embodiment. The mask plate 1 includes:
[0044] The mask body 10 includes a first semi-transparent area 11 , a mask area 12 and a second semi-transparent area 13 .
[0045] The first semi-transparent area 11 is located at the center of the mask body 10, and the mask area 12 surrounds the first semi-transparent area 11, wherein the mask area 12 includes light-shielding areas 120 and light-transmitting areas 121 that are alternately arranged in a direction away from the first semi-transparent area 11. The second semi-transparent area 13 is located on the side of the mask area 12 away from the first semi-transparent area 11, and surrounds the mask area 12.
[0046] In this embodiment, the mask body 10 mainly includes three parts, namely, the first semi-transparent area 11, the mask area 12, and the second semi-transparent area 13. The first semi-transparent area 11 is located at the center of the mask body 10, allowing light of a certain wavelength to pass through. The mask area 12 surrounds the first semi-transparent area 11 and includes alternating shading areas 120 and transparent areas 121. These areas determine which parts of the photoresist 22 will be exposed during the photolithography process. The second semi-transparent area 13 is located on the side of the mask area 12 away from the first semi-transparent area 11, surrounds the mask area 12, and also allows light of a certain wavelength to pass through.
[0047] It is worth noting that the materials of the first semi-transparent area 11 and the second semi-transparent area 13 can be semi-transparent films, and the material of the light-shielding area 120 can be other opaque materials such as metal chromium. The materials of the first semi-transparent area 11, the second semi-transparent area 13, the light-shielding area 120 and the light-transparent area 121 are not specifically limited here and need to be selected according to specific circumstances.
[0048] Furthermore, in the semiconductor device manufacturing process, when using a mask for patterning processing, it is necessary to pre-prepare a photoresist layer on the film layer to be processed, and then place the mask on top of the photoresist layer. The pattern on the mask can be transferred to the photoresist layer through exposure and development, and then the etching liquid or etching gas acts on the film layer to be processed through the through holes on the photolithography layer, and etches the film layer to be processed to obtain a patterned film layer.
[0049] In the above process, the photoresist used can be divided into positive photoresist and negative photoresist. The exposed area of the positive photoresist is dissolved and removed in the subsequent development process, while the non-exposed area is retained, so that the positive photoresist can form the same image as the mask after exposure. The exposed area of the negative photoresist is retained in the development process, while the unexposed area is dissolved and removed, so that the negative photoresist forms an image opposite to the mask after exposure.
[0050] In this embodiment, please refer to Figure 1 and Figure 2The mask area 12 includes light-shielding areas 120 and light-transmitting areas 121 that are alternately arranged. The light-shielding areas 120 are used to prevent light from passing through, while the light-transmitting areas 121 allow light to pass through to expose the photoresist below. For example, in one implementation of this embodiment, when the photoresist used is a positive photoresist, the light-shielding areas 120 surround the first semi-light-transmitting area 11, and the light-transmitting areas 121 are located on the side of the light-shielding areas 120 away from the first semi-light-transmitting areas 11, and surround the light-shielding areas 120.
[0051] Illustratively, in another implementation of the present embodiment, when the photoresist used is a negative photoresist, the light-transmitting area 121 surrounds the first semi-light-transmitting area 11, and the light-shielding area 120 is located on the side of the light-transmitting area 121 away from the first semi-light-shielding area 11, and surrounds the light-transmitting area 121.
[0052] It is worth mentioning that Figure 1 and Figure 2 The schematic diagram of the mask 1 when a positive photoresist is used is illustrated, and the schematic diagram of the mask 1 when a negative photoresist is used is not specifically illustrated here.
[0053] For further information, see Figure 1 , Figure 2 and Figure 3 , Figure 3 The schematic diagram of the silicon wafer 20 after the photolithography step is illustrated, a light-transmitting area 121 is arranged between two adjacent light-shielding areas 120 , and a light-shielding area 120 is arranged between two adjacent light-transmitting areas 121 .
[0054] In this embodiment, the light shielding areas 120 and the light transmitting areas 121 are arranged alternately, and a photoresist window 23 is formed on the oxide layer 21 of the silicon wafer 20 through a photolithography step for subsequent formation of a voltage divider ring 25 .
[0055] Further, please see again Figure 1 , Figure 2 and Figure 3 The transmittance of the light-transmitting area 121 is greater than the transmittance of the first semi-light-transmitting area 11 , the transmittance of the first semi-light-transmitting area 11 is greater than the transmittance of the light-shielding area 120 , and the transmittance of the first semi-light-transmitting area 11 is the same as the transmittance of the second semi-light-transmitting area 13 .
[0056] In this embodiment, the difference in transmittance directly affects the exposure degree of the photoresist, and the hierarchical nature of the transmittance means that different areas have different light transmission capabilities. When the transmittance of the first semi-transparent area 11 and the second semi-transparent area 13 can be half of the transmittance of the light-transmitting area 121, the photoresist 22 corresponding to the light-shielding area 120 or the light-transmitting area 121 is completely changed, and the photoresist 22 with changed properties is developed away during the development process. Therefore, the alternating light-shielding areas 120 and light-transmitting areas 121 eventually form photoresist windows 23 on the silicon wafer 20, and the oxide layer 21 is exposed between two adjacent photoresist windows 23.
[0057] However, only half of the photoresist 22 in the first semi-transparent area 11 and the second semi-transparent area 13 has its properties changed. During the development process, half of the photoresist 22 with changed properties is developed away, and the other half of the photoresist 22 with unchanged properties is retained, thereby realizing ring lithography and being able to protect the oxide layer 21 corresponding to the first semi-transparent area 11 and the second semi-transparent area 13.
[0058] For further information, see Figure 1 , the geometric centers of the first semi-light-transmitting area 11 , the light-transmitting area 121 , the light-shielding area 120 and the second semi-light-transmitting area 13 coincide with each other.
[0059] In this embodiment, the coincidence of the geometric centers ensures that during the photolithography process, light can pass through the first semi-transparent area 11 , the transparent area 121 , the light shielding area 120 and the second semi-transparent area 13 uniformly and accurately.
[0060] Further, please see again Figure 1 The shape of the first semi-light-transmitting area 11 includes a circle, and the light-transmitting area 121, the light-shielding area 120 and the second semi-light-transmitting area 13 include a ring shape.
[0061] Based on the same concept, the present application also provides a method for preparing a metal-oxide semiconductor field effect transistor, see Figure 4 and Figure 5 , Figure 4 A schematic diagram of the steps of a method for preparing a metal-oxide semiconductor field effect transistor provided in this embodiment, Figure 5 for Figure 4 Corresponding process flow chart, the method comprises the following steps:
[0062] Step S110 , providing a silicon wafer 20 .
[0063] Step S120, forming an oxide layer 21 on one side of the silicon wafer 20;
[0064] In this step, the oxide layer 21 is usually composed of silicon dioxide (SiO2), which serves as an insulating layer and a masking layer to protect the silicon wafer 20 in subsequent processes.
[0065] Step S130, coating a layer of photoresist 22 on a side of the oxide layer 21 away from the silicon wafer 20;
[0066] In this step, the photoresist 22 is a sensitive material that undergoes chemical changes after exposure, thereby dissolving or remaining in the development process to form a desired pattern. The photoresist 22 can be divided into positive photoresist and negative photoresist. The exposed area of the positive photoresist is dissolved and removed in the subsequent development process, while the exposed area of the negative photoresist is retained in the development process.
[0067] Step S140, patterning the photoresist 22 using a plurality of mask plates 1 provided in the present application, forming a photoresist window 23 at a position corresponding to the mask area 12, and thinning the photoresist 22 at a position corresponding to the first semi-transparent area 11 and the second semi-transparent area 13;
[0068] In this step, the mask area 12 is composed of light-shielding areas 120 and light-transmitting areas 121 arranged alternately. This design enables the formation of a photoresist window 23 for the subsequent formation of a voltage divider ring 25 during the photolithography process. At the same time, the photoresist 22 at the positions corresponding to the first semi-transmitting area 11 and the second semi-transmitting area 13 is thinner than the photoresist 22 at the corresponding positions of the mask area 12, thereby protecting the underlying oxide layer 21. Through this mask 1, source area photolithography and ring photolithography are realized through one photolithography, which simplifies the traditional photolithography process and improves production efficiency.
[0069] Step S150, etching the oxide layer 21 exposed by the photoresist window 23 to etch out a voltage divider ring window 24 for forming a voltage divider ring 25;
[0070] In this step, etching is generally performed using a wet or dry etching technique to ensure that the exposed oxide layer 21 is accurately removed.
[0071] In this embodiment, a portion of the oxide layer 21 may be retained when etching the oxide layer 21 exposed by the photoresist window 23 to prevent damage to the silicon wafer 20 during subsequent carrier injection.
[0072] Step S160 , injecting carriers into the silicon wafer 20 based on the voltage divider ring window 24 , and forming the voltage divider ring 25 by a push-junction process.
[0073] In this embodiment, carrier injection is to change the electrical properties of the silicon wafer 20 by introducing impurity atoms into the silicon wafer 20. The carriers may be P ions, and the type of carriers is not specifically limited here and needs to be selected according to actual conditions. Then, a voltage divider ring 25 is formed by a push-junction process to ensure that the injected carriers are properly distributed in the silicon wafer 20, thereby forming an effective voltage divider ring structure.
[0074] For further information, see Figure 6 , step S160 can be implemented in the following manner.
[0075] First, carriers are injected into the silicon wafer 20 based on the voltage divider ring window 24;
[0076] Next, the photoresist 22 at the positions corresponding to the first semi-light-transmitting area 11 and the second semi-light-transmitting area 13 is removed;
[0077] In this embodiment, after the voltage divider ring window 24 is used to inject carriers into the silicon wafer 20, the photoresist 22 at the positions corresponding to the first semi-transparent area 11 and the second semi-transparent area 13 and half of the photoresist 22 at the corresponding positions of the mask area are removed. At this time, the remaining photoresist 22 at the corresponding positions of the mask area 12 can also protect the oxide layer 21 below.
[0078] Then, the oxide layer 21 at the positions corresponding to the first semi-light-transmitting area 11 and the second semi-light-transmitting area 13 is removed by etching.
[0079] In this embodiment, the oxide layer 21 at the positions corresponding to the first semi-light-transmitting area 11 and the second semi-light-transmitting area 13 is removed by etching, and then the remaining photoresist 22 in the mask area 12 is removed.
[0080] Finally, the voltage divider ring 25 is formed based on the voltage divider ring window 24 through a push-fit process.
[0081] In addition, in this embodiment, after the voltage divider ring 25 is formed, a precise groove structure is created on the silicon wafer 20 by an etching process to improve the density and performance of the device, and then a highly doped source region and drain region are formed on the silicon wafer 20 by an ion implantation process, and a polysilicon layer is deposited above the source region and the drain region to form a gate. Then, after a hole is opened in the polysilicon layer, a metal is filled in the hole to form an electrical connection between the source, the drain and the gate, and the production of the metal-oxide semiconductor field effect transistor is completed. Among them, the deposition of the metal layer can be achieved by physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating.
[0082] Based on the same concept, the embodiment of the present application also provides a metal-oxide semiconductor field effect transistor, which is manufactured using a plurality of methods for manufacturing the metal-oxide semiconductor field effect transistor provided in the present application. In the preparation process of the metal-oxide semiconductor field effect transistor, the photolithography step can be performed at one time using the mask 1, thereby reducing the photolithography cost and production cost.
[0083] Based on the same aspect concept, an embodiment of the present application further provides an electronic device, which includes a plurality of the metal-oxide semiconductor field effect transistors provided in the present application.
[0084] In summary, the present application provides a method for preparing a mask and a metal-oxide semiconductor field effect transistor. The mask includes a mask body, and the mask body includes a first semi-transparent area, a mask area, and a second semi-transparent area. The first semi-transparent area is located at the center of the mask body, and the mask area surrounds the first semi-transparent area, wherein the mask area includes a shading area and a transparent area alternately arranged in a direction away from the first semi-transparent area. The second semi-transparent area is located on the side of the mask area away from the first semi-transparent area, and surrounds the mask area. In this way, in the process of preparing semiconductor devices (for example, metal-oxide semiconductor field effect transistors), the number of masks used is reduced, thereby reducing the production cost of semiconductor devices and improving the production capacity of lithography equipment.
[0085] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A mask, characterized in that: The mask comprises: A mask body, the mask body comprising a first semi-transparent area, a mask area and a second semi-transparent area; The first semi-transparent area is located at the center of the mask body; The mask area surrounds the first semi-light-transmitting area, wherein the mask area includes light-shielding areas and light-transmitting areas alternately arranged in a direction away from the first semi-light-transmitting area; The second semi-light-transmitting area is located at a side of the mask area away from the first semi-light-transmitting area and surrounds the mask area.
2. The mask according to claim 1, characterized in that: The light-shielding area surrounds the first semi-light-transmitting area, the light-transmitting area is located on a side of the light-shielding area away from the first semi-light-transmitting area, and surrounds the light-shielding area, or, The light-transmitting area surrounds the first semi-light-transmitting area. The light-shielding area is located on a side of the light-transmitting area away from the first semi-light-shielding area and surrounds the light-transmitting area.
3. The mask according to claim 1, wherein: The light-transmitting area is arranged between two adjacent light-shielding areas, and the light-shielding area is arranged between two adjacent light-transmitting areas.
4. The mask according to claim 1, characterized in that: The transmittance of the light-transmitting area is greater than that of the first semi-light-transmitting area, the transmittance of the first semi-light-transmitting area is greater than that of the light-shielding area, and the transmittance of the first semi-light-transmitting area is the same as that of the second semi-light-transmitting area.
5. The mask according to claim 1, characterized in that: The geometric centers of the first semi-light-transmitting area, the light-transmitting area, the light-shielding area and the second semi-light-transmitting area coincide with each other.
6. The mask according to claim 1, characterized in that: The shape of the first semi-light-transmitting area includes a circle, and the light-transmitting area, the light-shielding area and the second semi-light-transmitting area include a ring shape.
7. A method for preparing a metal-oxide semiconductor field effect transistor, characterized in that: The method comprises: Providing a silicon wafer; forming an oxide layer on one side of the silicon wafer; Coating a layer of photoresist on a side of the oxide layer away from the silicon wafer; Using the mask described in claims 1 to 6 to pattern the photoresist, forming a photoresist window at a position corresponding to the mask area, and thinning the photoresist at positions corresponding to the first semi-transparent area and the second semi-transparent area; Etching the oxide layer exposed by the photoresist window to etch out a voltage divider ring window for forming a voltage divider ring; Carriers are injected into the silicon wafer based on the voltage divider ring window, and a voltage divider ring is formed by a push-junction process.
8. The method for preparing a metal-oxide semiconductor field effect transistor according to claim 7, characterized in that: In the step of injecting carriers into the silicon wafer based on the voltage divider ring window and forming a voltage divider ring by a push-junction process, the method includes: Injecting carriers into the silicon wafer based on the voltage divider ring window; removing the photoresist at positions corresponding to the first semi-light-transmitting area and the second semi-light-transmitting area; Etching and removing the oxide layer at positions corresponding to the first semi-light-transmitting area and the second semi-light-transmitting area; A voltage divider ring is formed based on the voltage divider ring window through a push-junction process.
9. A metal-oxide semiconductor field effect transistor, wherein the metal-oxide semiconductor field effect transistor is manufactured by the metal-oxide semiconductor field effect transistor manufacturing method according to any one of claims 7 to 8.
10. An electronic device, characterized in that: The electronic device comprises the metal-oxide semiconductor field effect transistor according to claim 9.