Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: forming a supporting layer, and forming a plurality of through holes penetrating through the supporting layer; a conductive structure is formed in each through hole, and the through holes are exposed out of the two opposite surfaces of the conductive structure respectively; an electrical element is arranged on one side of the supporting layer, and an electrode of the electrical element is electrically connected with the conductive structure; forming a plastic packaging layer at least packaging the side surface of the electrical element; and forming a first trace layer on one side, deviating from the plastic packaging layer, of the supporting layer, wherein the first trace layer is electrically connected with the conductive structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In common semiconductor packaging processes, for example, the packaging process of electrical components may include the following process: first, a rewiring layer is prepared on a silicon substrate; then, the electrical component is mounted on the rewiring layer, with the electrode of the electrical component facing the rewiring layer; then, the electrode of the electrical component is connected to the rewiring layer; then, a plastic packaging layer is formed to encapsulate the rewiring layer and the electrical component; finally, a grinding process is used to remove the silicon substrate.

[0003] In the above-mentioned semiconductor packaging technology, the silicon substrate is consumed and cannot be reused, resulting in a high cost of the semiconductor packaging process. Summary of the invention

[0004] The embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] forming a support layer, and forming a plurality of through holes penetrating the support layer;

[0007] forming a conductive structure in each of the through holes, wherein two opposite surfaces of the conductive structure are exposed to the through holes respectively;

[0008] An electrical component is arranged on one side of the support layer, wherein an electrode of the electrical component is electrically connected to the conductive structure;

[0009] forming a plastic encapsulation layer that at least encapsulates the side surfaces of the electrical component;

[0010] A first trace layer is formed on a side of the support layer away from the plastic encapsulation layer, and the first trace layer is electrically connected to the conductive structure.

[0011] In one embodiment, before forming a plurality of through holes penetrating the support layer, the method for manufacturing the semiconductor structure further comprises: providing a metal layer on one side of the support layer;

[0012] The forming of the conductive structure in each of the through holes comprises: using the metal layer as a cathode and using an electroplating process to form the conductive structure in the through hole;

[0013] The step of arranging the electrical component on one side of the support layer comprises: arranging the electrical component on the side of the support layer away from the metal layer.

[0014] In one embodiment, forming a first trace layer on a side of the support layer away from the plastic encapsulation layer includes:

[0015] Etching the metal layer to form a first trace layer;

[0016] or,

[0017] removing the metal layer;

[0018] Performing a thinning process on the supporting layer and the conductive structure on a side facing away from the supporting layer;

[0019] A first trace layer is prepared on a side of the support layer facing away from the plastic encapsulation layer.

[0020] In one embodiment, the forming of the support layer comprises: forming the support layer on a carrier;

[0021] The step of disposing an electrical component on one side of the support layer, wherein an electrode of the electrical component is electrically connected to the conductive structure, comprises:

[0022] removing the carrier board,

[0023] Using the support layer to provide support, arranging an electrical component on one side of the support layer, and welding the electrode of the electrical component to the conductive structure using a reflow soldering process;

[0024] or,

[0025] forming a second trace layer electrically connected to the conductive structure on one side of the support layer;

[0026] removing the carrier board,

[0027] The support layer is used to provide support, an electrical component is arranged on a side of the second trace layer away from the support layer, and a reflow soldering process is used to solder the electrodes of the electrical component to the second trace layer.

[0028] In one embodiment, after an electrical element is disposed on one side of the support layer and an electrode of the electrical element is electrically connected to the conductive structure, the method for manufacturing the semiconductor structure further comprises:

[0029] A filler is filled between the surface of the electrical component facing the support layer and the film layer adjacent to and not in contact with the electrical component to form a filling portion.

[0030] In one embodiment, after the support layer is formed, the method for manufacturing the semiconductor structure further comprises: forming an alignment hole penetrating the support layer, forming an alignment structure in the alignment hole, wherein two opposite surfaces of the alignment structure are exposed to the alignment hole respectively;

[0031] The step of arranging the electrical component on one side of the support layer comprises: determining a first position of the electrical component on one side of the support layer according to the alignment structure, and arranging the electrical component at the first position; and / or,

[0032] The forming of the first trace layer on the side of the support layer away from the plastic encapsulation layer includes: determining a second position of the first trace layer on the side of the support layer away from the plastic encapsulation layer according to the alignment structure, and forming the first trace layer at the second position.

[0033] In one embodiment, the step of forming the alignment hole penetrating the support layer is performed simultaneously with the step of forming a plurality of through holes penetrating the support layer; and / or,

[0034] The step of forming an alignment structure in the alignment hole is performed simultaneously with the step of forming a conductive structure in each of the through holes.

[0035] In one embodiment, the material of the support layer is a molding compound.

[0036] In one embodiment, the electrical component includes at least one of a chip, an inductor, a resistor, and a capacitor.

[0037] A second aspect of an embodiment of the present application provides a semiconductor structure, wherein the semiconductor structure comprises:

[0038] The support layer is provided with a plurality of through holes penetrating the support layer; the material of the support layer is a plastic packaging material;

[0039] A plurality of conductive structures, each of which is located in the through hole, and two opposite surfaces of the conductive structure are exposed to the through hole respectively;

[0040] an electrical element, located on one side of the support layer, wherein an electrode of the electrical element is electrically connected to the conductive structure;

[0041] A plastic encapsulation layer, encapsulating at least the side surfaces of the electrical component;

[0042] The first trace layer is located on a side of the support layer away from the plastic packaging layer, and the first trace layer is electrically connected to the conductive structure.

[0043] The main technical effects achieved by the embodiments of the present application are:

[0044] The manufacturing method and semiconductor structure of the semiconductor structure provided in the embodiments of the present application form a support layer, which can provide support for the subsequent arrangement of electrical components and serve as a carrier for forming a first trace layer. The support layer does not need to be removed, and the first trace layer is electrically connected to the electrodes of the electrical components through the conductive structure arranged in the through holes of the support layer. Compared with the solution of first forming a rewiring layer on a silicon substrate, then mounting electrical components on the rewiring layer and finally grinding and removing the silicon substrate, there is no need to sacrifice the silicon substrate, which helps to reduce the manufacturing cost of the semiconductor structure and simplify the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0046] Figure 2 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0047] Figure 3 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0048] Figure 4 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0049] Figure 5 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0050] Figure 6 is a top view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0051] Figure 7 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;

[0052] Figure 8 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;

[0053] Fig. 9 is a partial cross-sectional view of a sixth intermediate structure provided by another exemplary embodiment of the present application;

[0054] Fig.10 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;

[0055] Fig.11 is a partial cross-sectional view of a seventh intermediate structure provided by another exemplary embodiment of the present application;

[0056] Fig.12 is a partial cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application;

[0057] Fig.13 is a partial cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application;

[0058] Fig.14 is a partial cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application;

[0059] Fig.15 is a partial cross-sectional view of an eleventh intermediate structure provided by an exemplary embodiment of the present application;

[0060] Fig.16 is a partial cross-sectional view of a twelfth intermediate structure provided by an exemplary embodiment of the present application;

[0061] Fig.17 is a partial cross-sectional view of a thirteenth intermediate structure provided by an exemplary embodiment of the present application;

[0062] Fig.18 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application. Specific embodiments

[0063] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0064] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0065] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0066] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0067] The present application embodiment provides a method for manufacturing a semiconductor structure. Figure 1 The method for manufacturing the semiconductor structure includes the following steps 110 to 150.

[0068] In step 110 , a support layer is formed, and a plurality of through holes penetrating the support layer are formed.

[0069] In step 120 , a conductive structure is formed in each of the through holes, and two opposite surfaces of the conductive structure are exposed to the through hole respectively.

[0070] In step 130, an electrical component is disposed on one side of the support layer, and an electrode of the electrical component is electrically connected to the conductive structure.

[0071] In step 140 , a plastic encapsulation layer is formed to encapsulate at least the side surfaces of the electrical component.

[0072] In step 150, a first trace layer is formed on a side of the support layer away from the plastic encapsulation layer, and the first trace layer is electrically connected to the conductive structure.

[0073] The manufacturing method of the semiconductor structure provided in the embodiment of the present application forms a support layer, which can provide support for the subsequent arrangement of electrical components and serve as a carrier for forming a first trace layer. The support layer does not need to be removed, and the first trace layer is electrically connected to the electrodes of the electrical components through the conductive structure arranged in the through holes of the support layer. Compared with the solution of first forming a rewiring layer on a silicon substrate, then mounting electrical components on the rewiring layer and finally grinding and removing the silicon substrate, there is no need to sacrifice the silicon substrate, which helps to reduce the manufacturing cost of the semiconductor structure and simplify the manufacturing process.

[0074] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0075] In step 110 , a support layer is formed, and a plurality of through holes penetrating the support layer are formed.

[0076] In one embodiment, the step of forming a support layer may include the following process: forming a support layer on a carrier.

[0077] In one embodiment, before forming the support layer on the carrier, the step of forming the support layer may further include: providing an adhesive layer on the carrier. The support layer is formed on the adhesive layer.

[0078] Through the above process, we can get Figure 2 The first intermediate structure shown. Figure 2 As shown, an adhesive layer 11 is formed on the carrier 12, and a support layer 20 is formed on a side of the adhesive layer 11 facing away from the carrier 12. The provision of the adhesive layer 11 facilitates the subsequent removal of the carrier 12.

[0079] In one embodiment, the shape of the carrier plate can be circular, rectangular or other shapes. The material of the carrier plate can be, for example, a stainless steel plate substrate, a polymer substrate, etc., so that the carrier plate is not easily deformed.

[0080] In one embodiment, the adhesive layer may be made of an easily peelable material so that the carrier can be peeled off later. For example, the adhesive layer may be made of a thermally releasable material that can lose its stickiness by heating. The adhesive layer has stickiness on both the side facing the carrier and the side facing away from the carrier.

[0081] In one embodiment, the material of the support layer is a plastic packaging material, which can make the support effect of the support layer better.

[0082] In one embodiment, after the step of forming the support layer, the method for manufacturing the semiconductor structure further comprises: disposing a metal layer on one side of the support layer.

[0083] Through this step, we can obtain Figure 3 The second intermediate structure shown. Figure 3 As shown, the metal layer 30 is formed on the side of the support layer 20 facing away from the carrier 10. The metal layer 30 may cover the support layer 20.

[0084] In one embodiment, the step of forming the metal layer 30 may include the following process: first, a seed layer is formed on the side of the support layer 20 away from the carrier 10 by a sputtering process; then, a metal material layer is formed on the seed layer by electroplating, and the metal layer 30 including the seed layer and the metal material layer is obtained. In this way, the thickness of the metal layer 30 can be relatively large, and the metal layer 30 can be prevented from cracking when a through hole is subsequently formed on the support layer 20 due to the small thickness of the metal layer 30.

[0085] In one example, after the step of providing a metal layer on one side of the support layer, the method for manufacturing the semiconductor structure further includes: removing the carrier, and mounting the obtained structure on the carrier with the metal layer facing the carrier.

[0086] Through this step, we can obtain Figure 4 The third intermediate structure shown. Figure 4 As shown, the metal layer 30 is attached to the carrier 18 via the adhesive layer 17. The adhesive layer 17 can be made of an easily peelable material so that the carrier can be peeled off later. For example, the adhesive layer 17 can be made of a thermally releasable material that can lose its stickiness by heating.

[0087] In another embodiment, the third intermediate structure may be formed by the following steps:

[0088] First, a carrier board is provided, and an adhesive layer is disposed on the carrier board.

[0089] Subsequently, a metal layer is mounted on the adhesive layer, wherein the metal layer is a prefabricated metal film.

[0090] Subsequently, a supporting layer is formed on the side of the metal film facing away from the carrier.

[0091] In one embodiment, the material of the metal layer 30 may be copper.

[0092] In one embodiment, after forming the support layer, the method for manufacturing the semiconductor structure further includes: forming an alignment hole penetrating the support layer.

[0093] After forming the alignment holes and through holes on the support layer, the following can be obtained: Figure 5 and Figure 6 The fourth intermediate structure shown. Figure 5 and Figure 6 As shown, a plurality of through holes 21 and alignment holes 22 are formed on the support layer 20, and both the through holes 21 and the alignment holes 22 penetrate the support layer 20. The alignment holes 22 may be annular. An alignment structure may be formed in the alignment hole 22, and the alignment structure may be used for alignment when setting the electrical components and the first trace layer.

[0094] In one embodiment, a laser process may be used to form the through hole 21 and the alignment hole 22 on the support layer 20 .

[0095] In one embodiment, the step of forming the alignment hole penetrating the support layer is performed simultaneously with the step of forming a plurality of through holes penetrating the support layer. This arrangement helps to simplify the manufacturing process of the semiconductor structure.

[0096] In step 120 , a conductive structure is formed in each of the through holes, and two opposite surfaces of the conductive structure are exposed to the through hole respectively.

[0097] Through this step, we can obtain Figure 7 The fifth intermediate structure shown. Figure 7 As shown, a conductive structure 41 is formed in each through hole 21 , and two opposite surfaces of the conductive structure 41 are respectively exposed from the through hole 21 , and the two opposite surfaces of the conductive structure 41 are respectively flush with the surface of the support layer 20 on the same side.

[0098] In one embodiment, the step of forming a conductive structure in each of the through holes may include the following process: using the metal layer as a cathode and using an electroplating process to form a conductive structure in the through hole.

[0099] In one embodiment, after the step of forming the alignment hole penetrating the support layer, the method for manufacturing the semiconductor structure further includes: forming an alignment structure in the alignment hole, wherein two opposite surfaces of the alignment structure are respectively exposed from the alignment hole. The arrangement of the alignment structure can make the surface of the support layer flush, which is convenient for the subsequent preparation of the first trace layer. The two opposite surfaces of the alignment structure are respectively flush with the surface of the support layer on the same side.

[0100] In one embodiment, the step of forming the alignment structure in the alignment hole is performed simultaneously with the step of forming the conductive structure in each through hole. This arrangement helps to simplify the manufacturing process of the semiconductor structure.

[0101] In one embodiment, the initially formed conductive structure may not expose the through hole where it is located on the surface facing away from the carrier, and the alignment structure may not expose the alignment hole where it is located on the surface facing away from the carrier. After the conductive structure and the alignment structure are formed, the surface of the supporting layer facing away from the carrier may be ground so that the conductive structure may expose the through hole where it is located on the surface facing away from the carrier, and the alignment structure may expose the alignment hole where it is located on the surface facing away from the carrier.

[0102] In step 130, an electrical component is disposed on one side of the support layer, and an electrode of the electrical component is electrically connected to the conductive structure.

[0103] In one embodiment, disposing the electrical element on one side of the support layer comprises: disposing the electrical element on a side of the support layer facing away from the metal layer.

[0104] In one embodiment, the electrical component includes at least one of a chip, an inductor, a resistor, and a capacitor.

[0105] In one embodiment, the step 130 of providing an electrical component on one side of the support layer, wherein the electrode of the electrical component is electrically connected to the conductive structure, comprises the following process:

[0106] First, a second trace layer electrically connected to the conductive structure is formed on one side of the support layer.

[0107] Through this step, we can obtain Figure 8 or Fig. 9 The sixth intermediate structure shown. Figure 8 As shown, the second trace layer 42 includes a plurality of first trace structures 421, and the first trace structures 421 are electrically connected to the conductive structure 41. Fig. 9As shown, the second trace layer 42 includes a first trace structure 421 and a plurality of second trace structures 422 located on the side of the first trace structure 421 away from the support layer 20, and the trace structure 422 is electrically connected to the first trace structure 421. Before forming the second trace structure 422, an insulating layer 50 covering the first trace structure 421 can be formed first, and a through hole 51 is opened on the insulating layer 50, and each through hole 51 exposes a part of the surface of the first trace structure 421; the second trace structure 422 is electrically connected to the first trace structure 421 through the conductive part 423 located in the through hole 51. The conductive part 243 and the second trace structure 422 can be formed simultaneously in the same process step. The support layer 20 is used as a carrier for forming the second trace layer 42. Compared with the solution of forming the second trace layer on the silicon substrate and then grinding and removing the silicon substrate, there is no need to sacrifice the silicon substrate, which helps to reduce the manufacturing cost of the semiconductor structure.

[0108] In one embodiment, the step of forming a second trace layer electrically connected to the conductive structure on one side of the support layer includes the following process: determining the position of the second trace layer on one side of the support layer according to the alignment structure, and forming the second trace layer at the determined position. In this way, the position accuracy of the second trace layer can be improved, which helps to improve the quality of the semiconductor structure.

[0109] Subsequently, the carrier plate is removed.

[0110] Subsequently, the support layer is used to provide support, an electrical component is arranged on a side of the second trace layer away from the support layer, and a reflow soldering process is used to solder the electrodes of the electrical component to the second trace layer.

[0111] The sixth intermediate structure is as follows Figure 8 As shown, this step can be used to obtain Fig.10 The seventh intermediate structure shown. Fig.10 As shown, the electrodes 63 of each electrical component 60 are respectively welded to the second trace layer 42 . Fig.10 In the illustrated embodiment, the electrical component 60 disposed on the side of the support layer 20 facing away from the metal layer 30 includes a passive device 61 and a chip 62. The chip 62 includes a solder pad 621, a protective layer 622 located on the side of the solder pad 621 facing the support layer 20, and an electrode 63. The protective layer 622 is provided with an opening exposing the solder pad 621. The electrode 63 is partially located in the opening of the protective layer and in contact with the solder pad 621, and the other part is exposed from the opening to lead out the solder pad 621. The electrode 63 may be a conductive ball. Since the reflow soldering process is carried out under high temperature conditions, if a carrier is used to provide support, the adhesive layer bonding the carrier to the support layer 20 will lose its viscosity due to heat, affecting the reflow soldering process. In the embodiment of the present application, the support layer can provide support, and the removal of the carrier does not affect the smooth progress of the soldering process.

[0112] In one embodiment, before the step of arranging electrical components on the side of the second trace layer facing away from the support layer, solder may be arranged on the surface of each conductive structure 41 facing away from the support layer 20. The solder may be solder paste.

[0113] In another embodiment, the step 130 of providing an electrical component on one side of the support layer, wherein the electrode of the electrical component is electrically connected to the conductive structure, comprises the following process:

[0114] First, the carrier plate is removed.

[0115] Subsequently, the support layer is used to provide support, an electrical component is arranged on one side of the support layer, and a reflow soldering process is used to solder the electrodes of the electrical component to the conductive structure.

[0116] Through this step, we can obtain Fig.11 The seventh intermediate structure shown. Fig.11 As shown, each electrode 63 of each electrical component 60 is electrically connected to a conductive structure 41. The reflow process is performed under high temperature conditions. If a carrier is used to provide support, the adhesive layer that bonds the carrier to the support layer 20 will lose its viscosity due to heat, affecting the reflow process. In the embodiment of the present application, the support layer can provide support, and the removal of the carrier does not affect the smooth progress of the reflow process.

[0117] In one embodiment, the step of arranging the electrical component on one side of the support layer includes: determining a first position of the electrical component on one side of the support layer according to the alignment structure, and arranging the electrical component at the first position. In this way, the accuracy of the arrangement position of the electrical component can be improved, which helps to improve the quality of the semiconductor structure.

[0118] In one embodiment, before the step of disposing electrical components on one side of the support layer, solder may be respectively disposed on the surface of each conductive structure 41 facing away from the support layer 20. The solder may be solder paste.

[0119] In one embodiment, after step 130 of disposing an electrical component on one side of the supporting layer and electrically connecting the electrode of the electrical component to the conductive structure, the method for manufacturing the semiconductor structure further includes: filling a filler to form a filling portion between the surface of the electrical component facing the supporting layer and a film layer adjacent to and not in contact with the electrical component.

[0120] The seventh intermediate structure is as follows Fig.10 or Fig.11 As shown, the film layers adjacent to and not in contact with the surface of each electrical element 60 facing the support layer are all support layers 20. Fig. 9When the second trace layer is shown in FIG, the film layer adjacent to and not in contact with the surface of each electrical component 60 facing the support layer is the insulating layer 50.

[0121] The seventh intermediate structure is as follows Fig.10 As shown, this step can be used to obtain Fig.12 The eighth intermediate structure shown. Fig.12 As shown, a filling portion 70 is formed between each electrical component 60 and the support layer 20, and the end of the filling portion 70 facing away from the support layer 20 abuts against the electrical component 60, and the end surface facing the support layer 20 abuts against the support layer 20. By forming the filling portion 70, the probability of voids in the subsequently formed plastic encapsulation layer can be reduced, and the quality of the semiconductor structure can be improved.

[0122] The filler forming the filling part 70 and the material of the supporting layer 20 may both contain filler particles. The size of the filler particles in the filling part 70 is smaller than that of the filler particles in the supporting layer 20 , which is more conducive to reducing the probability of voids in the plastic packaging layer.

[0123] In step 140 , a plastic encapsulation layer is formed to encapsulate at least the side surfaces of the electrical component.

[0124] In one embodiment, before step 140 , the method for manufacturing a semiconductor structure further includes: mounting a ninth intermediate structure on a carrier, with the support layer facing the carrier.

[0125] Through step 140, the following can be obtained: Fig.13 The ninth intermediate structure shown. Fig.13 As shown, the support layer 20 is mounted on the carrier 14 via the adhesive layer 13 , and the plastic encapsulation layer 80 encapsulates the side surfaces of each electrical component 60 and the surface facing away from the support layer 20 .

[0126] In one embodiment, before forming the plastic encapsulation layer 80, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities from the exposed surfaces of the electrical components 60 and the support layer 20 or the insulating layer 50, so that the plastic encapsulation layer 80 and the electrical components 60 and the support layer 20 or the insulating layer 50 can be more closely connected without delamination or cracking.

[0127] In one embodiment, the material of the plastic encapsulation layer 80 may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 80 may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer 80 may be formed by injection molding, compression molding, or transfer molding.

[0128] In step 150, a first trace layer is formed on a side of the support layer away from the plastic encapsulation layer, and the first trace layer is electrically connected to the conductive structure.

[0129] In one embodiment, before step 150 , the method for manufacturing the semiconductor structure further includes: removing the carrier 14 , and re-mounting the obtained structure on the carrier, with the plastic packaging layer facing the carrier.

[0130] Through this step, we can obtain Fig.14 The tenth intermediate structure shown. Fig.14 As shown, the plastic packaging layer 80 is attached to the carrier board 15 through the adhesive layer 16 .

[0131] In one embodiment, forming the first trace layer on the side of the support layer away from the plastic encapsulation layer includes the following process: etching the metal layer to form the first trace layer. In this way, the first trace layer is formed directly using the metal layer, which helps to simplify the manufacturing process of the semiconductor structure.

[0132] In another embodiment, forming the first trace layer on a side of the support layer away from the plastic encapsulation layer includes the following process:

[0133] First, the metal layer is removed.

[0134] Then, the support layer and the conductive structure are thinned on a side facing away from the support layer.

[0135] Through this step, we can obtain Fig.15 The eleventh intermediate structure shown. Fig.15 As shown, the surface of the support layer 20 away from the plastic encapsulation layer 80 is flush with the surface of the conductive structure 21 away from the plastic encapsulation layer 80. In this step, since the support layer and the conductive structure are not completely removed, only a part of them is thinned, the precision requirement of the thinning process is relatively low. Compared with the solution of removing the silicon substrate completely after forming a rewiring layer on the silicon substrate, it is easier to operate and helps to improve the yield of semiconductor products. In some embodiments, the support layer and the conductive structure can be thinned by a grinding process.

[0136] Subsequently, a first trace layer is prepared on a side of the support layer away from the plastic encapsulation layer.

[0137] Through the above steps, we can get Fig.16 The twelfth intermediate structure shown. Fig.16 As shown, the first trace layer 90 includes a plurality of third trace structures 91, and the third trace structures 91 are electrically connected to the conductive structure 41. Since the support layer needs to provide support in step 130, in order to ensure the support effect of the support layer, the thickness of the support layer is set to be relatively large. In this embodiment, the support layer 20 and the conductive structure 41 are thinned after the metal layer is removed, which can reduce the thickness of the final semiconductor structure, and is conducive to realizing the thinness of the semiconductor structure.

[0138] In one embodiment, the step of forming the first trace layer on the side of the support layer away from the plastic encapsulation layer includes the following process: determining the second position of the first trace layer on the side of the support layer away from the plastic encapsulation layer according to the alignment structure, and forming the first trace layer at the second position. In this way, the position accuracy of the first trace layer can be improved, which helps to improve the quality of the semiconductor structure.

[0139] In one embodiment, after the step 150 of forming the first trace layer on the side of the support layer away from the plastic encapsulation layer, the method for manufacturing the semiconductor structure may further include the following process:

[0140] First, an insulating film layer covering the first trace layer is formed, and through holes are opened on the insulating film layer, each of which exposes a partial surface of the third trace structure.

[0141] The material of the insulating film layer may be green oil or other insulating materials.

[0142] Subsequently, a plurality of conductive parts are formed, wherein a portion of each conductive part is located in a through hole of the insulating film layer and is electrically connected to the third trace structure.

[0143] Through the above steps, we can get Fig.17 The thirteenth intermediate structure shown. Fig.17 As shown, the insulating film layer 92 is provided with a plurality of through holes 921, each of which exposes a portion of the surface of a third trace structure 91; and a conductive portion 93 is formed on the surface of each third trace structure 91 away from the plastic encapsulation layer 80. Part of the conductive portion 93 is located in the through hole 921 of the insulating film layer 92, and the other part is exposed from the through hole 921. Fig.18 The conductive part 93 shown is a conductive ball. In other embodiments, the conductive part may be a columnar structure. The semiconductor structure can be soldered on the circuit board through the conductive part 93 to facilitate the connection between the semiconductor structure and the circuit board. The material of the conductive part 93 can be solder paste, metal tin, tin alloy or nickel gold.

[0144] In one embodiment, the method for manufacturing the semiconductor structure further comprises: removing the carrier and cutting the obtained structure to obtain a plurality of semiconductor structures. Each semiconductor structure comprises at least one electrical component.

[0145] Through this step, we can obtain Fig.18 The semiconductor structure shown.

[0146] The present application also provides a semiconductor structure. Fig.18 As shown, the semiconductor structure includes a support layer 20 , a plurality of conductive structures 41 , an electrical element 60 , a plastic encapsulation layer 80 and a first trace layer 90 .

[0147] The support layer 20 is provided with a plurality of through holes penetrating the support layer 20; the material of the support layer is a plastic encapsulation material. Each conductive structure 41 is located in one of the through holes, and two opposite surfaces of the conductive structure 41 are respectively exposed to the through hole. The electrical component 60 is located on one side of the support layer 20, the electrode 63 of the electrical component 60 is electrically connected to the conductive structure 41, and the plastic encapsulation layer 80 at least encapsulates the side of the electrical component 60. The first trace layer 90 is located on the side of the support layer 20 away from the plastic encapsulation layer 80, and the first trace layer 90 is electrically connected to the conductive structure 41.

[0148] The embodiment of the semiconductor structure provided in the embodiment of the present application and the embodiment of the method for manufacturing the semiconductor structure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0149] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0150] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0151] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: forming a support layer, and forming a plurality of through holes penetrating the support layer; forming a conductive structure in each of the through holes, wherein two opposite surfaces of the conductive structure are exposed to the through holes respectively; An electrical component is arranged on one side of the support layer, wherein an electrode of the electrical component is electrically connected to the conductive structure; forming a plastic encapsulation layer that at least encapsulates the side surfaces of the electrical component; A first trace layer is formed on a side of the support layer away from the plastic packaging layer, and the first trace layer is electrically connected to the conductive structure.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before forming a plurality of through holes penetrating the support layer, the method for manufacturing the semiconductor structure further includes: providing a metal layer on one side of the support layer; The forming of the conductive structure in each of the through holes comprises: using the metal layer as a cathode and using an electroplating process to form the conductive structure in the through hole; The step of arranging the electrical component on one side of the support layer comprises: arranging the electrical component on the side of the support layer away from the metal layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The forming of a first trace layer on a side of the support layer away from the plastic encapsulation layer comprises: Etching the metal layer to form a first trace layer; or, removing the metal layer; Performing a thinning process on the supporting layer and the conductive structure on a side facing away from the supporting layer; A first trace layer is prepared on a side of the support layer facing away from the plastic encapsulation layer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of the support layer comprises: forming the support layer on the carrier; The step of disposing an electrical component on one side of the support layer, wherein an electrode of the electrical component is electrically connected to the conductive structure, comprises: The carrier board is removed, the support layer is used to provide support, an electrical component is arranged on one side of the support layer, and the electrode of the electrical component is welded to the conductive structure by a reflow soldering process; or, forming a second trace layer electrically connected to the conductive structure on one side of the support layer; The carrier board is removed, the support layer is used to provide support, an electrical component is arranged on a side of the second trace layer away from the support layer, and the electrode of the electrical component is welded to the second trace layer by using a reflow soldering process.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After the electrical element is arranged on one side of the support layer and the electrode of the electrical element is electrically connected to the conductive structure, the method for manufacturing the semiconductor structure further includes: A filler is filled between the surface of the electrical component facing the support layer and the film layer adjacent to and not in contact with the electrical component to form a filling portion.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After the support layer is formed, the method for manufacturing the semiconductor structure further includes: forming an alignment hole penetrating the support layer, forming an alignment structure in the alignment hole, wherein two opposite surfaces of the alignment structure are exposed to the alignment hole respectively; The step of arranging the electrical component on one side of the support layer comprises: determining a first position of the electrical component on one side of the support layer according to the alignment structure, and arranging the electrical component at the first position; and / or, The forming of the first trace layer on the side of the support layer away from the plastic encapsulation layer includes: determining a second position of the first trace layer on the side of the support layer away from the plastic encapsulation layer according to the alignment structure, and forming the first trace layer at the second position.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The step of forming the alignment hole penetrating the support layer is performed simultaneously with the step of forming a plurality of through holes penetrating the support layer; and / or, The step of forming an alignment structure in the alignment hole is performed simultaneously with the step of forming a conductive structure in each of the through holes.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the support layer is plastic packaging material.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The electrical component includes at least one of a chip, an inductor, a resistor, and a capacitor.

10. A semiconductor structure, characterized in that: The semiconductor structure comprises: The support layer is provided with a plurality of through holes penetrating the support layer; the material of the support layer is a plastic packaging material; A plurality of conductive structures, each of which is located in the through hole, and two opposite surfaces of the conductive structure are exposed to the through hole respectively; an electrical element, located on one side of the support layer, wherein an electrode of the electrical element is electrically connected to the conductive structure; A plastic encapsulation layer, encapsulating at least the side surfaces of the electrical component; The first trace layer is located on a side of the support layer away from the plastic packaging layer, and the first trace layer is electrically connected to the conductive structure.

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