Printed circuit board

Abstract

The invention relates to a printed circuit board. The printed circuit board according to an embodiment includes: a first insulating layer; a second insulating layer, which is disposed on the first insulating layer, and which includes a cavity; the bonding pad is arranged on the first insulating layer, and the upper surface of the bonding pad is exposed through the cavity; wherein the cavity comprises: a first portion, the first portion comprising a first inner wall; and a second portion, the second portion comprising a second inner wall located below the first portion; wherein the inclination angle of the first inner wall is different from that of the second inner wall.

Description

[0001] Divisional application

[0002] This application is a divisional application of the Chinese invention application No. 202080073737.X. The invention name of the Chinese invention application No. 202080073737.X is “Printed Circuit Board” and the application date is October 21, 2020. Technical Field

[0003] Embodiments relate to a printed circuit board. Background Art

[0004] A printed circuit board (PCB) is a board with conductive material printed on an electrically insulating substrate.

[0005] The printed circuit board has a structure in which the mounting position of each device is determined and a circuit pattern of a connecting element is printed on a flat surface to be fixed, or has an embedded structure in which the device is embedded in the printed circuit board to densely mount various types of devices on a flat plate.

[0006] In recent years, in order to realize miniaturization and multifunctionality of electronic devices, printed circuit boards are used in a multilayer structure capable of high-density integration.

[0007] Typically, a conventional embedded printed circuit board uses a drill to form a cavity for embedding a device, or uses an auxiliary material such as a release film to mount the device, or uses sandblasting to form a cavity for embedding a device.

[0008] However, the conventional embedded printed circuit board has difficulty in realizing high-density integration due to the tolerance of the portion and depth of the processing area when using a drill as described above, and thus it is necessary to form a protective layer that is removed at the end.

[0009] In addition, it is difficult to form a cavity of a desired depth in a conventional embedded printed circuit board when using the above-mentioned sandblasting, and thus a stop layer must be formed.

[0010] In addition, in order to use auxiliary materials such as a release film, manual work must be performed, and thus there is a problem in that it is difficult to reduce the size of the cavity and the manufacturing cost increases.

[0011] On the other hand, when the protective layer or stop layer is used, a removal process must inevitably be performed after forming the cavity, thereby causing a problem of a complicated process. In addition, since the protective layer or stop layer is formed of metal, the protective layer or stop layer is removed by performing an etching process.

[0012] However, for the sandblasting or laser process, the protective layer or stop layer must have a thickness of at least 3 to 10 μm, and thus there is a problem in that when the protective layer or stop layer is removed, a portion of the pad exposed through the cavity is also removed. Summary of the invention

[0013] Technical issues

[0014] The embodiment provides a printed circuit board with a novel structure, a package substrate and a manufacturing method thereof.

[0015] In addition, the embodiment provides a printed circuit board, a package substrate, and a method of manufacturing the same, which can solve the reliability problem of the printed circuit board by forming a cavity through a plurality of processes.

[0016] In addition, the embodiments provide a printed circuit board, a package substrate, and a method of manufacturing the same, which can improve adhesion with a mold layer to be laminated later by allowing a portion of the insulating layer including the cavity to remain on the surface through the roughness.

[0017] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned may be clearly understood by those skilled in the art to which the proposed embodiments are described below.

[0018] Technical Solutions

[0019] According to an embodiment, a printed circuit board includes: a first insulating layer; a second insulating layer, which is arranged on the first insulating layer and includes a cavity; a pad, which is arranged on the first insulating layer and has an upper surface exposed through the cavity; wherein the cavity includes: a first part, which includes a first inner wall; and a second part, which includes a second inner wall located below the first part; wherein the inclination angle of the first inner wall is different from the inclination angle of the second inner wall.

[0020] Additionally, the cavity includes an inflection point between the first inner wall and the second inner wall.

[0021] In addition, the inflection point is positioned higher than an upper surface of the pad.

[0022] In addition, the inclination angle of the first inner wall is smaller than the inclination angle of the second inner wall.

[0023] In addition, the inclination angle of the first inner wall ranges from 50° to 60°, and the inclination angle of the second inner wall ranges from 60° to 80°.

[0024] In addition, the second insulating layer includes: a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, wherein a thickness of the first portion is smaller than a thickness of the second portion.

[0025] In addition, an upper surface of the first portion of the second insulating layer is located lower than an upper surface of the pad.

[0026] In addition, an upper width of the first portion of the cavity is greater than a lower width of the second portion of the cavity.

[0027] In addition, the cavity includes a bottom surface connected to the second inner wall and located higher than an upper surface of the first insulating layer.

[0028] In addition, the first inner wall, the second inner wall and the bottom surface have surface curvature.

[0029] In addition, a surface curvature of the first inner wall is different from a surface curvature of at least one of the second inner wall and the bottom surface.

[0030] On the other hand, according to an embodiment, a packaging substrate includes: a first insulating layer; a second insulating layer, which is arranged on the first insulating layer and includes a cavity; a solder pad, which is arranged on the first insulating layer and has an upper surface exposed through the cavity; a connecting portion, which is arranged on the solder pad; and an electronic device, which is arranged on the connecting portion, wherein the cavity includes: a first part, which includes a first inner wall; and a second part, which is located below the first part, and the second part includes a second inner wall connected to the first inner wall and a bottom surface connected to the second inner wall, wherein each of the first inner wall, the second inner wall and the bottom surface has a surface curvature, and the surface curvature of the first inner wall is different from the surface curvature of at least one of the second inner wall and the bottom surface.

[0031] In addition, the cavity includes an inflection point located higher than an upper surface of the pad between the first inner wall and the second inner wall, and an inclination angle of the first inner wall relative to the inflection point is smaller than an inclination angle of the second inner wall.

[0032] In addition, the packaging substrate further includes a molding layer disposed in the cavity and covering at least a portion of the electronic device, wherein the molding layer contacts the first inner wall, the second inner wall, and the bottom surface.

[0033] On the other hand, according to an embodiment, a method for manufacturing a printed circuit board includes: preparing a first insulating layer; forming a solder pad on the upper surface of the first insulating layer; forming a second insulating layer, which covers the solder pad on the upper surface of the first insulating layer; forming a mask having an opening on the second insulating layer; performing a laser process through the opening of the mask to form a first portion of the cavity, the first portion of the cavity opening a portion of the second insulating layer; and performing a plasma process on the second insulating layer below the first portion to form a second portion of the cavity, the second portion of the cavity exposing the upper surface of the solder pad while partially opening the second insulating layer, wherein the upper surface of the solder pad is covered by the second insulating layer before the second portion is formed.

[0034] In addition, the first portion includes a first inner wall having a first inclination angle, and the second portion includes a second inner wall having a second inclination angle different from the first inclination angle.

[0035] In addition, the second portion includes a bottom surface connected to the second inner wall and positioned higher than the upper surface of the first insulating layer, and the first inner wall, the second inner wall and the bottom surface have a surface curvature, and the surface curvature of the first inner wall is different from the surface curvature of at least one of the second inner wall and the bottom surface.

[0036] Effects of the Invention

[0037] The printed circuit board of the embodiment includes a cavity. In this case, the cavity 160 has a non-penetrating structure, rather than a penetrating structure that passes through the second insulating layer 120. In this case, the cavity 160 exposes the pad 141a disposed on the first insulating layer 110. In addition, the position of the bottom surface of the cavity 160 is lower than the upper surface of the pad 141a. Therefore, the embodiment does not need to form an additional layer to form the cavity 160, thereby reducing the number of processes. In addition, the embodiment can solve the loss caused by the change in thickness or shape of the pad 141a during the removal of the additional layer, thereby improving product reliability.

[0038] In addition, the first part of the cavity of the present embodiment is formed by a laser process, and the remaining second part of the cavity is formed by a plasma process after the laser process. Thus, the entire process time for forming the cavity can be shortened by forming the first part by a laser process, and a precise space can be ensured by forming the second part by a plasma process.

[0039] In addition, the cavity 160 of the printed circuit board of the embodiment includes: a first inner wall 161 having a first inclination angle relative to the inflection point 163; a second inner wall 162 having a second inclination angle; and a bottom surface 164 extending from the second inner wall 163. In this case, the first inner wall 161, the second inner wall 162, and the bottom surface 164 of the cavity 160 may not be flat, and may have a predetermined surface roughness. In addition, the electronic device may be mounted on the pad 141a in the cavity 160. In addition, the molding layer 190 may be provided in the cavity 160 to cover the electronic device. At this time, the inner wall and the bottom surface 164 of the cavity 160 may have a specific surface roughness, so that the surface area in contact with the molding layer 190 can be increased, and thus, the bonding strength can be improved during the molding of the molding layer 190. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a view showing a printed circuit board according to an embodiment.

[0041] Figure 2 yes Figure 1 Magnified image of the cavity area.

[0042] Figure 3 is a view showing a package substrate according to a first embodiment.

[0043] Figure 4 is a view showing a package substrate according to a second embodiment.

[0044] Figures 5 to 9 The manufacturing process is shown in sequence Figure 1 A view of a method of printing a circuit board is shown in FIG.

[0045] Fig.10 is a magnified micrograph of a cavity of a printed circuit board according to an embodiment. DETAILED DESCRIPTION

[0046] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] However, the spirit and scope of the present invention are not limited to parts of the embodiments, but may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and replaced within the spirit and scope of the present invention.

[0048] In addition, unless otherwise clearly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as the same meanings as those commonly understood by those skilled in the art to which the present invention belongs, and these terms, such as those defined in commonly used dictionaries, may be interpreted as having meanings consistent with their meanings in the context of the prior art. In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention.

[0049] In the present specification, unless specifically stated otherwise in a phrase, a singular form may also include a plural form, and when described in the form of “at least one (or more) A (and), B, and C”, at least one of all combinations that can be combined in A, B, and C may be included. In addition, terms such as first, second, A, B, (a), and (b) may be used to describe elements of embodiments of the present invention.

[0050] These terms are only used to distinguish an element from other elements, and these terms are not limited to the nature, order or sequence of elements. In addition, when an element is described as being "connected", "coupled" or "in contact with" another element, it may include not only the case where the element is directly "connected", "coupled" or "in contact with" other elements, but also the case where the element is "connected", "coupled" or "in contact with" another element between the element and other elements.

[0051] In addition, when described as being formed or disposed “on” or “below” each element, the term “on” or “below” may include not only a case where two elements are directly connected to each other, but also a case where one or more other elements are formed or arranged between the two elements. Furthermore, when expressed as “on” or “below”, not only an upper direction based on one element but also a lower direction may be included.

[0052] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] Figure 1 is a view showing a printed circuit board according to an embodiment, Figure 2 yes Figure 1 Magnified image of the cavity area.

[0054] refer to Figure 1 and Figure 2 The printed circuit board 100 includes a first insulating layer 110 , a second insulating layer 120 , a third insulating layer 130 , circuit patterns 141 , 142 , 143 , 144 , 145 , 146 , 147 , 148 , vias V1 , V2 , V3 , V4 , V5 , V6 , V7 , and protection layers 151 and 152 .

[0055] The first insulating layer 110 may be an insulating layer disposed at the center of the printed circuit board 100 .

[0056] The second insulating layer 120 is disposed on the first insulating layer 110 .

[0057] In addition, the third insulating layer 130 is disposed under the first insulating layer 110 .

[0058] At this time, although the first insulating layer 110 is shown in the drawings as being disposed at the central layer in the entire stacking structure of the printed circuit board 100, the embodiment is not limited thereto. That is, the first insulating layer 110 may be disposed at a position biased toward the upper side in the entire stacking structure of the printed circuit board 100, or conversely, may be disposed at a position biased toward the lower side.

[0059] The second insulating layer 120 is disposed on the first insulating layer 110. In this case, the second insulating layer 120 has a multi-layer structure. For example, the second insulating layer 120 may include: a second-first insulating layer 121, the second-first insulating layer is disposed on the upper surface of the first insulating layer 110; a second-second insulating layer 122, the second-second insulating layer is disposed on the upper surface of the second-first insulating layer 121; and a second-third insulating layer 123, the second-third insulating layer is disposed on the upper surface of the second-second insulating layer 122. At this time, although the second insulating layer 120 is shown in the drawings as having a three-layer structure, the embodiment is not limited thereto. That is, the second insulating layer 120 may be composed of two or fewer layers, or alternatively, the second insulating layer may be composed of a structure of four or more layers.

[0060] In addition, the third insulating layer 130 is disposed below the first insulating layer 110. In this case, the third insulating layer 130 has a multi-layer structure. For example, the third insulating layer 130 may include: a third-first insulating layer 131, the third-first insulating layer is disposed below the lower surface of the first insulating layer 110; a third-second insulating layer 132, the third-second insulating layer is disposed below the lower surface of the third-first insulating layer 131; and a third-third insulating layer 133, the third-third insulating layer is disposed below the lower surface of the third-second insulating layer 132. At this time, although the third insulating layer 130 is shown in the drawings as having a three-layer structure, the embodiment is not limited thereto. That is, the third insulating layer 130 may be composed of two or fewer layers, or alternatively, the third insulating layer may be composed of a structure of four or more layers.

[0061] In addition, although the printed circuit board 100 is shown as having a seven-layer structure based on the insulating layer in the drawings, the embodiment is not limited thereto. For example, the printed circuit board 100 may have 6 or fewer layers based on the insulating layer, or alternatively, may have 8 or more layers.

[0062] The first insulating layer 110 , the second insulating layer 120 , and the third insulating layer 130 are substrates on which circuits capable of changing wiring are formed, and may include a printed circuit board and an insulating substrate made of an insulating material and capable of forming a circuit pattern on a surface thereof.

[0063] For example, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be rigid or flexible. For example, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may include glass or plastic. In detail, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may include chemically strengthened / semi-tempered glass, such as soda-lime glass or aluminosilicate glass, or reinforced or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0064] In addition, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may include an optically isotropic film. For example, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0065] In addition, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be bent while having a partially curved surface. That is, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be partially flat and partially curved while having a curved surface. In detail, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may have a curved end, or have a surface including a random curvature, and be bent or curved.

[0066] In addition, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be a flexible substrate having flexible characteristics. In addition, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be a curved or bent substrate. At this time, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 represents the following electrical wiring: it connects multiple circuit parts into a wiring diagram in which electrical conductors can be reproduced based on circuit design. In addition, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may form a wiring for mounting the device and connecting it in a circuit, and mechanically fix the device in addition to the electrical connection function of the device.

[0067] Meanwhile, the second-first insulating layer 121, which is the lowermost layer of the second insulating layer 120, may be an insulating layer that does not contain glass fiber. Preferably, the second-first insulating layer 121 may be any one of resin coated copper (RCC), PPG (PREPER; glass fabric), and Ajinomoto laminated film (ABF). In this case, a portion of the second-first insulating layer 121 may be removed by a plasma process. At this time, when the second-first insulating layer 121 contains glass fiber, the plasma process may be affected, and thus, the second-first insulating layer 121 may contain an insulating material that does not contain glass fiber.

[0068] Circuit patterns may be provided on surfaces of the first, second, and third insulating layers 110 , 120 , and 130 .

[0069] For example, the first circuit pattern 141 may be disposed on the upper surface of the first insulating layer 110. In this case, a plurality of first circuit patterns 141 may be disposed on the upper surface of the first insulating layer 110 while being spaced apart from each other by a predetermined interval.

[0070] The second circuit pattern 142 may be disposed on the lower surface of the first insulating layer 110. A plurality of second circuit patterns 142 may be disposed on the lower surface of the first insulating layer 110 while being spaced apart from each other by a predetermined distance.

[0071] Furthermore, a circuit pattern may be provided on the surface of the second insulating layer 120. For example, a plurality of third circuit patterns 143 may be provided on the upper surface of the second-first insulating layer 121, while the plurality of third circuit patterns are spaced apart from each other by a predetermined interval. Furthermore, a plurality of fourth circuit patterns 144 may be provided on the upper surface of the second-second insulating layer 122, while the plurality of fourth circuit patterns are spaced apart from each other by a predetermined distance. In addition, a plurality of fifth circuit patterns 145 may be provided on the upper surface of the second-third insulating layer 123, while the plurality of fifth circuit patterns are spaced apart from each other by a predetermined interval.

[0072] Furthermore, a circuit pattern may be disposed on the surface of the third insulating layer 130. For example, a plurality of sixth circuit patterns 146 may be disposed on the lower surface of the third-first insulating layer 131, and the plurality of sixth circuit patterns may be spaced apart from each other by a predetermined interval. Furthermore, a plurality of seventh circuit patterns 147 may be disposed on the lower surface of the third-second insulating layer 132, and the plurality of seventh circuit patterns may be spaced apart from each other by a predetermined interval. In addition, a plurality of eighth circuit patterns 148 may be disposed on the lower surface of the third-third insulating layer 133, and the plurality of eighth circuit patterns may be spaced apart from each other by a predetermined interval.

[0073] Meanwhile, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147 and 148 as described above are wirings for transmitting electrical signals and may be formed of a metal material having high conductivity. To this end, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147 and 148 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn). In addition, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147 and 148 may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn). Preferably, the first to eighth circuit patterns 141 , 142 , 143 , 144 , 145 , 146 , 147 , and 148 may be formed of copper (Cu) which has high conductivity and is relatively inexpensive.

[0074] The first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147 and 148 may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP) and a semi-additive process (SAP), which are typical printed circuit board manufacturing processes and detailed descriptions thereof will be omitted herein.

[0075] Meanwhile, the first circuit pattern 141 may include a pad 141a, which is disposed on the upper surface of the first insulating layer 110 while being exposed through the cavity 160. The pad 141a may be electrically connected to an electronic device (described below) mounted in the cavity 160. For example, the pad 141a may be a wire bonding pad connected to the electronic device mounted in the cavity 160 through a wire. Alternatively, the pad 141a may be a flip chip bonding pad directly connected to a terminal of the electronic device mounted in the cavity 160. This will be described in more detail below.

[0076] Meanwhile, each of the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147 and 148 may include a pattern connected to a via for interlayer conduction, a pattern for signal transmission, a pad connected to an electronic device, and the like.

[0077] Vias V1, V2, V3, V4, V5, V6, and V7 are provided in the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130, and can electrically connect circuit patterns provided on different layers to each other. The vias V1, V2, V3, V4, V5, V6, and V7 can be provided to pass through at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. In addition, both ends of the vias V1, V2, V3, V4, V5, V6, and V7 are respectively connected to circuit patterns provided on different insulating layers, so that electrical signals can be transmitted.

[0078] The first via hole V1 may be provided in the first insulating layer 110. The first via hole V1 may be provided to pass through the upper and lower surfaces of the first insulating layer 110. The first via hole V1 may electrically connect the first circuit pattern 141 provided on the upper surface of the first insulating layer 110 and the second circuit pattern 142 provided on the lower surface of the first insulating layer.

[0079] A plurality of via holes may be provided in the second insulating layer 120. That is, the second via hole V2 may be provided in the second-first insulating layer 121. The second via hole V2 may electrically connect the first circuit pattern 141 provided on the upper surface of the first insulating layer 110 and the third circuit pattern 143 provided on the upper surface of the second-first insulating layer 121.

[0080] In addition, a third via hole V3 may be provided in the second-second insulating layer 122. The third via hole V3 may electrically connect the fourth circuit pattern 144 provided on the upper surface of the second-second insulating layer 122 and the third circuit pattern 143 provided on the upper surface of the second-first insulating layer 121.

[0081] In addition, a fourth via hole V4 may be provided in the second-third insulating layer 123. The fourth via hole V4 may electrically connect the fifth circuit pattern 145 provided on the upper surface of the second-third insulating layer 123 and the fourth circuit pattern 144 provided on the upper surface of the second-second insulating layer 122.

[0082] A plurality of via holes may be provided in the third insulating layer 130. That is, a fifth via hole V5 may be provided in the third-first insulating layer 131. The fifth via hole V5 may electrically connect the second circuit pattern 142 provided on the lower surface of the first insulating layer 110 and the sixth circuit pattern 146 provided on the lower surface of the third-first insulating layer 131.

[0083] In addition, a sixth via V6 may be provided in the third-second insulating layer 132. The sixth via V6 may electrically connect the seventh circuit pattern 147 provided on the lower surface of the third-second insulating layer 132 and the sixth circuit pattern 146 provided on the lower surface of the third-first insulating layer 131.

[0084] In addition, a seventh via hole V7 may be provided in the third-third insulating layer 133. The seventh via hole V7 may electrically connect the eighth circuit pattern 148 provided on the lower surface of the third-third insulating layer 133 and the seventh circuit pattern 147 provided on the lower surface of the third-second insulating layer 132.

[0085] Meanwhile, the via holes V1, V2, V3, V4, V5, V6 and V7 may be disposed to pass through only one of the first insulating layer 110, the second insulating layer 120 and the third insulating layer 130, or alternatively, the via holes V1, V2, V3, V4, V5, V6 and V7 may be disposed to pass through the plurality of insulating layers together. Thus, the via holes V1, V2, V3, V4, V5, V6 and V7 may connect circuit patterns disposed on surfaces of insulating layers spaced apart from each other by at least two or more insulating layers, rather than connecting circuit patterns disposed on surfaces of adjacent insulating layers.

[0086] Meanwhile, the via holes V1, V2, V3, V4, V5, V6 and V7 may be formed by filling the inside of a through hole (not shown) penetrating at least one of the plurality of insulating layers with a conductive material.

[0087] The through hole can be formed by any processing method, including mechanical, laser and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, routing and the like can be used. When the through hole is formed by laser processing, UV or CO2 laser methods can be used. When the through hole is formed by chemical processing, agents including aminosilane, ketones and the like can be used, thereby opening at least one of the multiple insulating layers.

[0088] On the other hand, laser processing is a cutting method that concentrates light energy on a surface, causing a portion of the material to melt and evaporate, thereby obtaining a desired shape, and laser processing can easily process complex shapes through computer programs, and can process composite materials that are difficult to cut by other methods.

[0089] Additionally, laser processing can have a cutting diameter of at least 0.005 mm and has broad advantages over the range of possible thicknesses.

[0090] As the laser processing drilling, YAG (yttrium aluminum garnet) laser, CO2 laser or ultraviolet (UV) laser is preferably used. YAG laser is a laser that can process both copper foil layer and insulating layer, while CO2 laser is a laser that can only process insulating layer.

[0091] When forming the through holes, the via holes V1, V2, V3, V4, V5, V6 and V7 may be formed by filling the inside of the through holes with a conductive material. The metal material forming the via holes V1, V2, V3, V4, V5, V6 and V7 may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni) and palladium (Pd), and the conductive material may be filled by any one of chemical plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet and dispensing.

[0092] Meanwhile, the protective layers 151 and 152 may be disposed on the surface of the outermost insulating layer among the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. For example, the first protective layer 151 may be disposed on the upper surface of the uppermost insulating layer among the plurality of insulating layers. For example, the first protective layer 151 may be disposed on the upper surface of the second-third insulating layer 123 which is the uppermost insulating layer among the second insulating layer 120. In addition, the second protective layer 152 may be disposed on the lower surface of the lowermost insulating layer among the plurality of insulating layers. For example, the second protective layer 152 may be disposed on the lower surface of the third-third insulating layer 133 which is the lowermost insulating layer among the third insulating layer 130.

[0093] The first protective layer 151 and the second protective layer 152 may both have openings. For example, the first protective layer 151 may have an opening that exposes the surface of the fifth circuit pattern 145 disposed on the upper surface of the second-third insulating layer 123 to be exposed.

[0094] In addition, the second protective layer 152 may have an opening that exposes a surface of the eighth circuit pattern to be exposed among the eighth circuit patterns 148 disposed on the lower surface of the third-third insulating layer 133 .

[0095] The first protective layer 151 and the second protective layer 152 may include an insulating material. The first protective layer 151 and the second protective layer 152 may include the following various materials: these materials can be cured by heating after being applied to protect the surface of the circuit pattern. The first protective layer 151 and the second protective layer 152 may be an anti-etching layer. For example, the first protective layer 151 and the second protective layer 152 may be a solder mask including an organic polymer material. For example, the first protective layer 151 and the second protective layer 152 may include an epoxy acrylate-based resin. In detail, the first protective layer 151 and the second protective layer 152 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first protective layer 151 and the second protective layer 152 may be any one of a photo solder mask, a cover layer, and a polymer material.

[0096] The thickness of each of the first protective layer 151 and the second protective layer 152 may be 1 μm to 20 μm. The first protective layer 151 and the second protective layer 152 may have a thickness of 1 μm to 15 μm. For example, the thickness of the first protective layer 151 and the second protective layer 152 may be 5 μm to 20 μm. When the thickness of the first protective layer 151 and the second protective layer 152 is greater than 20 μm, the thickness of the printed circuit board 100 may increase. When the thickness of the first protective layer 151 and the second protective layer 152 is less than 1 μm, the reliability of the circuit pattern included in the printed circuit board 100 may be deteriorated.

[0097] Meanwhile, the cavity 160 may be formed in the second insulating layer 120. In this case, the cavity 160 may be formed in the second insulating layer 120 composed of a plurality of layers. In this case, the cavity 160 may be provided to pass through at least one insulating layer of the second insulating layer 120 composed of the plurality of layers, and may not pass through at least another insulating layer.

[0098] That is, the normal cavity 160 is provided through the insulating layer. Thus, there is no insulating layer overlapping the cavity 160 in the vertical direction at the position where the cavity 160 is to be provided. For example, the cavity in the comparative example is provided to penetrate the second insulating layer 120 as a whole. For example, the cavity in the comparative example is provided to penetrate the lower surface of the second-first insulating layer 121 and the upper surface of the second-third insulating layer 123.

[0099] Different from this, at least one of the insulating layers vertically overlapping the cavity 160 at the position where the cavity is to be provided penetrates the cavity of the embodiment but does not penetrate at least another insulating layer.

[0100] That is, the cavity 160 in the embodiment is disposed in the second insulating layer 120. That is, the cavity 160 is disposed in the second-first insulating layer 121, the second-second insulating layer 122, and the second-third insulating layer 123.

[0101] In this case, the cavity in the structure of the printed circuit board of the comparative example is arranged to pass through all of the second-first insulating layer 121, the second-second insulating layer 122, and the second-third insulating layer 123. Thus, the upper surface of the first insulating layer located in the region vertically overlapping with the cavity is exposed in the printed circuit board of the comparative example. That is, in the printed circuit board of the comparative example, there is no second insulating layer (more specifically, no second-first insulating layer) on the upper surface of the first insulating layer vertically overlapping with the cavity.

[0102] In contrast, the cavity 160 in the printed circuit board 100 according to the embodiment penetrates the second-first insulating layer 121 and the second-second insulating layer 122 , but does not penetrate the second-third insulating layer 123 .

[0103] That is, the cavity 160 includes a first portion disposed in the second-first insulating layer 121, a second portion disposed in the second-second insulating layer 122, and a third portion disposed in the second-third insulating layer 123. Here, since the second insulating layer 120 in the embodiment has a three-layer structure, the cavity 160 is shown as being composed of the first portion to the third portion, but the embodiment is not limited thereto. For example, when the second insulating layer 120 has a double-layer structure, the cavity 160 may include only the first portion and the second portion. For example, when the second insulating layer 122 has a five-layer structure, the cavity 160 may include the first portion to the fifth portion. However, the cavity 160 in the embodiment is characterized in that the lowermost portion has a groove shape, rather than a through-hole shape.

[0104] The first portion may be provided in the second-first insulating layer 121. In this case, the first portion may be a trench provided in the second-first insulating layer 121 and forming a lower region of the cavity 160.

[0105] The second portion may be disposed in the second-second insulating layer 122. The second portion may be disposed in the second-second insulating layer 122 and may be a through hole forming a central area of ​​the cavity 160.

[0106] The third portion may be disposed in the second-third insulating layer 123. The third portion may be a through hole disposed in the second-third insulating layer 123 and forming an upper region of the cavity 160.

[0107] That is, the cavity 160 may be composed of a combination of the first portion, the second portion, and the third portion. In this case, the thickness of the first portion may be less than the thickness of the second-first insulating layer 121. Thus, the cavity 160 may be formed without penetrating the second-first insulating layer 121.

[0108] In other words, the second-first insulating layer 121 may include a first region R1 disposed on a region vertically overlapping the cavity 160 and a second region R2 excluding the first region R1. In addition, a thickness of the first region R1 may be different from a thickness of the second region R2.

[0109] Preferably, a thickness H1 of the second region R2 may be the thickness of the second-first insulating layer 121 .

[0110] The thickness H1 of the second region R2 may be 20 μm to 100 μm. For example, the thickness H1 of the second region R2 may be 25 μm to 50 μm. For example, the thickness H1 of the second region R2 may be 30 μm to 40 μm. When the thickness H1 of the second region R2 exceeds 100 μm, the overall thickness of the printed circuit board 100 may increase. When the thickness H1 of the second region R2 is less than 20 μm, the pad 141a or the first circuit pattern cannot be stably protected. In addition, when the thickness H1 of the second region R2 is less than 20 μm, the second-first insulating layer 121 may be easily affected by heat / pressure, etc. during the installation of electronic devices.

[0111] The thickness H2 of the first region R1 may be smaller than the thickness H1 of the second region. The thickness H2 of the first region R1 may be determined by the thickness H3 of the pad 141a. Preferably, the thickness H2 of the first region R1 may be smaller than the thickness H3 of the pad 141a.

[0112] Preferably, the thickness H3 of the pad 141a may be smaller than the thickness H1 of the second region R2. For example, the thickness H3 of the pad 141a may be 5 μm to 30 μm.

[0113] In addition, the thickness H2 of the first region R1 may be less than the thickness H3 of the pad 141a. For example, the thickness H2 of the first region R1 may be 3 μm to 25 μm. Thus, the first region R1 of the second-first insulating layer 121 is disposed on the first insulating layer 110. In this case, the first region R1 of the second-first insulating layer 121 may expose the upper surface of the pad 141a disposed on the first insulating layer 110.

[0114] The cavity 160 of the embodiment is not formed to penetrate the second insulating layer 120 to mount an electronic device, but at least a portion of the second insulating layer 120 (the first region of the second-first insulating layer 121 ) is formed on the first insulating layer 110 in a remaining state.

[0115] In this case, the thickness H2 of the remaining portion of the second insulating layer 120 is smaller than the thickness H3 of the pad 141a to be exposed on the cavity 160. Therefore, the cavity 160 in the embodiment can be formed to maintain the shape of the pad 141a without affecting the mounting of the electronic device on the pad 141a.

[0116] That is, the cavity forming process in the prior art is performed under the following conditions: a protective layer or a stop layer is provided on the first insulating layer so as to form the cavity in the above-mentioned multiple insulating layers. Thus, the cavity in the prior art can be formed to a desired depth (the depth that penetrates all the second insulating layers). However, the etching process for removing the protective layer or the stop layer in the related art must be performed after the cavity is formed. Thus, during the etching process for removing the protective layer or the stop layer, a portion of the pad provided on the first insulating layer in the related art is also removed, and thus, the reliability of the pad may be problematic. At this time, the thickness of the protective layer or the stop layer required for sandblasting or laser processing is 3 μm to 10 μm, and thus, there is a problem that during the etching process, the amount corresponding to the thickness of the protective layer or the stop layer in the entire thickness of the pad is removed.

[0117] Thus, in a state in which the protection layer or the stop layer is not formed, the cavity in the embodiment can be easily formed, thereby solving the reliability problem occurring in the process of removing the protection layer or the stop layer.

[0118] And, this allows the cavity 160 to be formed without penetrating the second-first insulating layer 121 by controlling process conditions for forming the cavity.

[0119] In this case, the cavity 160 may be formed through a plurality of processes.

[0120] That is, the cavity 160 may be divided into a first portion formed by the first process and a second portion formed by the second process.

[0121] The first portion may be formed on the entire region of the second-third insulating layer 123, the entire region of the second-second insulating layer 122, and a partial region of the second-first insulating layer 121. The first process may be a laser process.

[0122] That is, when the cavity 160 is formed in the embodiment, the first part 160a of the cavity 160 can be mainly formed by removing the entire area of ​​the second-third insulating layer 123, the entire area of ​​the second-second insulating layer 122, and a partial area of ​​the second-first insulating layer 121 through a laser process.

[0123] In this case, the first inner wall 161 of the first portion 160a may have a first inclination angle θ1. Preferably, the first inclination angle θ1 may be 50° to 60°. The first inner wall 161 of the first portion 160a may be a laser cut surface formed by a laser process.

[0124] The first portion 160a may have a first depth. In this case, the first depth of the first portion 160a may be greater than the second depth of the second portion 160b formed by the plasma process based on the total thickness of the second insulating layer 120. The first depth of the first portion 160a may be greater than 1 / 2 of the thickness of the second insulating layer 120.

[0125] The second portion 160 b may be formed below the first portion 160 a. The second portion 160 b may communicate with the first portion 160 a. For example, the second portion 160 b may be connected to the first portion 160 a to form a single cavity 160 .

[0126] An inflection point 163 may be formed between the first inner wall 161 of the first portion 160a and the second inner wall 162 of the second portion 160b. The inflection point 163 may indicate a portion where the inclination angles of the inner walls 161 and 162 of the cavity 160 change. For example, the inflection point 163 may be a point where the lowermost end of the first inner wall 161 of the first portion 160a intersects the uppermost end of the second inner wall 162 of the second portion 160b.

[0127] That is, the first portion 160a is formed by a laser process and the second portion 160b is formed by a plasma process, so that the inflection point 163 where the tilt angle (or curvature) changes may be located at a point where the first portion 160a and the second portion 160b intersect.

[0128] In this case, the position of the inflection point 163 may be higher than the pad 141a. In other words, the position of the lowermost end of the first portion 160a may be higher than the upper surface of the pad 141a. In other words, the position of the uppermost end of the second portion 160b may be higher than the upper surface of the pad 141a.

[0129] That is, the first portion 160a may be formed to a point higher than the upper surface of the pad 141a by a laser process. In this case, when the first portion 160a is formed to the point where the pad 141a is located, the pad 141a may be damaged by the laser during the process of forming the first portion 160a. Thus, the first portion 160a in the embodiment may be formed only to a point higher than the upper surface of the pad 141a.

[0130] In addition, the second portion 160b may have a second depth and be formed below the first portion 160a. The second depth may be smaller than the first depth of the first portion 160a.

[0131] The second portion 160b may include a second inner wall 162 connected to the first inner wall 161 and a bottom surface 164 connected to the second inner wall 162. The second inner wall 162 and the bottom surface 164 may be plasma-treated surfaces formed by a plasma process.

[0132] The bottom surface 164 may be located lower than the upper surface of the pad 141a. That is, when the bottom surface 164 is located higher than the pad 141a, a portion of the upper surface of the pad 141a is covered by the second insulating layer, which may affect the reliability of the product. Thus, the bottom surface 164 in the embodiment is located lower than the upper surface of the pad 141a.

[0133] The second inner wall 162 of the second portion 160b may have a second inclination angle θ2. In this case, the second inclination angle θ2 of the second inner wall 162 of the second portion 160b may be different from the first inclination angle θ1 of the first inner wall 161 of the first portion 160a. For example, the second inclination angle θ2 of the second inner wall 162 of the second portion 160b may be greater than the first inclination angle θ1 of the first inner wall 161 of the first portion 160a. For example, the second inclination angle θ2 may be 60° to 80°.

[0134] Meanwhile, the upper surface of the pad 141a covered by the second insulating layer 120 may be exposed during the process of forming the second portion 160b. In this case, the second portion 160b is formed by a plasma process, and thus, during the process of forming the second portion 160b, the second portion 160b may be accurately formed without damaging the surface of the pad 141a.

[0135] As described above, the maximum depth of the cavity 160 including the first portion 160a and the second portion 160b may be less than the total thickness of the second insulating layer 120. Also, the minimum depth of the cavity 160 may be greater than a depth obtained by subtracting the thickness of the pad 141a from the total thickness of the second insulating layer 120. Thus, in the embodiment, the upper surface of the first region R1 of the second-first insulating layer 121 of the second insulating layer 120 is higher than the upper surface of the first insulating layer 110 and lower than the upper surface of the pad 141a.

[0136] At the same time, reference Figure 2 The cavity 160 may include a first inner wall 161 of the first portion 160 a , a second inner wall 162 of the second portion 160 b , and a bottom surface 164 .

[0137] In this case, the first inner wall 161 of the first portion 160 a and the second inner wall 162 and the bottom surface 164 of the second portion 160 b may have a predetermined surface roughness.

[0138] In this case, the surface roughness of the first inner wall 161 of the first portion 160a may be different from the surface roughness of the second inner wall 162 of the second portion 160b. For example, the surface roughness of the first inner wall 161 of the first portion 160a may be greater than the surface roughness of the second inner wall 162 of the second portion 160b. Moreover, the surface roughness of the second inner wall 162 of the second portion 160b may be the same as the surface roughness of the bottom surface 164.

[0139] At this time, in the embodiment, no additional process is performed, so that the first inner wall 161 of the first part 160a of the cavity 160, the second inner wall 162 of the second part 160b, and the bottom surface 164 have a predetermined surface roughness. That is, in the embodiment, during the laser process and the plasma process for forming the cavity 160, different surface roughnesses as described above can be formed.

[0140] In other words, the bottom surface 164 of the cavity 160 may refer to the upper surface of the first region R1 of the second-first insulating layer 121. In addition, the height of the upper surface of the first region R1 of the second-first insulating layer 121 is not constant and may have deviations according to positions.

[0141] Meanwhile, the first inner wall 161 of the first portion 160 a and the second inner wall 162 of the second portion 160 b may have the first inclination angle θ1 and the second inclination angle θ2 as described above.

[0142] In this case, the inner walls 161 and 162 may be curved with a certain surface roughness, rather than being straight lines. Thus, the first inclination angle θ1 may be an inner angle between a first virtual line connecting the uppermost end of the first portion 160a and the lowermost end of the first portion 160a and a second virtual line corresponding to the upper surface of the second insulating layer 120.

[0143] In addition, the second inclination angle θ2 may be an inner angle between a third virtual line connecting the uppermost end of the second portion 160 b and the lowermost end of the second portion 160 b and a second virtual line corresponding to the upper surface of the second insulating layer 120 .

[0144] Figure 3 is a view showing a package substrate according to a first embodiment.

[0145] refer to Figure 3The packaging substrate 200 in the embodiment includes Figure 1 The printed circuit board 100 shown in FIG. 1 and the electronic device 180 mounted in the cavity 160 of the printed circuit board 100 .

[0146] refer to Figure 1 The printed circuit board 100 may be used as a packaging substrate 200 to mount the electronic device 180 .

[0147] At this time, since it is already Figure 1 The printed circuit board 100 is described in detail in , so its description will be omitted.

[0148] The printed circuit board 100 includes a cavity 160, and the pad 141a may be exposed in the cavity 160. In this case, the second-first insulating layer 121 may be provided in a region other than a region where the pad 141a is formed in the cavity 160. However, the height of the first region R1 of the second-first insulating layer 121 is lower than the height of the pad 141a. Thus, the electronic device 180 may be stably mounted on the pad 141a without being affected by the second-first insulating layer 121 on the first region R1. In other words, when the height of the first region R1 of the second-first insulating layer 121 is higher than the height of the pad 141a, the electronic device 180 may be mounted on the pad 141a in a tilted state, and further, a defect may occur in an electrical connection state with the pad 141a.

[0149] In this case, the electronic device 180 may be an electronic component disposed in the cavity 160 of the printed circuit board 100, and may be divided into an active device and a passive device. In addition, the active device is a device that actively uses a nonlinear portion, and the passive device refers to a device that does not use nonlinear characteristics even if there are linear and nonlinear characteristics. In addition, the passive device may include a transistor, an IC semiconductor chip, etc., and the passive device may include a capacitor, a resistor, an inductor, etc. The passive device is mounted on a general printed circuit board to increase the signal processing speed of the semiconductor chip as an active device, or to perform a filtering function.

[0150] Meanwhile, the connection portion 170 may be disposed on the pad 141a. The planar shape of the connection portion 170 may be a quadrilateral. The connection portion 170 is disposed on the pad 141a and electrically connects the electronic device 180 and the pad 141a while fixing the electronic device 180. To this end, the pad 141a may be formed of a conductive material. For example, the connection portion 170 may be a solder ball. The connection portion 170 may include a solder containing a heterogeneous component material. The solder may be formed of at least one of SnCu, SnPb, and SnAgCu. In addition, the heterogeneous material may include any one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

[0151] Meanwhile, the upper surface of the electronic device 180 may be located higher than the uppermost surface of the printed circuit board 100. However, the embodiment is not limited thereto, and the upper surface of the electronic device 180 may be disposed at the same height as the uppermost surface of the printed circuit board 100, or may be disposed lower than this height, depending on the type of the electronic device 180.

[0152] Figure 4 is a view showing a package substrate according to a second embodiment.

[0153] refer to Figure 4 The packaging substrate 200A in the embodiment includes Figure 1 The printed circuit board 100 shown in FIG. 1 and the electronic device 180A mounted in the cavity 160 of the printed circuit board 100 .

[0154] In addition, the package substrate 200A is disposed in the cavity 160 , and further includes a mold layer 190 covering the electronic device 180A.

[0155] The mold layer 190 may be selectively disposed in the cavity 160 to protect the electronic device 180A installed in the cavity 160 .

[0156] The mold layer 190 may be formed of a molding resin, such as EMC (Epoxy Molding Compound). However, the embodiment is not limited thereto, and the mold layer 190 may be formed of various resins for molding other than EMC.

[0157] refer to Figure 1 The printed circuit board 100 may be used as the packaging substrate 200A to mount the electronic device 180A.

[0158] The printed circuit board 100 includes a cavity 160, and the pad 141a may be exposed in the cavity 160. In this case, the second-first insulating layer 121 may be disposed in a region other than a region where the pad 141a is formed in the cavity 160. However, the height of the first region R1 of the second-first insulating layer 121 is lower than the height of the pad 141a. Thus, the electronic device 180A may be stably mounted on the pad 141a without being affected by the second-first insulating layer 121 on the first region R1. In other words, when the height of the first region R1 of the second-first insulating layer 121 is higher than the height of the pad 141a, the electronic device 180A may be mounted on the pad 141a in a tilted state, and further, a defect may occur in an electrical connection state with the pad 141a.

[0159] On the other hand, the inner walls 161, 162 and the bottom surface 164 of the cavity 160 in the embodiment are not flat, but may have a certain curvature. In other words, the inner walls 161 and 162 and the bottom surface 164 of the cavity 160 may have at least a certain level of surface roughness. That is, the inner walls 161 and 162 and the bottom surface 164 of the cavity 160 may have a roughness.

[0160] In the embodiment, the mold layer 190 is disposed to contact the inner walls 161 and 162 and the bottom surface 164 of the cavity 160. At this time, the inner walls 161 and 162 and the bottom surface 164 of the cavity 160 are not flat, but have a specific curvature. The structure of the cavity 160 as described above can increase the surface area contacting the mold layer 190, thereby improving the bonding force between the mold layer 190 and the printed circuit board 100.

[0161] According to the embodiment, the printed circuit board includes a cavity. In this case, the cavity 160 has a non-penetrating structure rather than a penetrating structure that passes through the second insulating layer 120. In this case, the cavity 160 exposes the pad 141a disposed on the first insulating layer 110. In addition, the position of the bottom surface of the cavity 160 is lower than the upper surface of the pad 141a. Thus, the embodiment does not need to form an additional layer to form the cavity 160, thereby reducing the number of processes. In addition, the embodiment can solve the loss caused by the change in thickness or shape of the pad 141a that occurs during the removal of the additional layer, thereby improving product reliability.

[0162] In addition, the cavity 160 of the printed circuit board of the embodiment includes: a first inner wall 161, which has a first inclination angle relative to the inflection point 163; a second inner wall 162, which has a second inclination angle; and a bottom surface 164, which extends from the second inner wall 163. In this case, the first inner wall 161, the second inner wall 162, and the bottom surface 164 of the cavity 160 may not be flat, and may have a predetermined surface roughness. In addition, the electronic device may be mounted on the pad 141a in the cavity 160. In addition, the molding layer 190 may be provided in the cavity 160 to cover the electronic device. At this time, the inner wall and the bottom surface 164 of the cavity 160 have a specific surface roughness so that the surface area contacting the molding layer 190 can be increased, thereby improving the bonding strength during molding of the molding layer 190.

[0163] Hereinafter, a method of manufacturing a printed circuit board according to an embodiment will be described with reference to the accompanying drawings.

[0164] Figures 5 to 9 The manufacturing process is shown in the order of the process Figure 1 A view of a printed circuit board method shown in FIG. Fig.10 is a magnified micrograph of a cavity of a printed circuit board according to an embodiment.

[0165] refer to Figure 5 , the first insulating layer 110 may be prepared, a first circuit pattern 141 and a second circuit pattern 142 may be formed on a surface of the first insulating layer 110 , and a first via hole V1 that passes through the first insulating layer 110 and electrically connects the first circuit pattern 141 and the second circuit pattern 142 may be formed.

[0166] The first insulating layer 110 may be a prepreg. The prepreg (PPG) has good fluidity and adhesion in a semi-cured state and is used as an intermediate substrate for a fiber-reinforced composite material, which is used as an adhesive layer and an insulating material layer, and is a molding material in which reinforcing fibers are pre-impregnated with a matrix resin. A molded product is formed by laminating these prepregs and curing the resin by heating / pressurizing. That is, the prepreg refers to a material in which a resin (BT / Epoxy, FR4, FR5, etc.) is impregnated in glass fibers and cured to a B stage.

[0167] That is, the first insulating layer 110 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber impregnated substrate, and may include an epoxy-based insulating resin when the first insulating layer 110 includes a polymer resin, or alternatively, it may include a polyimide-based resin.

[0168] That is, the first insulating layer 110 is a substrate on which a circuit capable of changing wiring is formed, and may include a printed circuit board and an insulating substrate made of an insulating material capable of forming a circuit pattern on a surface thereof.

[0169] A metal layer (not shown) is laminated on a surface of the first insulating layer 110. The metal layer may be formed by chemically plating a metal including copper on the first insulating layer 110. In addition, instead of forming the metal layer by chemically plating on the first insulating layer 110, a copper clad laminate (CCL) may be used.

[0170] When the metal layer is formed by chemical plating, roughness is provided on the upper surface of the first insulating layer 110 so that plating can be smoothly performed. Then, by patterning the metal layer, a first circuit pattern 141 and a second circuit pattern 142 are respectively formed on the upper surface and the lower surface of the first insulating layer 110. In this case, the first circuit pattern 141 may include a pad 141a connected to the electronic devices 180 and 180A, so as to be mounted on the first insulating layer 110 through the connection portion 170 thereafter.

[0171] As described above, the first and second circuit patterns 141 and 142 may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are typical printed circuit board manufacturing processes, and detailed descriptions thereof will be omitted herein.

[0172] Then, refer to Figure 6 , the process of laminating the second insulating layer 120 and the third insulating layer 130 on the upper surface and the lower surface of the first insulating layer 110 may be performed respectively.

[0173] In this case, the second insulating layer 120 has a multi-layer structure. For example, the second insulating layer 120 may include: a second-first insulating layer 121, which is disposed on the upper surface of the first insulating layer 110; a second-second insulating layer 122, which is disposed on the upper surface of the second-first insulating layer 121; and a second-third insulating layer 123, which is disposed on the upper surface of the second-second insulating layer 122.

[0174] In addition, the third insulating layer 130 has a multi-layer structure. For example, the third insulating layer 130 may include: a third-first insulating layer 131, which is disposed below the lower surface of the first insulating layer 110; a third-second insulating layer 132, which is disposed below the lower surface of the third-first insulating layer 131; and a third-third insulating layer 132, which is disposed below the lower surface of the third-second insulating layer 132.

[0175] In addition, a process of forming a circuit pattern on the surface of the second insulating layer 120 may be performed. For example, a process of forming a plurality of third circuit patterns 143 spaced apart from each other by a predetermined distance may be performed on the upper surface of the second-first insulating layer 121. In addition, a process of forming a plurality of fourth circuit patterns 144 spaced apart from each other by a predetermined distance may be performed on the upper surface of the second-second insulating layer 122. In addition, a process of forming a plurality of fifth circuit patterns 145 spaced apart from each other by a predetermined distance may be performed on the upper surface of the second-third insulating layer 123.

[0176] In addition, a process of forming a circuit pattern on the surface of the third insulating layer 130 may be performed. For example, a process of forming a plurality of sixth circuit patterns 146 spaced apart from each other by a predetermined distance on the lower surface of the third-first insulating layer 131 may be performed. In addition, a process of forming a plurality of seventh circuit patterns 147 spaced apart from each other by a predetermined distance on the lower surface of the third-second insulating layer 132 may be performed. In addition, a process of forming a plurality of eighth circuit patterns 148 spaced apart from each other by a predetermined distance on the lower surface of the third-third insulating layer 133 may be performed.

[0177] In addition, a process of forming via holes V1 , V2 , V3 , V4 , V5 , V6 , and V7 may be performed to electrically connect circuit patterns disposed on different layers among the first, second, and third insulating layers 110 , 120 , and 130 .

[0178] Then, refer to Figure 7 , a process of forming the cavity 160 in the cavity region of the second insulating layer 120 may be performed. In this case, the cavity 160 may be formed in the second insulating layer 120 composed of a plurality of layers.

[0179] In this case, the cavity 160 may be formed by a number of different processes.

[0180] That is, as a first cavity forming step for forming the cavity 160, a laser process may be performed.

[0181] In this case, before forming the first cavity, a mask 310 may be formed in the remaining area of ​​the upper surface of the second insulating layer 120 except for the area where the cavity 160 is to be formed. The mask 310 may be a metal layer. For example, the mask 310 may be formed of a metal material including copper.

[0182] That is, the mask 310 may be formed of a material that is not etched during a laser and plasma process, and may be, for example, a metal layer including copper.

[0183] The mask 310 may have a thickness of 0.1 μm to 12 μm. When the thickness of the mask 310 is less than 0.1 μm, the mask may not function properly, and thus, the cavity may be formed in an area where the cavity should not be formed. In addition, when the thickness of the mask 310 is greater than 12 μm, other circuit patterns may be damaged during the removal of the mask 310.

[0184] Then, if Figure 8 As shown in FIG. 1 , a first cavity forming step is performed on the second insulating layer 120 using a laser to form a first portion 160a of the cavity 160. Then, as shown in FIG. Fig. 9 As shown in FIG. 1 , a second cavity forming step is performed by a plasma process to form a second portion 160 b of the cavity 160 below the first portion 160 a .

[0185] Thus, the cavity 160 may include: a first portion, which is disposed in the second-first insulating layer 121; a second portion, which is disposed in the second-second insulating layer 122; and a third portion, which is disposed in the second-third insulating layer 123. Here, since the second insulating layer 122 in the embodiment has a three-layer structure, the cavity 160 is shown as consisting of the first portion to the third portion, but the embodiment is not limited thereto. For example, when the second insulating layer 120 has a double-layer structure, the cavity 160 may include only the first portion and the second portion. For example, when the second insulating layer 122 has a five-layer structure, the cavity 160 may include the first portion to the fifth portion. However, the cavity 160 in the embodiment is characterized in that the lowermost portion has a groove shape rather than a through-hole shape. Thus, as Fig.10 As shown in FIG. 1 , the cavity 160 is formed through a plurality of processes and may be divided into a plurality of parts having different inclination angles.

[0186] Then, if Fig. 9 As shown in FIG. 1 , after the mask 310 for forming the cavity 160 is removed, the protective layers 151 and 152 are formed on the outermost sides of the second insulating layer 120 and the third insulating layer 130 .

[0187] For example, the first protective layer 151 may be disposed on the upper surface of the insulating layer located on the top of the plurality of insulating layers. For example, the first protective layer 151 may be disposed on the upper surface of the second-third insulating layer 123, which is disposed on the uppermost portion of the second insulating layer 120. In addition, the second protective layer 152 may be disposed on the lower surface of the insulating layer disposed on the lowermost portion of the plurality of insulating layers. For example, the second protective layer 152 may be disposed on the lower surface of the third-third insulating layer 133, which is disposed on the lowermost portion of the third insulating layer 130.

[0188] The first protective layer 151 and the second protective layer 152 may both have openings. For example, the first protective layer 151 may have an opening that exposes the surface of the fifth circuit pattern 145 disposed on the upper surface of the second-third insulating layer 123 to be exposed.

[0189] In addition, the second protective layer 152 may have an opening that exposes a surface of the eighth circuit pattern to be exposed among the eighth circuit patterns 148 disposed on the upper surface of the third-third insulating layer 133 .

[0190] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. In addition, the features, structures, effects, etc. shown in each embodiment can be combined or modified by a person skilled in the art to which the embodiment belongs for other embodiments. Therefore, the contents related to such combinations and variations should be interpreted as being included in the scope of the embodiments.

[0191] The above mainly describes the embodiment, but this is only an example and does not limit the embodiment. It should be understood by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the present embodiment. For example, each component specifically shown in the present embodiment can be implemented by modification. And the differences related to these modifications and applications should be interpreted as being included in the scope of the embodiment set forth in the appended claims.

Claims

1. A circuit board, comprising: Basic insulation layer; an upper insulating layer disposed on the base insulating layer and comprising a cavity; a circuit pattern embedded in the upper insulating layer; an electronic device disposed in the cavity of the upper insulating layer; and a protective layer disposed on the upper insulating layer, wherein the upper insulating layer includes an inner wall surface forming the cavity, wherein the inner wall surface includes a first surface, a second surface, and a contact portion, the first surface having a first inclination angle relative to an upper surface of the basic insulating layer, the second surface extending from the first surface toward the protective layer and having a second inclination angle smaller than the first inclination angle relative to the upper surface of the basic insulating layer, and the first surface and the second surface contact each other in the contact portion, wherein the circuit pattern includes a portion overlapping with the second surface of the inner wall surface along a horizontal direction, wherein the portion of the circuit pattern includes an upper surface and a lower surface, and wherein a first distance in the vertical direction between an upper surface of the basic insulating layer and the contact portion is smaller than a second distance in the vertical direction between the portion of the circuit pattern and the upper surface of the basic insulating layer.

2. The circuit board according to claim 1, wherein: The portion of the circuit pattern does not overlap the first surface of the inner surface along the horizontal direction.

3. The circuit board according to claim 2, wherein: A third distance in the vertical direction between a lower surface of the portion of the circuit pattern and an upper surface of the insulating layer is equal to or greater than the first distance.

4. The circuit board according to claim 2, wherein: The electronic device overlaps the contact portion, the first surface, and the second surface along the horizontal direction.

5. The circuit board according to claim 4, wherein: The protective layer includes a through hole, the through hole passing through the upper surface of the protective layer and the lower surface of the protective layer, and Wherein, the width of the through hole in the horizontal direction is greater than the width of the electronic device.

6. The circuit board according to claim 2, further comprising: a first via electrode disposed between a lower surface of the portion of the circuit pattern and the base insulating layer, and The first via electrode overlaps with the first surface of the inner wall surface along the horizontal direction.

7. The circuit board according to claim 6, wherein: The first via electrode overlaps the contact portion and the electronic device along the horizontal direction.

8. The circuit board according to claim 7, further comprising: a second via electrode disposed on an upper surface of the portion of the circuit pattern, and The second via electrode overlaps with the second surface of the inner wall surface along the horizontal direction.

9. The circuit board according to claim 8, wherein: The second via electrode overlaps the first via electrode along the vertical direction.

10. The circuit board according to claim 2, further comprising: a top insulating layer disposed on the upper insulating layer and filling the cavity, and The top insulating layer fills the cavity to cover the exposed surface of the upper insulating layer including the first surface and the second surface.

11. The circuit board according to claim 10, wherein: A fourth distance in the vertical direction between an upper surface of the electronic device and an upper surface of the basic insulating layer is greater than a fifth distance in the vertical direction between an upper surface of the basic insulating layer and an upper surface of the upper insulating layer.

12. The circuit board according to claim 10, wherein: The top insulating layer includes a material different from that of the upper insulating layer.

13. A circuit board, comprising: Basic insulation layer; an upper insulating layer disposed on the base insulating layer and comprising a cavity; a circuit pattern embedded in the upper insulating layer; as well as an electronic device disposed in the cavity of the upper insulating layer; wherein the upper insulating layer includes an inner wall surface forming the cavity, wherein the inner wall surface includes a first surface, a second surface, and a contact portion, the first surface having a first inclination angle relative to an upper surface of the base insulating layer, the second surface extending from the first surface toward an upper surface of the upper insulating layer and having a second inclination angle smaller than the first inclination angle relative to the upper surface of the base insulating layer, and the first surface and the second surface contact each other in the contact portion, wherein the circuit pattern comprises a first circuit pattern and a second circuit pattern, the first circuit pattern overlaps with the first surface along a horizontal direction, the second circuit pattern overlaps with the second surface along the horizontal direction, and wherein the contact portion is positioned between a lower surface of the first circuit pattern and an upper surface of the second circuit pattern.

14. The circuit board according to claim 13, further comprising: a first via electrode, the first via electrode being disposed between the first circuit pattern and the second circuit pattern, and The first via electrode overlaps with the first surface and the contact portion along the horizontal direction.

15. The circuit board according to claim 13, wherein: The second circuit pattern does not overlap the first surface along the horizontal direction, and Wherein, a height of a lower surface of the second circuit pattern is greater than or equal to a height of the contact portion.

16. The circuit board according to claim 13, wherein: The electronic device overlaps the contact portion, the first surface, and the second surface along the horizontal direction.

17. The circuit board according to claim 13, further comprising: a protective layer, the protective layer being disposed on the upper insulating layer, wherein the protective layer comprises a through hole, the through hole passes through the upper surface of the protective layer and the lower surface of the protective layer, and Wherein, the width of the through hole in the horizontal direction is greater than the width of the electronic device.

18. The circuit board according to claim 14, further comprising: a second via electrode, the second via electrode being disposed on the second circuit pattern and overlapping the first via electrode in a vertical direction, and The second via electrode overlaps with the second surface of the inner wall surface along the horizontal direction.

19. The circuit board according to claim 13, further comprising: a top insulating layer disposed on the upper insulating layer and filling the cavity, and The top insulating layer fills the cavity to cover the exposed surface of the upper insulating layer including the first surface and the second surface.

20. The circuit board according to claim 19, wherein An upper surface of the electronic device is positioned higher than an upper surface of the upper insulating layer.

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