Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention relates to a semiconductor device, a preparation method thereof and electronic equipment. The preparation method of the semiconductor device comprises the steps that a through hole is formed in a stacking structure, and the through hole penetrates through a second source / drain electrode and an interlayer dielectric layer in the direction perpendicular to a substrate and at least extends to a first source / drain electrode; at least exposing the interlayer dielectric layer on the side wall of the through hole, and forming a self-assembled monomolecular layer in an adsorption relationship with the interlayer dielectric layer on the side wall, so that the first source / drain electrode and the second source / drain electrode which are not covered by the self-assembled monomolecular layer are exposed in the through hole; forming a contact layer on the first source / drain electrode and the second source / drain electrode by taking the self-assembled monomolecular layer as a mask; removing the self-assembled monomolecular layer; the contact layer on the first source / drain electrode and the contact layer on the second source / drain electrode are isolated through an interlayer dielectric layer; and forming a semiconductor layer on the side wall in the through hole, wherein the semiconductor layer is connected with the contact layers on the first source / drain electrode and the second source / drain electrode. The process is simple and low in cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor device and a method for manufacturing the same, as well as an electronic device, which can avoid surface oxidation of the source / drain, while having a simple process and low cost.

[0005] A method for preparing a semiconductor device is provided, comprising:

[0006] Providing a stacked structure at least comprising a first source / drain, an interlayer dielectric layer and a second source / drain formed in sequence in a direction perpendicular to the substrate;

[0007] forming a through hole in the stacked structure, wherein the through hole penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends at least to the first source / drain;

[0008] At least when the interlayer dielectric layer is exposed to the sidewall of the through hole, a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer is formed on the sidewall, so that the first source / drain and the second source / drain not covered by the self-assembled monolayer are exposed in the through hole;

[0009] Using the self-assembled monolayer as a mask, forming a contact layer on the first source / drain and the second source / drain;

[0010] removing the self-assembled monolayer; isolating the contact layer on the first source / drain and the contact layer on the second source / drain by the interlayer dielectric layer;

[0011] A semiconductor layer is formed on the side wall of the through hole, and the semiconductor layer is connected to the contact layer on the first source / drain and the second source / drain.

[0012] In some embodiments, the contact layer is an anti-oxidation conductive layer and / or a film layer for reducing Schottky barrier.

[0013] In some embodiments, the self-assembled monolayer includes long-chain organic molecules; the long-chain organic molecules are combined with the molecules of the interlayer dielectric layer by chemical adsorption.

[0014] In some embodiments, the long-chain organic molecule contains at least a fluoroalkyl group, and the fluoroalkyl group is the tail group of the long-chain organic molecule;

[0015] The contact layer is formed by an atomic layer deposition process; and the interlayer dielectric layer includes a non-metallic oxide layer.

[0016] In some embodiments, the interlayer dielectric layer has at least hydroxyl groups on its surface;

[0017] The fluoroalkyl group in the long-chain organic molecule is combined with the hydroxyl group on the surface of the interlayer dielectric layer through chemical adsorption.

[0018] In some embodiments, the interlayer dielectric layer includes: a silicon oxide film layer having hydroxyl groups on the surface.

[0019] In some embodiments, the self-assembled monolayer comprises 1H,1H,2H,2H-perfluorooctyltrichlorosilane and / or (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane;

[0020] In the process of forming the self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer, the first reaction gas at least includes ammonia.

[0021] In some embodiments, in the process of forming the contact layer in the through hole using the self-assembled monolayer as a mask, the reaction precursor includes at least pentamethyldiamine tantalum complex, the second reaction gas includes at least ammonia, and the reaction temperature is 225°C to 300°C.

[0022] In some embodiments, the self-assembled monolayer is removed by a steam hydrolysis process or a silane thermal decomposition process.

[0023] In some embodiments, the contact layer includes a tantalum metal nitride layer.

[0024] A semiconductor device is provided, which is prepared by the preparation method described in any one of the above embodiments.

[0025] In some embodiments, the thickness of each region of the semiconductor layer is the same.

[0026] In some embodiments, a pattern of the contact layer on the first source / drain electrode overlaps with a pattern of the first source / drain electrode;

[0027] A pattern of the contact layer on the second source / drain electrode overlaps with a pattern of the second source / drain electrode.

[0028] In some embodiments, the contact layer includes a tantalum metal nitride layer.

[0029] In some embodiments, the interlayer dielectric layer includes a silicon oxide film layer.

[0030] An electronic device is provided, comprising the semiconductor device described in any one of the above embodiments.

[0031] The semiconductor device and the method for manufacturing the semiconductor device provided in the present application may have / at least have the following advantages:

[0032] In the embodiment of the present application, a self-assembled monolayer adsorbed on the interlayer dielectric layer is selectively formed on the sidewall of the interlayer dielectric layer exposed to the through hole, and the self-assembled monolayer is used as a mask to form a contact layer on the sidewall of the first source / drain and the second source / drain exposed to the through hole. Therefore, the contact layer is formed between the semiconductor layer and the source electrode or the drain electrode by the embodiment of the present application, and the process is simple and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided in some embodiments of the present application; Figure 1 It is also a schematic cross-sectional view of a structure obtained after an anti-oxidation conductive layer is formed in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0035] Figure 2 Schematic diagram of the cross-sectional structure of a semiconductor device provided in some other embodiments of the present application;

[0036] Figure 3 Schematic diagram of the cross-sectional structure of a semiconductor device provided in some other embodiments of the present application;

[0037] Figure 4 A schematic diagram of a process for preparing a semiconductor device according to some embodiments of the present application;

[0038] Figure 5 A schematic cross-sectional view of a structure obtained after forming an insulating dielectric layer and a first source / drain in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0039] Figure 6A schematic cross-sectional view of a structure obtained after an interlayer dielectric layer is formed in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0040] Figure 7 A schematic cross-sectional view of a structure obtained after forming a second source / drain in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0041] Figure 8 A schematic cross-sectional view of a structure obtained after forming a through hole in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0042] Fig. 9 A schematic diagram of a cross-sectional structure of a structure obtained after a self-assembled monolayer is formed in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0043] Fig.10 Figure (a) is a chemical scale model diagram of FOTS; Fig.10 Figure (b) is a chemical scale model diagram of HDFTEOS;

[0044] Fig.11 A schematic cross-sectional view of a structure obtained after an anti-oxidation conductive layer is formed in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0045] Fig.12 Figure (a) shows a method for preparing a semiconductor device provided by some embodiments of the present application. x TaN during atomic layer deposition on self-assembled monolayers x The relationship between the number of atomic layer deposition cycles and the initial growth rate; Fig.12 FIG. (b) shows a method for preparing a semiconductor device provided in some embodiments of the present application. x TaN on copper layer during atomic layer deposition x The relationship between the number of atomic layer deposition cycles and the initial growth rate;

[0046] Fig.13 Figure (a) shows a method for preparing a semiconductor device provided by some embodiments of the present application. x TaN during atomic layer deposition on self-assembled monolayers x The relationship curve between atomic layer deposition thickness and Ta element content; Fig.13 FIG. (b) shows a method for preparing a semiconductor device provided in some embodiments of the present application. x When atomic layer deposition is performed on copper layer, TaN x The relationship curve between atomic layer deposition thickness and Ta element content.

[0047] Description of reference numerals:

[0048] 1. First source / drain; 2. Second source / drain; 3. Contact layer; 4. Semiconductor layer; 5. Interlayer dielectric layer; 6. Self-assembled monolayer; T. Through hole; 7. Gate dielectric layer; 8. Gate; 9. Insulating dielectric layer; 10. Substrate. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "located on...", "on the top surface of..." or "on the surface of...", it may be directly located on other elements or layers, located on the top surface of other elements or layers, or located on the surface of other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly ..." other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion.

[0052] It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures; the device may be included in alternative orientations (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0055] The present application provides a semiconductor device and a method for manufacturing the same, and a semiconductor device, wherein when a contact layer is formed between a semiconductor layer and a source or drain electrode, the contact layer on the source electrode and the drain electrode is formed in one process, the process is simple, and the manufacturing cost is low. The details will be described in the subsequent embodiments.

[0056] In one aspect, the present application provides a semiconductor device according to some embodiments.

[0057] See also Figure 1 In some embodiments, the semiconductor device may specifically include: a first source / drain 1, a second source / drain 2, a through hole T, a contact layer 3, a semiconductor layer 4 and an interlayer dielectric layer 5.

[0058] Among them, the first source / drain 1, the interlayer dielectric layer 5 and the second source / drain 2 are stacked in sequence in a direction perpendicular to the substrate; the through hole T penetrates the second source / drain 2 and the interlayer dielectric layer 5 in a direction perpendicular to the substrate, and extends to the first source / drain 1; the contact layer 3 is located at the side walls of the first source / drain 1 and the second source / drain 2 exposed to the through hole T; and the semiconductor layer 4 is located at the surfaces of the contact layer 3 and the interlayer dielectric layer 5 exposed to the through hole T.

[0059] The above-mentioned device is formed by the following method, providing a stacking structure which at least includes a first source / drain, an interlayer dielectric layer and a second source / drain formed in sequence in a direction perpendicular to a substrate; forming a through hole in the stacking structure, wherein the through hole penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends at least to the first source / drain; forming a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer at least on the side wall of the interlayer dielectric layer exposed to the through hole, so that the first source / drain and the second source / drain not covered by the self-assembled monolayer are exposed in the through hole; using the self-assembled monolayer as a mask, forming a contact layer on the first source / drain and the second source / drain exposed in the through hole; removing the self-assembled monolayer; the contact layer on the first source / drain and the contact layer on the second source / drain are isolated by the interlayer dielectric layer; forming a semiconductor layer on the side wall in the through hole, wherein the semiconductor layer is connected to the contact layer on the first source / drain and the second source / drain.

[0060] In the semiconductor device and method provided in the above embodiment, the contact layer 3 is selectively formed only on the first source / drain 1 and the second source / drain 2 exposed on the inner sidewall of the through hole, and a self-assembled monolayer is formed in other areas, and the self-assembled monolayer serves as a mask for forming the contact layer 3 on the first source / drain 1 and the second source / drain 2. The contact layer 3 can be only arranged on the first source / drain 1 or the second source / drain 2 to contact the semiconductor layer. This process does not require a complicated process to simultaneously form a contact layer with the same pattern as the first source / drain 1 or the second source / drain 2.

[0061] It should be noted that, in the embodiment of the present application, one of the first source / drain 1 and the second source / drain 2 is a source, and the other is a drain. Specifically, the following situations may be included: if the first source / drain 1 is a source, then the second source / drain 2 is a drain; or if the first source / drain 1 is a drain, then the second source / drain 2 is a source.

[0062] The present application embodiment does not specifically limit the constituent materials of the first source / drain 1 and the second source / drain 2. The constituent materials of the first source / drain 1 and the second source / drain 2 may be the same or different. The first source / drain 1 and the second source / drain 2 may be a single layer or a stacked multilayer structure, and the material of each layer may be the same or different.

[0063] As an example, the constituent materials of the first source / drain 1 and the second source / drain 2 may be metals, metal alloys, conductive metal oxides or conductive metal nitrides, etc. Specifically, the metal material may be, for example, tungsten (W), molybdenum (Mo), nickel (Ni), copper (Cu), tantalum (Ta), titanium (Ti) or aluminum (Al); the metal alloy material may be an alloy including two or more of the above metals, such as TiAl, an alloy material composed of two elements of titanium and aluminum; the conductive metal oxide may be, for example, indium tin oxide (ITO); the conductive metal nitride may be, for example, titanium nitride (TiN).

[0064] The contact layer is an anti-oxidation conductive layer and / or a film layer for reducing Schottky barrier.

[0065] The contact layer may be a double layer or a single layer. If it is a double layer, the second layer is formed immediately after the first layer is formed, and then the semiconductor layer is formed after the self-assembled monolayer is removed.

[0066] Exemplarily, the single-layer contact layer may only play the function of anti-oxidation and electrical conductivity, or may simultaneously play the functions of anti-oxidation and electrical conductivity and reducing the Schottky barrier between the source or drain electrode and the semiconductor layer.

[0067] The double layer may have only the function of anti-oxidation and electrical conductivity or only the function of reducing the Schottky barrier, or may have the functions of anti-oxidation and electrical conductivity and reducing the Schottky barrier respectively.

[0068] In the above embodiment, there is no protective layer on the upper surface of the second source / drain 2 , and the upper surface and the sidewalls are exposed at the same time. At this time, the exposed areas all form contact layers.

[0069] The present application is not limited to the above-mentioned embodiments. For example, the stacked structure includes a first source / drain 1 and a second source / drain 2, and a dielectric layer is provided on the second source / drain 2. The through hole penetrates the dielectric layer, the second source / drain 2 and the interlayer dielectric layer 5 to expose the first source / drain 1. A self-assembled monolayer is provided on all dielectric layers or insulating layers exposed in the hole, and other regions are the first source / drain 1 and the second source / drain 2 with complementary patterns to the dielectric layer or insulating layer.

[0070] There are different embodiments for the extension position of the through hole, wherein the through hole can extend to the upper surface of the first source / drain 1, or extend into the first source / drain 1 while exposing the sidewall, or penetrate the first source / drain 1 to expose the dielectric layer or substrate below the first source / drain 1. All exposed non-conductive layers can form a self-assembled monolayer as a mask for forming a contact layer on the first source / drain 1 and the second source / drain 2.

[0071] For ease of understanding and explanation, please combine Figure 1It is understood that the surface of the contact layer 3 in contact with the first source / drain 1 is defined as the first contact surface, and the surface connected to the first contact surface is defined as the first end surface; at the same time, the surface of the contact layer 3 in contact with the second source / drain 2 is defined as the second contact surface, and the surface connected to the second contact surface is defined as the second end surface. As an example, the contact layer 3 can be a conductive film, which extends on the side wall of the through hole T and can have two opposite end surfaces in the extension direction; that is, the first end surface and the second end surface are opposite end surfaces.

[0072] Please continue reading Figure 1 In some embodiments, the first end surface of the contact layer 3 may be flush with the surface of the first source / drain 1 close to the second source / drain 2. In some embodiments, the second end surface of the contact layer 3 may be flush with the surface of the second source / drain 2 close to the first source / drain 1. One end or the other end of the contact layer is the end surface between the main surfaces of the contact film layer.

[0073] As an example, the first end surface of the contact layer 3 may be flush with the surface of the first source / drain 1 close to the second source / drain 2; meanwhile, the second end surface of the contact layer 3 is also flush with the surface of the second source / drain 2 close to the first source / drain 1. Figure 1 As shown, the pattern of the contact layer 3 overlaps with the patterns of the first source / drain 1 and the second source / drain 2 , and is complementary to the pattern of the interlayer dielectric layer 5 exposed to the through hole T.

[0074] It can be understood that the contact layer between the first source / drain 1 and the semiconductor layer overlaps with the pattern of the first source / drain 1 exposed in the through hole. The contact layer between the second source / drain 2 and the semiconductor layer overlaps with the pattern of the second source / drain 2 exposed in the through hole.

[0075] The present embodiment of the application does not specifically limit the constituent material of the contact layer 3. As an example, in the present embodiment of the application, the contact layer 3 can be composed of a conductive material with high oxidation resistance; wherein the conductive material with high oxidation resistance refers to a conductive material with higher oxidation resistance than the first source / drain 1 and the second source / drain. Exemplarily, the conductive material with high oxidation resistance may include a conductive transition metal nitride material. The conductive transition metal nitride material may be, for example, tantalum metal nitride (TaN x ), vanadium (V) metal nitride, chromium (Cr) metal nitride, manganese (Mn) metal nitride, iron (Fe) metal nitride, cobalt (Co) metal nitride, nickel (Ni) metal nitride and the like.

[0076] For example, the conductive material with high oxidation resistance may also include tantalum metal oxide (TaO x). The bond energy of tantalum metal oxide is greater than that of tantalum metal nitride, so it has more stable chemical properties than tantalum metal nitride; and tantalum metal oxide is a high dielectric constant material (high-k material), which is also beneficial to improving the electrical performance of semiconductor devices.

[0077] Please continue reading Figure 1 In some embodiments, the thickness of the semiconductor layer 4 formed by ALD on the surface of the interlayer dielectric layer 5 exposed to the through hole T is equal to the thickness of the semiconductor layer 4 on the surface of the contact layer 3 .

[0078] See also Figure 2 In some embodiments, the semiconductor device may further include a gate dielectric layer 7 and a gate 8 .

[0079] The gate dielectric layer 7 is conformally covered on the semiconductor layer 4; the gate 8 is located on the gate dielectric layer 7 and fills the hole.

[0080] like Figure 2 As shown, in some embodiments, the channel direction between the first source / drain 1 and the second source / drain 2 generally extends in a direction perpendicular to the substrate.

[0081] It should be noted that when the channel direction between the first source / drain 1 and the second source / drain 2 generally extends in a direction perpendicular to the substrate, for example Figure 2 As shown, the gate 8 is surrounded by the semiconductor layer 4 and at least fills the through hole T; alternatively, the gate 8 may be formed on the outer wall of the semiconductor layer 4, and the through hole T may be filled with an insulating layer, a barrier layer and / or a back gate, etc.

[0082] In some other embodiments, see Figure 3 The gate 8 is located on the substrate 10 and extends in a direction perpendicular to the substrate 10. The semiconductor layer 4 surrounds the gate 8, and the gate dielectric layer 7 is located between the gate 8 and the semiconductor layer 4 to insulate the gate 8 and the semiconductor layer 4 from each other.

[0083] As an example, Figure 3 As shown, the channel direction between the first source / drain 1 and the second source / drain 2 can generally extend in a direction parallel to the substrate 10. Exemplarily, the first source / drain 1 and the second source / drain 2 can be arranged in the same layer in a direction parallel to the substrate 10, and the first source / drain 1 and the second source / drain 2 are spaced apart in a direction parallel to the substrate 10.

[0084] On the other hand, the present application also provides a method for preparing a semiconductor device according to some embodiments. It should be noted that the methods for preparing semiconductor devices in the embodiments of the present application can all be used to prepare corresponding semiconductor devices, so the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that those skilled in the art can understand the technical content of the present application.

[0085] See also Figure 4 In some embodiments, the method for preparing the semiconductor device may specifically include the following steps:

[0086] S100: providing a first source / drain, an interlayer dielectric layer, and a second source / drain stacked in sequence in a direction perpendicular to a substrate.

[0087] Of course, the stacked structure includes at least the stacked first source / drain, the interlayer dielectric layer and the second source / drain, and may also include an insulating layer below the first source / drain and an insulating layer above the second source / drain. Both the insulating layer and the interlayer dielectric layer may be silicon oxide.

[0088] S200: forming a through hole that penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends to the first source / drain. Of course, it can be a hole that penetrates the stacked structure, and the hole can extend to the first source / drain layer, or penetrate the first source / drain layer, or only extend into a partial area of ​​the first source / drain layer.

[0089] S300: forming a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer on the sidewall of the interlayer dielectric layer exposed to the through hole.

[0090] Of course, in the stacked structure, the insulating layer regions of the first source / drain and the second source / drain are removed in the through hole to form a self-assembled monolayer.

[0091] S400: Using the self-assembled monolayer as a mask, forming a contact layer on each area of ​​the sidewalls of the first source / drain and the second source / drain exposed to the through hole, wherein the contact layer has the same pattern as the corresponding first source / drain or second source / drain.

[0092] S500: Removal of self-assembled monolayer.

[0093] S600: forming a semiconductor layer on surfaces of the contact layer and the interlayer dielectric layer exposed to the through hole.

[0094] A semiconductor layer is formed in the through hole, covering each area and connecting with the contact layer. A channel is formed between two spaced contact layers.

[0095] In the preparation method provided in the above embodiment, a self-assembled monolayer adsorbed on the interlayer dielectric layer is selectively formed on the sidewall of the interlayer dielectric layer exposed to the through hole, and the self-assembled monolayer is used as a mask to form a contact layer on the sidewall of the first source / drain and the second source / drain exposed to the through hole. The process is simple and the cost is low.

[0096] It should be understood that although Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0097] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 1 to 3 ,as well as Figures 5 to 13 Understand some embodiments of the present application.

[0098] In step S100, refer to Figures 5 to 7 , providing a first source / drain 1, an interlayer dielectric layer 5 and a second source / drain 2 which are insulated and stacked in a direction perpendicular to the substrate.

[0099] As an example, in the embodiment of the present application, the substrate can be composed of any combination of semiconductor materials, insulating materials, conductor materials or their material types. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0100] The embodiment of the present application does not specifically limit the method of forming the first source / drain 1, the interlayer dielectric layer 5, and the second source / drain 2 in step S100. As an example, the first source / drain 1, the interlayer dielectric layer 5, and the second source / drain 2 may be formed by the following steps, for example:

[0101] A first conductive material layer, an interlayer dielectric material layer, and a second conductive material layer are sequentially formed in a direction perpendicular to the substrate; then, the second conductive material layer, the interlayer dielectric material layer, and the first conductive material layer are patterned simultaneously or sequentially to form a second source / drain 2, an interlayer dielectric layer 5, and a first source / drain 1, respectively.

[0102] This step can form a plurality of source electrodes and drain electrodes corresponding to a plurality of memory cells from a larger film layer, and isolate the source electrodes and drain electrodes between different memory cells. The source electrodes and drain electrodes can be block or strip structures of different layers. The source electrodes and drain electrodes can be initial patterns, and patterning will continue in the future.

[0103] In some embodiments, Figure 5 As shown, an insulating dielectric layer 9 may be formed on one side of the substrate. Based on this, in step S100, a first source / drain 1 and a second source / drain 2 may be formed on a surface of the insulating dielectric layer 9 away from the substrate.

[0104] In the preparation method provided in the above embodiment, the substrate is isolated from the first source / drain 1 by forming an insulating dielectric layer 9 to prevent current from flowing directly, which is beneficial to reducing short circuit and leakage phenomena in the semiconductor device and ensuring that the current flows along the designed circuit path. In addition, the insulating dielectric layer 9 can prevent electrons from escaping from the substrate or entering the substrate from the first source / drain 1, thereby improving the reliability of the semiconductor device.

[0105] The present embodiment of the application does not specifically limit the constituent material of the insulating dielectric layer 9. As an example, the insulating dielectric layer 9 may include but is not limited to a non-metallic oxide layer. The non-metallic oxide layer may be, for example, a silicon oxide (SiO2) layer.

[0106] It can be understood that the interlayer dielectric layer 5 is formed between the first source / drain 1 and the second source / drain 2 to achieve mutual insulation between the first source / drain 1 and the second source / drain 2 .

[0107] The present embodiment does not specifically limit the material of the interlayer dielectric layer 5. As an example, the material of the interlayer dielectric layer 5 may include but is not limited to low-k materials. The interlayer dielectric layer 5 may be a single layer or a stacked multilayer structure, and the material of each layer may be the same or different.

[0108] The present embodiment of the application does not specifically limit the constituent material of the interlayer dielectric layer 5. In some embodiments, the interlayer dielectric layer 5 may include but is not limited to a non-metallic oxide layer. The non-metallic oxide layer may be, for example, a silicon oxide layer.

[0109] As an example, the surface of the interlayer dielectric layer 5 may have at least hydroxyl groups.

[0110] Exemplarily, the interlayer dielectric layer 5 may include a silicon oxide film layer having hydroxyl groups on the surface. It is understood that the surface of the silicon oxide film layer will react with the moisture in the environment, form hydrogen bonds and adsorb water molecules, so a large number of hydroxyl groups (-OH) are formed on the surface of the silicon oxide film layer. In some embodiments, the hydroxyl groups on the surface of the interlayer dielectric layer 5 may be naturally adsorbed in the environment without the need for additional processing. In addition, after removing the self-assembled monolayer (SAM), the hydroxyl groups are processed at the same time and will not contact the metal oxide semiconductor layer.

[0111] As an example, after forming the interlayer dielectric layer 5 on the surface of one side of the first source / drain electrode 1 and before forming the second source / drain electrode 2, the following step may be further included: performing a planarization process on the surface of the interlayer dielectric layer 5 away from the first source / drain electrode 1. The planarization process may eliminate the undulations and unevenness of the surface of the interlayer dielectric layer 5, so that the interface between the second source / drain electrode 2 and the surface of the interlayer dielectric layer 5 is formed into a better morphology, which is conducive to improving the production yield of the preparation method and the reliability of the semiconductor device.

[0112] In step S200, refer to Figure 8 , forming a through hole T that penetrates the second source / drain 2 and the interlayer dielectric layer 5 in a direction perpendicular to the substrate and at least extends to the first source / drain 1. At this time, each source electrode and drain electrode formed in the previous step is patterned to form a final electrode structure, and the electrode far from the substrate is penetrated to form a ring electrode, or to form an electrode with a through hole. Whether the electrode close to the substrate is penetrated or partially penetrated, or only stays on the upper surface of the film layer depends on the needs.

[0113] The embodiment of the present application does not specifically limit the method of forming the through hole T in the above steps. As an example, the second source / drain 2, the interlayer dielectric layer 5 and the first source / drain 1 can be etched by a photolithography process, but is not limited to, to form the through hole T.

[0114] As an example, the second source / drain 2 , the interlayer dielectric layer 5 , and the first source / drain 1 may be etched by photolithography and etching to form a through hole T.

[0115] It should be noted that, in some embodiments, the through hole T may only extend to the top surface of the film layer of the first source / drain 1; in other embodiments, such as Figure 8 As shown, the through hole T can extend into the film layer of the first source / drain 1, but does not pass through the first source / drain 1; in some other embodiments, the through hole T can pass through the upper and lower surfaces of the film layer of the first source / drain 1. In this case, the first source / drain 1 has an annular through hole that surrounds the semiconductor layer on the side wall of the through hole.

[0116] In step S300, refer to Fig. 9 , a self-assembled monolayer 6 in an adsorption relationship with the interlayer dielectric layer 5 is formed on the sidewall of the interlayer dielectric layer 5 exposed to the through hole T.

[0117] In the above step S300, a self-assembled monolayer 6 is formed on the side wall of the interlayer dielectric layer 5 exposed to the through hole T, and the self-assembled monolayer 6 generally does not react with the precursor used to form the contact layer in the subsequent process, so that the contact layer will not be formed on the surface of the interlayer dielectric layer 5 exposed to the through hole T, thereby achieving selective deposition of the contact layer and ensuring that the contact layer can be accurately formed on the side wall of the first source / drain 1 and the second source / drain 2 exposed to the through hole T.

[0118] Self-Assembled Monolayer (SAM) refers to a film or coating with a single molecule thickness; specifically, it refers to a monolayer with a specific structure and function formed on a solid surface by utilizing the interaction between molecules and the self-assembly property. Self-assembled monolayers are usually constructed using surface active molecules (such as fatty acids, phospholipids, etc.) or organic molecules with self-assembly properties.

[0119] SAM generally includes a head group and a tail group (referred to as tail group). The tail group in the embodiment of the present application will be adsorbed to the interlayer dielectric layer 5 .

[0120] The present application embodiment does not specifically limit the constituent materials of the self-assembled monolayer 6. In some embodiments, the self-assembled monolayer 6 may include long-chain organic molecules. The long-chain organic molecules may be combined with molecules of the interlayer dielectric layer 5 (such as silicon oxide) by chemical adsorption.

[0121] As an example, the long-chain organic molecule contains at least a fluoroalkyl group, and the fluoroalkyl group is the tail group of the long-chain organic molecule, referred to as a fluoro(F)alkyl tail group.

[0122] Exemplarily, the organic molecules of the self-assembled monolayer 6 may include 1H,1H,2H,2H-perfluorooctyltrichlorosilane ((Cl)3Si(CH2)2(CF2)5CF3, abbreviated as FOTS), Fig.10 Figure (a) in FIG. 1 shows a chemical scale model of FOTS. For example, the organic molecules of the self-assembled monolayer 6 may include (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane ((CH3CH2O)3Si(CH2)2(CF2)7CF3, abbreviated as HDFTEOS), Fig.10 Figure (b) shows the chemical proportion model of HDFTEOS.

[0123] In some embodiments, the F-chain alkyl tail group in the long-chain organic molecule can be combined with the hydroxyl group on the surface of the interlayer dielectric layer 5 by chemical adsorption.

[0124] The interlayer dielectric layer 5 includes a silicon oxide film layer with hydroxyl groups for exemplary description. Both FOTS and HDFTEOS contain F chain alkyl tail groups, and thus will combine with the silicon oxide film layer with hydroxyl groups in the silicon dioxide layer rich in hydroxyl groups but not with the constituent materials of the first source / drain 1 and the second source / drain 2, thereby forming a self-assembled monolayer 6 on the surface of the silicon oxide film layer with hydroxyl groups exposed to the gate through hole T in the silicon dioxide layer.

[0125] Moreover, FOTS and HDFTEOS do not react with precursors used in most atomic layer deposition processes (such as Ta[N(CH3)2]5), so the self-assembled monolayer 6 will not be formed on the second source / drain 2, the surface of the first source / drain 1 exposed to the gate through hole T, or the surface of the second source / drain 2 exposed to the gate through hole T, and the contact layer 3 can be selectively deposited on the surface of the first source / drain 1 exposed to the through hole T and the surface of the second source / drain 2 exposed to the through hole T.

[0126] As an example, in the process of forming the self-assembled monolayer 6 in step S300, ammonia can be used as the first reaction gas but is not limited to it. The first reaction gas is used to provide a suitable environment and conditions, promote the adsorption and chemical reaction of organic molecules, and regulate the properties and structure of the self-assembled monolayer 6.

[0127] In step S400, refer to Fig.11 It is understood that the contact layer 3 is formed on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed at the through hole T using the self-assembled monolayer 6 as a mask.

[0128] In the above step S400, the contact layer 3 is only formed on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the through hole T, and is not formed on the interlayer dielectric layer covered by the self-assembled monolayer 6. Exemplarily, the self-assembled monolayer 6 can be a long-chain organic molecule containing a F-chain alkyl tail group, which does not react with most precursors, thereby achieving selective deposition of the contact layer 3; that is, the contact layer 3 is only deposited on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the through hole T.

[0129] The embodiment of the present application does not specifically limit the method of forming the contact layer 3 in the above steps. In some embodiments, the contact layer 3 can be formed on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the through hole T by using, but not limited to, an atomic layer deposition (ALD) process.

[0130] As mentioned above, in the embodiment of the present application, the contact layer 3 may be made of a conductive transition metal nitride material. The conductive transition metal nitride material may be, for example, tantalum metal nitride, vanadium metal nitride, chromium metal nitride, manganese metal nitride, iron metal nitride, cobalt metal nitride, nickel metal nitride, etc.

[0131] The transition metal indicates a transition metal element in the periodic table.

[0132] The material of the contact layer 3 includes tantalum metal nitride (TaN x ), ITO, materials containing Ir, etc. x For example, the process of forming the contact layer 3 by using the atomic layer deposition process may specifically include the following steps, such as:

[0133] The precursor and the second reaction gas are alternately introduced into the reaction chamber, so that the precursor and the second reaction gas are chemically adsorbed on the surface of the first source / drain 1 exposed to the through hole T and the surface of the second source / drain 2 exposed to the through hole T. The precursor may be, for example, a tantalum nitride precursor Ta[N(CH3)2]5, and the second reaction gas may be, for example, ammonia (NH3).

[0134] The present application embodiment does not specifically limit the reaction temperature in the above-mentioned atomic layer deposition process. As an example, when TaN is formed by atomic layer deposition process x During the process, the reaction temperature can be 225°C to 300°C; for example, the reaction temperature can be 225°C, 250°C, 275°C or 300°C, etc.

[0135] In step S500, please continue to refer to Figure 1 , remove the self-assembled monolayer 6.

[0136] The embodiment of the present application does not specifically limit the method of removing the self-assembled monolayer 6 in step S320. As an example, the self-assembled monolayer 6 can be removed by a water vapor hydrolysis process or a silane pyrolysis process, and the hydroxyl groups can be removed at the same time.

[0137] Please combine Figure 12 to Figure 13 Understand that the following uses the atomic layer deposition process to form the constituent materials including TaN x The contact layer 3 is taken as an example. In this example, the interlayer dielectric layer 5 includes a main structure, such as a low-K material such as silicon dioxide or silicon oxide containing C, and may also include an isolation layer between the silicon oxide and the semiconductor layer, such as an isolation layer that blocks H or O, and the isolation layer can adsorb a self-assembled monolayer.

[0138] The first source / drain electrode 1 and the second source / drain electrode 2 are both made of materials including copper, Ni, Mo, Ti, TiN, and the like.

[0139] exist Fig.12 Figure (a) and Fig.12 In Figure (b), the horizontal axis Number of ALD cycles represents the number of ALD cycles used to form the contact layer 3 (TaN x ) process, the number of atomic layer deposition cycles, the vertical axis Initialgrowth rate (A-cyvle -1 ) represents the initial growth rate.

[0140] exist Fig.12 In Figure (a), bare SiO2 shows TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate when atomic layer deposition is performed on an untreated silicon oxide layer; FOTS|SiO2 shows that when the silicon oxide layer is exposed on the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including FOTS, TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate of HDFTEOS|SiO2 is shown in Figure 6. When the silicon oxide layer is exposed to the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including HDFTEOS, TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate.

[0141] exist Fig.12 In Figure (b), bare Cu shows TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate when performing atomic layer deposition on a copper layer; FOTS|Cu shows that after the formation of a self-assembled monolayer of organic molecules including FOTS, TaN x Figure 2. The relationship between the number of atomic layer deposition cycles and the initial growth rate when performing atomic layer deposition on a copper layer. HDFTEOS|Cu shows that after the formation of a self-assembled monolayer of organic molecules including HDFTEOS, TaN x Figure 3. Relationship between the number of ALD cycles and the initial growth rate during ALD on a copper layer.

[0142] contrast Fig.12 Figure (a) and Fig.12As can be seen from Figure (b), the formation of the self-assembled monolayer 6 has little effect on the initial growth rate of the contact layer 3 on the surface of the first source / drain 1 exposed to the through hole T and the surface of the second source / drain 2 exposed to the through hole T; however, the growth of the contact layer 3 is hindered at the self-assembled monolayer 6. Therefore, the embodiment of the present application can suppress the growth of the contact layer 3 on the surface exposed by the interlayer dielectric layer 5 by forming the self-assembled monolayer 6, thereby achieving selective deposition of the contact layer 3 on the inner sidewall of the through hole.

[0143] exist Fig.13 Figure (a) and Fig.13 In Figure (b), the horizontal axis TaN x thickness It represents the contact layer 3 (TaN) formed by atomic layer deposition process. x ) thickness, vertical axis Ta LEISS (eV-counts-s -1 ) can be used to characterize the content of Ta element.

[0144] exist Fig.13 In Figure (a), bare SiO2 shows TaN x When ALD is performed on an untreated silicon oxide layer, the TaN obtained by ALD x The relationship curve between the thickness and the Ta element content; FOTS|SiO2 shows that when the silicon oxide layer is exposed on the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including FOTS, the TaN obtained by atomic layer deposition x The relationship curve between the thickness and the Ta element content; HDFTEOS|SiO2 shows that when the silicon oxide layer is exposed on the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including HDFTEOS, the TaN obtained by atomic layer deposition x The relationship curve between thickness and Ta element content.

[0145] exist Fig.13 In Figure (b), bare Cu shows TaN x When atomic layer deposition is performed on a copper layer, the TaN obtained by atomic layer deposition x The relationship curve between the thickness and the Ta element content; FOTS|Cu shows the TaN obtained by atomic layer deposition after the formation of the self-assembled monolayer 6 of organic molecules including FOTS x The relationship curve between the thickness and the Ta element content; HDFTEOS|Cu shows the TaN obtained by atomic layer deposition after the self-assembled monolayer 6 of organic molecules including HDFTEOS is formed. x The relationship curve between thickness and Ta element content.

[0146] contrast Fig.13 Figure (a) and Fig.13 It can be further seen from Figure (b) that the formation of the self-assembled monolayer 6 has little effect on the Ta content of the contact layer 3 on the surface of the first source / drain 1 exposed to the through hole T and the surface of the second source / drain 2 exposed to the through hole T; however, the growth of the contact layer 3 is hindered at the self-assembled monolayer 6. Therefore, the embodiment of the present application can suppress the growth of the contact layer 3 on the surface exposed by the interlayer dielectric layer 5 by forming the self-assembled monolayer 6, thereby achieving selective deposition of the contact layer 3.

[0147] In step S600, please refer to Figure 2 A semiconductor layer 4 is formed on the surfaces of the contact layer 3 and the interlayer dielectric layer 5 exposed to the through hole.

[0148] The embodiment of the present application does not specifically limit the constituent materials of the semiconductor layer 4. As an example, the semiconductor layer 4 can be a single-layer structure or a multi-layer structure. For example, the constituent materials of the semiconductor layer 4 can include but are not limited to metal oxides. The material of the metal oxide can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the semiconductor device is small (for example, the leakage current can be less than or equal to 15A), thereby ensuring a low refresh rate of the semiconductor device. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z Oa 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO, IAZO, IGO, IZO (Indium-Zinc-Oxide), IZ Ox and other materials. As long as the leakage current of the semiconductor device can meet the requirements, the specific adjustments can be made according to the actual situation.

[0149] The present embodiment does not specifically limit the method for forming the semiconductor layer 4. As an example, the semiconductor layer 4 may be formed on the surfaces of the contact layer 3 and the interlayer dielectric layer 5 exposed to the through hole by using, but not limited to, an atomic layer deposition process.

[0150] It can be understood that when the first source / drain 1 and / or the second source / drain 2 are penetrated, a closed ring is formed inside the corresponding first source / drain 1 and / or the second source / drain 2, and the first source / drain 1 and / or the second source / drain 2 can completely surround the semiconductor layer 4.

[0151] In some embodiments, after forming the semiconductor layer 4 in step S600, the method for preparing the semiconductor device may further include the following steps:

[0152] A gate dielectric layer 7 is conformally covered on a surface of the semiconductor layer 4 away from the contact layer 3 ; and a gate electrode 8 is formed on a surface of the gate dielectric layer 7 away from the semiconductor layer 4 .

[0153] As an example, the gate 8 may at least fill the through hole T. In some embodiments, the top surface of the gate 8 may also be higher than the top surface of the gate dielectric layer 7 .

[0154] The present embodiment of the present application does not specifically limit the constituent material of the gate dielectric layer 7. As an example, the constituent material of the gate dielectric layer 7 may include but is not limited to high dielectric constant materials. High-k materials may include, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and the like.

[0155] The present embodiment does not specifically limit the constituent material of the gate 8. As an example, the constituent material of the gate 8 may include but is not limited to indium zinc oxide (IZO), indium tin oxide, titanium nitride, tungsten, and the like.

[0156] In another aspect, the present application also provides an electronic device according to some embodiments. The semiconductor device may include the semiconductor device provided in any of the above embodiments.

[0157] The electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal, etc.

[0158] It can be understood that the structure of the semiconductor device can refer to the relevant descriptions in some of the above embodiments. The semiconductor device can also include other necessary elements or components, which are not limited in the embodiments of the present application.

[0159] In the embodiments of the present application, the semiconductor device adopts the semiconductor device provided in some of the aforementioned embodiments, which can avoid the reduction of the on-state current and is conducive to improving the electrical performance of the semiconductor device. It can be understood that the technical effects that can be achieved by the aforementioned semiconductor devices can also be achieved by the semiconductor device, which will not be described in detail here.

[0160] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a stacked structure at least comprising a first source / drain, an interlayer dielectric layer and a second source / drain formed in sequence in a direction perpendicular to the substrate; forming a through hole in the stacked structure, wherein the through hole penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends at least to the first source / drain; At least when the interlayer dielectric layer is exposed to the sidewall of the through hole, a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer is formed on the sidewall, so that the first source / drain and the second source / drain not covered by the self-assembled monolayer are exposed in the through hole; Using the self-assembled monolayer as a mask, forming a contact layer on the first source / drain and the second source / drain; removing the self-assembled monolayer; isolating the contact layer on the first source / drain and the contact layer on the second source / drain by the interlayer dielectric layer; A semiconductor layer is formed on the side wall of the through hole, and the semiconductor layer is connected to the contact layer on the first source / drain and the second source / drain.

2. The method for preparing a semiconductor device according to claim 1, wherein: The contact layer includes an anti-oxidation conductive layer and / or a film layer for reducing Schottky barrier.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The self-assembled monolayer includes long-chain organic molecules; the long-chain organic molecules are combined with the molecules of the interlayer dielectric layer through chemical adsorption.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The long-chain organic molecule contains at least a fluoroalkyl group, and the fluoroalkyl group is the tail group of the long-chain organic molecule; The contact layer is formed by an atomic layer deposition process; and the interlayer dielectric layer includes a non-metallic oxide layer.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The surface of the interlayer dielectric layer has at least hydroxyl groups; The fluoroalkyl group in the long-chain organic molecule is bonded to the hydroxyl group on the surface of the interlayer dielectric layer by chemical adsorption.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The interlayer dielectric layer includes a silicon oxide film layer with hydroxyl groups on the surface.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: The components of the self-assembled monolayer include 1H,1H,2H,2H-perfluorooctyltrichlorosilane and / or (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane; In the process of forming the self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer, the first reaction gas at least includes ammonia.

8. The method for preparing a semiconductor device according to claim 1, characterized in that: In the process of forming the contact layer in the through hole using the self-assembled monolayer as a mask, the reaction precursor at least includes pentamethyldiamine tantalum complex, the second reaction gas at least includes ammonia, and the reaction temperature is 225°C to 300°C.

9. The method for preparing a semiconductor device according to claim 1, wherein: The self-assembled monolayer is removed by using a water vapor hydrolysis process or a silane thermal decomposition process.

10. The method for preparing a semiconductor device according to claim 2, characterized in that: The contact layer includes a tantalum metal nitride layer.

11. A semiconductor device, characterized in that: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 10.

12. The semiconductor device according to claim 11, characterized in that The thickness of each region of the semiconductor layer is the same.

13. The semiconductor device according to claim 11, characterized in that The pattern of the contact layer on the first source / drain electrode overlaps with the pattern of the first source / drain electrode; The pattern of the anti-oxidation conductive layer on the second source / drain electrode overlaps with the pattern of the second source / drain electrode.

14. The semiconductor device according to claim 11, characterized in that The contact layer includes a tantalum metal nitride layer.

15. The semiconductor device according to claim 11, wherein: The interlayer dielectric layer includes a silicon oxide film layer.

16. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device as claimed in any one of claims 11 to 15.

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