Preparation method of chip packaging structure

Abstract

The invention relates to a preparation method of a chip packaging structure. The preparation method of the chip packaging structure comprises the following steps: forming a plurality of holes extending into a silicon wafer on the surface of one side of the silicon wafer; filling the holes with a conductive material to form a plurality of metal columns; removing a part of height of the silicon wafer, taking the exposed part of the metal column as a target metal column, and taking the unexposed part of the metal column as an internal metal column; mounting a silicon bridge structure on the surface of the silicon wafer among the plurality of target metal columns; forming a first rewiring layer on one side of the silicon bridge structure back to the silicon wafer and one side of the target metal column back to the silicon wafer; the first redistribution layer is connected with the silicon bridge structure and the target metal column; and inversely arranging a plurality of chips on one side of the first rewiring layer back to the silicon wafer. According to the preparation method of the chip packaging structure, the metal column and the target metal column which are high in height and diameter proportion and high in stability can be prepared, high-density interconnection of the chip and the target metal column is achieved, and the chip packaging yield and the integration level of the chip packaging structure are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for preparing a chip packaging structure. Background Art

[0002] As the semiconductor industry's demand for higher performance and higher integration chips continues to increase, traditional packaging technology is gradually unable to meet the demand. CoWoS-L (Chip-on-Wafer-on-Substrate with Logic) is an advanced integrated circuit packaging technology. CoWoS-L technology is mainly used to integrate logic chips with other functional chips (such as memory or RF chips) in the same package, providing higher performance and lower power consumption.

[0003] The existing CoWoS-L process includes: making a metal interconnect layer on a glass carrier, making copper pillars (mega pillars), attaching silicon bridges, continuing to make metal interconnects after plastic encapsulation and thinning, attaching chips on the front, plastic encapsulation and thinning again, removing the back glass, making back solder balls, and completing the process. However, the process of making copper pillars on glass carriers has certain defects: ① The bonding stability between the copper pillars and the glass carrier is not high, which may cause the copper pillars to fall off in subsequent processes; ② The copper pillars are made by dry film attachment and etching, and the density and height of the formed copper pillars are low, and the ratio of height to diameter is low, generally only 3:1 or 4:1, and it is impossible to form copper pillars with a high ratio of height to diameter, resulting in the inability to achieve high-density interconnection of the chip and a low integration of the chip packaging structure; ③ The glass carrier needs to be removed by debonding in the subsequent process, which is a complicated process, and debonding may cause surface damage and increased warping of the packaging structure.

[0004] Therefore, a method for preparing a chip packaging structure is needed, which can prepare copper pillars with a high height-to-diameter ratio, while ensuring the stability of the copper pillars in the packaging process, reducing damage to the chip packaging structure, and reducing the warping of the chip packaging structure. Summary of the invention

[0005] Therefore, the present invention provides a method for preparing a chip packaging structure to solve the problems in the prior art that the copper pillars have low density, low height-to-diameter ratio, poor stability and are easy to fall off, resulting in the chip packaging structure being unable to achieve high-density chip interconnection and low integration of the chip packaging structure.

[0006] The present invention provides a method for preparing a chip packaging structure, comprising the following steps:

[0007] Provide silicon wafers;

[0008] A plurality of holes are formed on a surface of one side of the silicon wafer, and the holes extend into the interior of the silicon wafer;

[0009] filling the holes with a conductive material to form a plurality of metal pillars;

[0010] Removing a portion of the height of the silicon wafer so that a portion of the height of the metal column is exposed on the remaining silicon wafer surface; the exposed portion is used as the target metal column, and the unexposed portion is used as the internal metal column;

[0011] Mounting a silicon bridge structure on the silicon wafer surface between a plurality of target metal pillars;

[0012] forming a first redistribution layer on a side of the silicon bridge structure facing away from the silicon wafer and a side of the target metal column facing away from the silicon wafer; the first redistribution layer connects the silicon bridge structure and the target metal column;

[0013] A plurality of chips are flip-chip mounted on the side of the first redistribution layer facing away from the silicon wafer.

[0014] Optionally, the ratio of the height to the diameter of the metal column is greater than or equal to 10:1;

[0015] The target metal pillars include a plurality of target metal pillar groups; the interval between adjacent target metal pillars in each target metal pillar group is less than 40 μm.

[0016] Optionally, the step of removing a portion of the height of the silicon wafer so that a portion of the height of the metal pillar is exposed on the surface of the remaining silicon wafer includes:

[0017] Removing a portion of the height of the silicon wafer from one side of the hole opening position, so that a portion of the height of the metal column is exposed on the remaining silicon wafer surface;

[0018] After the step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, the method further includes:

[0019] Thinning the side of the silicon wafer facing away from the target metal pillar until the silicon wafer and the internal metal pillar are removed;

[0020] A second redistribution layer is formed on the side of the target metal column facing away from the first redistribution layer; the second redistribution layer connects the silicon bridge structure and the target metal column.

[0021] Optionally, the silicon bridge structure includes a silicon bridge body and a silicon bridge metal column;

[0022] In the step of mounting a silicon bridge structure on the surface of a silicon wafer between a plurality of target metal pillars, the silicon bridge body is located on the surface of the silicon wafer, and the silicon bridge metal pillar is located on a side of the silicon bridge structure facing away from the silicon wafer;

[0023] The step of forming a first redistribution layer on a side of the silicon bridge structure facing away from the silicon wafer and a side of the target metal column facing away from the silicon wafer comprises:

[0024] A first redistribution layer is formed on the side of the silicon bridge metal column facing away from the silicon wafer and the side of the target metal column facing away from the silicon wafer; the first redistribution layer connects the silicon bridge metal column and the target metal column.

[0025] Optionally, the step of thinning the side of the silicon wafer facing away from the target metal pillar until the silicon wafer and the internal metal pillar are removed further includes:

[0026] Thinning a portion of the target metal pillar and a portion of the silicon bridge body.

[0027] Optionally, after the step of mounting a silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars and before the step of forming a first redistribution layer on the side of the silicon bridge structure facing away from the silicon wafer and the side of the target metal pillar facing away from the silicon wafer, the method further includes:

[0028] Forming a first plastic encapsulation layer on one side surface of the silicon wafer, wherein the first plastic encapsulation layer covers the target metal column and the silicon bridge structure;

[0029] Thinning the first plastic encapsulation layer until the target metal column and the silicon bridge metal column are exposed;

[0030] The first redistribution layer is formed on the side of the first plastic packaging layer facing away from the silicon wafer.

[0031] Optionally, the step of flip-chipping a plurality of chips on a side of the first redistribution layer facing away from the silicon wafer includes:

[0032] A first pad is formed on a side of the first redistribution layer facing away from the silicon wafer; the first pad is connected to the silicon bridge metal column and the target metal column through the first redistribution layer;

[0033] A plurality of chips are flip-chip mounted on a side of the first pad facing away from the first redistribution layer; and the chip pins of the chips are connected to the first pad.

[0034] Optionally, after the step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, thinning the side of the silicon wafer facing away from the target metal pillar until the step of removing the silicon wafer and the internal metal pillar further comprises:

[0035] A second plastic encapsulation layer is formed on a surface of the first redistribution layer facing away from the silicon wafer, wherein the second plastic encapsulation layer covers the plurality of chips and the first pad;

[0036] Thin the second plastic layer.

[0037] Optionally, the step of mounting a silicon bridge structure on the surface of a silicon wafer between a plurality of target metal pillars includes:

[0038] A silicon bridge structure is mounted on the surface of the silicon wafer between two adjacent target metal pillar groups.

[0039] Optionally, the step of removing a portion of the height of the silicon wafer so that a portion of the height of the metal pillar is exposed on the surface of the remaining silicon wafer includes:

[0040] A wet etching process or a dry etching process is used to remove a portion of the height of the silicon wafer, so that a portion of the height of the metal column is exposed on the remaining silicon wafer surface.

[0041] Optionally, the conductive material is copper; the metal column is a copper column;

[0042] The chips are HBM chips and SOC chips;

[0043] The material of the first plastic sealing layer is epoxy resin.

[0044] The technical solution of the present invention has the following advantages:

[0045] (1) The preparation method of the chip packaging structure provided by the present invention, on the one hand, by forming a metal column by drilling a hole inside a silicon wafer and filling it with a conductive material, a metal column with a high ratio of height to diameter and a high density can be formed, thereby realizing high-density interconnection between the chip and the copper column, improving the integration of the chip packaging structure, and thus reducing the volume of the chip packaging structure; on the other hand, after removing a portion of the height of the silicon wafer, due to the presence of an internal metal column inside the silicon wafer, the stability of the target metal column is increased, and it can be ensured that the target metal column will not fall off or shift in the subsequent steps of mounting the silicon bridge structure, forming the first redistribution layer, and connecting multiple chips, thereby improving the chip packaging yield. Therefore, the preparation method of the chip packaging structure provided by the present invention can prepare a metal column and a target metal column with a high ratio of height to diameter, a high density, and a high stability, thereby realizing high-density interconnection between the chip and the target metal column, improving the chip packaging yield and the integration of the chip packaging structure, and thus reducing the volume of the chip packaging structure.

[0046] (2) In the preparation method of the chip packaging structure provided by the present invention, the ratio of the height to the diameter of the metal column is greater than or equal to 10:1; the target metal column includes a plurality of target metal column groups; the spacing between adjacent target metal columns in each target metal column group is less than 40 μm. By preparing metal columns with a higher height to diameter ratio and a higher density, target metal columns with a higher height to diameter ratio and a higher density can be obtained, which can achieve high-density interconnection between the chip and the target metal columns, improve the integration of the chip packaging structure, and thereby reduce the volume of the chip packaging structure.

[0047] (3) In the preparation method of the chip packaging structure provided by the present invention, after the step of flip-chip setting a plurality of chips, the side of the silicon wafer facing away from the target metal column is thinned until the silicon wafer and the internal metal column are removed. Therefore, there is no need to remove the silicon wafer and the internal metal column through an additional process. The silicon wafer and the internal metal column are removed while thinning the back of the chip packaging structure, which simplifies the process flow and avoids the problem of damage to the packaging structure and increased warping caused by the debonding process of the glass carrier. Therefore, the preparation method of the chip packaging structure provided by the present invention can simplify the process flow, reduce damage to the chip packaging structure, and reduce the warping of the chip packaging structure by thinning the silicon wafer and the internal metal column.

[0048] (4) In the preparation method of the chip packaging structure provided by the present invention, in the step of mounting the silicon bridge structure on the surface of the silicon wafer between multiple target metal pillars, the silicon bridge body is located on the surface of the silicon wafer. Since the materials of the silicon bridge body and the silicon wafer are both silicon, the stability of the silicon bridge structure after mounting can be improved, thereby improving the stability and yield of the chip packaging structure.

[0049] (5) In the preparation method of the chip packaging structure provided by the present invention, after the step of mounting the silicon bridge structure and before the step of forming the first redistribution layer, a first plastic encapsulation layer is formed on one side surface of the silicon wafer, and the first plastic encapsulation layer is thinned until the target metal column and the silicon bridge metal column are exposed. This allows the target metal column and the silicon bridge metal column to be at the same height, thereby ensuring that the subsequently formed first redistribution layer simultaneously connects the silicon bridge structure and the target metal column. In addition, the first plastic encapsulation layer can also improve the stability of the target metal column and the silicon bridge structure, reduce electromagnetic interference, and protect the target metal column and the silicon bridge structure from damage, thereby improving the reliability and yield of the chip packaging structure.

[0050] (6) In the preparation method of the chip packaging structure provided by the present invention, after the step of flip-chip arranging multiple chips and before the step of thinning the silicon wafer, a second plastic encapsulation layer is formed on the surface of the first redistribution layer facing away from the silicon wafer, and the second plastic encapsulation layer is thinned. This can ensure that before the silicon wafer and the internal metal pillars are thinned and removed, the chip, the first redistribution layer, the first solder pad and other structures in the chip packaging structure are completely covered, which can reduce damage to the chip packaging structure. In addition, the second redistribution layer can also improve the stability of the chip, the first redistribution layer, the first solder pad and other structures, reduce electromagnetic interference, and protect the chip, the first redistribution layer, the first solder pad and other structures from damage, thereby improving the reliability and yield of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 It is a structural schematic diagram of a method for preparing a copper pillar in a chip packaging structure in the prior art;

[0053] Figure 2 A schematic diagram of a process for preparing a chip packaging structure according to an embodiment of the present invention;

[0054] Figure 3 The present invention is a schematic diagram of a specific process of a method for preparing a chip packaging structure according to an embodiment of the present invention.

[0055] Figure 4-Figure 14 The present invention is a schematic structural diagram of each step in a specific process of a method for preparing a chip packaging structure according to an embodiment of the present invention.

[0056] Description of reference numerals:

[0057] 100-silicon wafer; 200-glass carrier; 10-copper pillar; 11-target copper pillar; 12-internal copper pillar; 20-silicon bridge structure; 21-silicon bridge body; 22-silicon bridge copper pillar; 30-first plastic encapsulation layer; 40-first redistribution layer; 50-first solder pad; 60-chip; 61-HBM1 chip; 62-SOC chip; 63-HBM2 chip; 70-second plastic encapsulation layer; 80-second redistribution layer; 90-pin. DETAILED DESCRIPTION

[0058] The method for making copper pillars in the existing CoWoS-L process is as follows: Figure 1As shown, the copper pillar 10 is made by depositing a copper layer on the glass carrier 200, attaching a dry film, and etching, and the chip packaging process is continued on the formed copper pillar 10, for example: attaching a silicon bridge, continuing to make metal interconnection after plastic sealing and thinning, attaching a chip on the front, plastic sealing and thinning again, removing the back glass, and making back solder balls. However, there are certain defects in the process of making the copper pillar 10 on the glass carrier 200: ① The bonding stability between the copper pillar and the glass carrier is not high, which may cause the copper pillar to fall off in the subsequent process; ② The copper pillar is made by attaching a dry film and etching, and the pitch (spacing) of the formed copper pillar is greater than 80μm, and the density is low; the ratio of the height to the diameter of the copper pillar is low, generally only 3:1 or 4:1, and it is impossible to form a copper pillar with a high ratio of height to diameter, resulting in the inability to achieve high-density interconnection of the chip and a low integration of the chip packaging structure; ③ The glass carrier needs to be removed by debonding in the subsequent process, and the process is complicated, and the debonding may cause problems such as surface damage and increased warping of the packaging structure.

[0059] In order to solve the problems in the prior art that copper pillars have low density, low height-to-diameter ratio, poor stability and are easy to fall off, resulting in the inability of a chip packaging structure to achieve high-density chip interconnection and low integration of the chip packaging structure, the present invention provides a method for preparing a chip packaging structure, comprising: providing a silicon wafer; forming a plurality of holes on a surface of one side of the silicon wafer, the holes extending into the interior of the silicon wafer; filling the holes with a conductive material to form a plurality of metal pillars; removing a portion of the height of the silicon wafer so that a portion of the height of the metal pillars is exposed to the remaining silicon wafer surface; the exposed portion serves as a target metal pillar, and the unexposed portion serves as an internal metal pillar; mounting a silicon bridge structure on the silicon wafer surface between the plurality of target metal pillars; forming a first redistribution layer on a side of the silicon bridge structure facing away from the silicon wafer and a side of the target metal pillar facing away from the silicon wafer; the first redistribution layer connects the silicon bridge structure and the target metal pillar; and flip-chip arranging a plurality of chips on a side of the first redistribution layer facing away from the silicon wafer.

[0060] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0061] Example 1

[0062] like Figure 2 As shown, this embodiment provides a method for preparing a chip packaging structure, comprising:

[0063] S101, provide silicon wafer.

[0064] S102, forming a plurality of holes on a surface of one side of the silicon wafer, wherein the holes extend into the interior of the silicon wafer.

[0065] In specific implementation, the method of forming multiple holes can be laser drilling, dry etching or wet etching, etc., which is not limited in this embodiment. Multiple holes are perpendicular to the surface of the silicon wafer, and the ratio of hole height to diameter is relatively high, and the density is also relatively high.

[0066] S103, filling the holes with a conductive material to form a plurality of metal pillars.

[0067] In a specific implementation, the conductive material may be a metal material, such as copper, silver, tin, etc., and the metal column may be a copper column, a silver column, a tin column, etc.

[0068] S104, removing a portion of the height of the silicon wafer, so that a portion of the height of the metal column is exposed on the remaining silicon wafer surface; the exposed portion is used as the target metal column, and the unexposed portion is used as the internal metal column.

[0069] In specific implementation, the target metal column is a part of the chip packaging structure finally prepared. According to the actual requirements of the chip packaging structure, a part of the height of the silicon wafer is removed to expose the target metal column.

[0070] S105, mounting a silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars.

[0071] In specific implementation, the silicon bridge structure can be mounted using a DAF film or other adhesive film materials.

[0072] S106, forming a first redistribution layer on a side of the silicon bridge structure facing away from the silicon wafer and a side of the target metal column facing away from the silicon wafer; the first redistribution layer connects the silicon bridge structure and the target metal column.

[0073] S107, flip-chipping a plurality of chips on a side of the first redistribution layer facing away from the silicon wafer.

[0074] During specific implementation, the multiple chips may be the same chip or different chips.

[0075] The preparation method of the chip packaging structure provided in the present embodiment, on the one hand, by forming a metal column by drilling a hole inside the silicon wafer and filling it with a conductive material, a metal column with a high ratio of height to diameter and a high density can be formed, thereby realizing high-density interconnection between the chip and the copper column, improving the integration of the chip packaging structure, and thus reducing the volume of the chip packaging structure; on the other hand, after removing a portion of the height of the silicon wafer, due to the presence of an internal metal column inside the silicon wafer, the stability of the target metal column is increased, and it can be ensured that the target metal column will not fall off or shift in the subsequent steps of mounting the silicon bridge structure, forming the first redistribution layer, and connecting multiple chips, and the chip packaging yield can be improved. Therefore, the preparation method of the chip packaging structure provided in the present embodiment can prepare a metal column and a target metal column with a high ratio of height to diameter, a high density, and a high stability, thereby realizing high-density interconnection between the chip and the target metal column, improving the chip packaging yield and the integration of the chip packaging structure, and thus reducing the volume of the chip packaging structure.

[0076] Further, in some embodiments, the ratio of the height to the diameter of the metal pillar is greater than or equal to 10:1;

[0077] The target metal pillars include a plurality of target metal pillar groups; the interval between adjacent target metal pillars in each target metal pillar group is less than 40 μm.

[0078] In specific implementation, the heights of the target metal column and the internal metal column can be set as required. In some embodiments, the height of the internal metal column is relatively small, for example, the height of the internal metal column is the metal column diameter D, and the ratio of the height to the diameter of the target metal column is greater than or equal to 9:1. In other embodiments, the height of the internal metal column can be set to other multiples of the metal column diameter D as required, which is not limited in this embodiment.

[0079] In the preparation method of the chip packaging structure provided in this embodiment, the ratio of the height to the diameter of the metal column is greater than or equal to 10:1; the target metal column includes a plurality of target metal column groups; the spacing between adjacent target metal columns in each target metal column group is less than 40μm. By preparing metal columns with a higher height to diameter ratio and a higher density, target metal columns with a higher height to diameter ratio and a higher density can be obtained, which can achieve high-density interconnection between the chip and the target metal columns, improve the integration of the chip packaging structure, and thereby reduce the volume of the chip packaging structure.

[0080] Furthermore, in some embodiments, the step of removing a portion of the height of the silicon wafer so that a portion of the height of the metal pillar is exposed on the surface of the remaining silicon wafer includes:

[0081] Removing a portion of the height of the silicon wafer from one side of the hole opening position, so that a portion of the height of the metal column is exposed on the remaining silicon wafer surface;

[0082] After the step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, the method further includes:

[0083] Thinning the side of the silicon wafer facing away from the target metal pillar until the silicon wafer and the internal metal pillar are removed;

[0084] A second redistribution layer is formed on the side of the target metal column facing away from the first redistribution layer; the second redistribution layer connects the silicon bridge structure and the target metal column.

[0085] In the preparation method of the chip packaging structure provided in the present embodiment, after the step of flip-chip setting a plurality of chips, the side of the silicon wafer facing away from the target metal column is thinned until the silicon wafer and the internal metal column are removed. Therefore, there is no need to remove the silicon wafer and the internal metal column through an additional process. The silicon wafer and the internal metal column are removed while thinning the back of the chip packaging structure, which simplifies the process flow and avoids the problem of damage to the packaging structure and increased warping caused by the debonding process of the glass carrier. Therefore, the preparation method of the chip packaging structure provided by the present invention can simplify the process flow, reduce damage to the chip packaging structure, and reduce the warping of the chip packaging structure by thinning the silicon wafer and the internal metal column.

[0086] Further, in some embodiments, the silicon bridge structure includes a silicon bridge body and a silicon bridge metal column;

[0087] In the step of mounting a silicon bridge structure on the surface of a silicon wafer between a plurality of target metal pillars, the silicon bridge body is located on the surface of the silicon wafer, and the silicon bridge metal pillar is located on a side of the silicon bridge structure facing away from the silicon wafer;

[0088] The step of forming a first redistribution layer on a side of the silicon bridge structure facing away from the silicon wafer and a side of the target metal column facing away from the silicon wafer comprises:

[0089] A first redistribution layer is formed on the side of the silicon bridge metal column facing away from the silicon wafer and the side of the target metal column facing away from the silicon wafer; the first redistribution layer connects the silicon bridge metal column and the target metal column.

[0090] In the preparation method of the chip packaging structure provided in the present embodiment, in the step of mounting the silicon bridge structure on the surface of the silicon wafer between multiple target metal pillars, the silicon bridge body is located on the surface of the silicon wafer. Since the materials of the silicon bridge body and the silicon wafer are both silicon, the stability of the silicon bridge structure after mounting can be improved, thereby improving the stability and yield of the chip packaging structure.

[0091] Furthermore, in some embodiments, the step of thinning the side of the silicon wafer facing away from the target metal pillar until the silicon wafer and the internal metal pillar are removed further includes:

[0092] Thinning a portion of the target metal pillar and a portion of the silicon bridge body.

[0093] Furthermore, in some embodiments, after the step of mounting a silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars and before the step of forming a first redistribution layer on the side of the silicon bridge structure facing away from the silicon wafer and the side of the target metal pillar facing away from the silicon wafer, the method further includes:

[0094] Forming a first plastic encapsulation layer on one side surface of the silicon wafer, wherein the first plastic encapsulation layer covers the target metal column and the silicon bridge structure;

[0095] Thinning the first plastic encapsulation layer until the target metal column and the silicon bridge metal column are exposed;

[0096] The first redistribution layer is formed on the side of the first plastic packaging layer facing away from the silicon wafer.

[0097] In the preparation method of the chip packaging structure provided in the present embodiment, after the step of mounting the silicon bridge structure and before the step of forming the first redistribution layer, a first plastic encapsulation layer is formed on the surface of one side of the silicon wafer, and the first plastic encapsulation layer is thinned until the target metal column and the silicon bridge metal column are exposed. This allows the target metal column and the silicon bridge metal column to be at the same height, thereby ensuring that the subsequently formed first redistribution layer simultaneously connects the silicon bridge structure and the target metal column. In addition, the first plastic encapsulation layer can also improve the stability of the target metal column and the silicon bridge structure, reduce electromagnetic interference, and protect the target metal column and the silicon bridge structure from damage, thereby improving the reliability and yield of the chip packaging structure.

[0098] Furthermore, in some embodiments, the step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer includes:

[0099] A first pad is formed on a side of the first redistribution layer facing away from the silicon wafer; the first pad is connected to the silicon bridge metal column and the target metal column through the first redistribution layer;

[0100] A plurality of chips are flip-chip mounted on a side of the first pad facing away from the first redistribution layer; and the chip pins of the chips are connected to the first pad.

[0101] Furthermore, in some embodiments, after the step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, thinning the side of the silicon wafer facing away from the target metal pillar until the step of removing the silicon wafer and the internal metal pillar further includes:

[0102] A second plastic encapsulation layer is formed on a surface of the first redistribution layer facing away from the silicon wafer, wherein the second plastic encapsulation layer covers the plurality of chips and the first pad;

[0103] Thin the second plastic layer.

[0104] In the preparation method of the chip packaging structure provided in the present embodiment, after the step of flip-chip arranging multiple chips and before the step of thinning the silicon wafer, a second plastic packaging layer is formed on the surface of the first redistribution layer facing away from the silicon wafer, and the second plastic packaging layer is thinned. This can ensure that before the silicon wafer and the internal metal pillars are thinned and removed, the chip, the first redistribution layer, the first solder pad and other structures in the chip packaging structure are completely covered, which can reduce damage to the chip packaging structure. In addition, the second redistribution layer can also improve the stability of the chip, the first redistribution layer, the first solder pad and other structures, reduce electromagnetic interference, and protect the chip, the first redistribution layer, the first solder pad and other structures from damage, thereby improving the reliability and yield of the chip packaging structure.

[0105] Furthermore, in some embodiments, after the step of forming a second redistribution layer on the side of the target metal column facing away from the first redistribution layer, the method further includes:

[0106] A pin is formed on a side of the second redistribution layer facing away from the target metal pillar.

[0107] Furthermore, in some embodiments, the step of mounting a silicon bridge structure on the surface of a silicon wafer between a plurality of target metal pillars includes:

[0108] A silicon bridge structure is mounted on the surface of the silicon wafer between two adjacent target metal pillar groups.

[0109] Furthermore, in some embodiments, the step of removing a portion of the height of the silicon wafer so that a portion of the height of the metal pillar is exposed on the surface of the remaining silicon wafer includes:

[0110] A wet etching process or a dry etching process is used to remove a portion of the height of the silicon wafer, so that a portion of the height of the metal column is exposed on the remaining silicon wafer surface.

[0111] Further, in some embodiments, the conductive material is copper; the metal pillar is a copper pillar;

[0112] The chips are HBM chips and SOC chips;

[0113] The material of the first plastic sealing layer is epoxy resin;

[0114] The material of the second plastic sealing layer is epoxy resin.

[0115] In specific implementation, the chip may be an HBM1 chip, an HBM2 chip, and a SOC chip, and the quantity of each chip may be set according to actual needs.

[0116] Example 2

[0117] refer to Figure 3 This embodiment provides a specific process of a method for preparing a chip packaging structure, including steps S201-S213:

[0118] S201, provide a silicon wafer 100.

[0119] S202 , forming a plurality of holes on a surface of one side of the silicon wafer 100 , wherein the holes extend into the interior of the silicon wafer 100 .

[0120] S203, filling the holes with copper to form a plurality of copper pillars 10, such as Figure 4 As shown, the ratio of the height to the diameter of the copper pillar 10 is greater than or equal to 10:1.

[0121] S204, removing a portion of the height of the silicon wafer 100 from one side of the hole opening position, so that a portion of the height of the copper pillar 10 is exposed on the surface of the remaining silicon wafer 100; the exposed portion is used as the target copper pillar 11, and the unexposed portion is used as the internal copper pillar 12, such as Figure 5 As shown, the target copper pillar 11 includes two target copper pillar groups; the ratio of the height to the diameter of the target copper pillar 11 is greater than or equal to 9:1.

[0122] S205, a silicon bridge structure 20 is mounted on the surface of the silicon wafer 100 between the two target copper pillar groups. The silicon bridge structure 20 includes a silicon bridge body 21 and a silicon bridge copper pillar 22. The silicon bridge body 21 is located on the surface of the silicon wafer 100, and the silicon bridge copper pillar 22 is located on the side of the silicon bridge structure 20 facing away from the silicon wafer 100. Figure 6 shown.

[0123] S206, forming a first plastic encapsulation layer 30 on one side surface of the silicon wafer 100, wherein the first plastic encapsulation layer 30 covers the target copper pillar 11 and the silicon bridge structure 20. Figure 7 As shown;

[0124] S207, thinning the first plastic encapsulation layer 30 until the target copper pillar 11 and the silicon bridge copper pillar 22 are exposed. Figure 8 As shown;

[0125] S208, forming a first redistribution layer 40 on the side of the first plastic encapsulation layer 30 facing away from the silicon wafer 100; the first redistribution layer 40 connects the silicon bridge copper pillar 22 and the target copper pillar 11, such as Fig. 9 As shown;

[0126] S209, forming a first pad 50 on the side of the first redistribution layer 40 facing away from the silicon wafer 100; the first pad 50 connects the silicon bridge copper pillar 22 and the target copper pillar 11 through the first redistribution layer 40, such as Fig.10 As shown;

[0127] S210, HBM1 chip 61, SOC chip 62, SOC chip 63 and HBM2 chip 63 are flip-chip mounted in sequence on the side of the first pad 50 facing away from the first redistribution layer 40; the chip pins of the chips are connected to the first pad 50, such as Fig.11 shown.

[0128] S211, forming a second plastic encapsulation layer 70 on a surface of the first redistribution layer 40 facing away from the silicon wafer 100, the second plastic encapsulation layer 70 covering the plurality of chips 60 and the first pad 50; thinning the second plastic encapsulation layer 70, such as Fig.12 shown.

[0129] S212, thinning the side of the silicon wafer 100 facing away from the target copper pillar 11 until the silicon wafer 100 and the internal copper pillar 12 are removed. Fig.13 As shown;

[0130] S213, forming a second redistribution layer 80 and a pin 90 in sequence on the side of the target copper pillar 11 facing away from the first redistribution layer 40; the pin 90 connects the silicon bridge structure 20 and the target copper pillar 11 through the second redistribution layer 80, such as Fig.14 shown.

[0131] The preparation method of the chip packaging structure provided by the present invention, firstly, by forming a copper column by punching holes inside the silicon wafer and filling the conductive material, a copper column with a high ratio of height to diameter and a high density can be formed, so that the high-density interconnection between the chip and the copper column can be realized, the integration of the chip packaging structure can be improved, and the volume of the chip packaging structure can be reduced; secondly, after removing the silicon wafer of part of the height, due to the internal copper column inside the silicon wafer, the stability of the target copper column is increased, and the target copper column can be guaranteed not to fall off or shift in the subsequent steps, and the chip packaging yield can be improved; finally, the silicon wafer and the internal copper column are removed while thinning the back of the chip packaging structure, the process flow is simplified, and the problem of damage to the packaging structure and increased warping caused by the debonding process of the glass carrier is avoided. Therefore, the preparation method of the chip packaging structure provided by the present invention can prepare copper columns and target copper columns with a high ratio of height to diameter, a high density and a high stability, so that the high-density interconnection between the chip and the target copper column can be realized, the chip packaging yield and the integration of the chip packaging structure can be improved, and the volume of the chip packaging structure can be reduced, and the process flow can be simplified, the damage to the chip packaging structure can be reduced, and the warping of the chip packaging structure can be reduced.

[0132] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for preparing a chip packaging structure, characterized in that: The following steps are involved: Provide silicon wafers; Forming a plurality of holes on a surface of one side of the silicon wafer, wherein the holes extend into the interior of the silicon wafer; Filling the holes with a conductive material to form a plurality of metal pillars; Removing a portion of the height of the silicon wafer so that a portion of the height of the metal column is exposed on the remaining surface of the silicon wafer; the exposed portion is used as the target metal column, and the unexposed portion is used as the internal metal column; Mounting a silicon bridge structure on the surface of the silicon wafer between a plurality of the target metal pillars; forming a first redistribution layer on a side of the silicon bridge structure facing away from the silicon wafer and a side of the target metal column facing away from the silicon wafer; The first redistribution layer connects the silicon bridge structure and the target metal pillar; A plurality of chips are flip-chip mounted on a side of the first redistribution layer facing away from the silicon wafer.

2. The method for preparing a chip packaging structure according to claim 1, characterized in that: The ratio of the height to the diameter of the metal column is greater than or equal to 10:1; The target metal pillars include a plurality of target metal pillar groups; the distance between adjacent target metal pillars in each target metal pillar group is less than 40 μm.

3. The method for preparing a chip packaging structure according to claim 1, characterized in that: The step of removing a portion of the height of the silicon wafer so that a portion of the height of the metal pillar is exposed on the remaining surface of the silicon wafer includes: Removing a portion of the height of the silicon wafer from one side of the opening position of the hole, so that a portion of the height of the metal column is exposed on the remaining surface of the silicon wafer; After the step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, the method further includes: Thinning a side of the silicon wafer facing away from the target metal pillar until the silicon wafer and the internal metal pillar are removed; A second redistribution layer is formed on a side of the target metal column facing away from the first redistribution layer; the second redistribution layer connects the silicon bridge structure and the target metal column.

4. The method for preparing a chip packaging structure according to claim 3, characterized in that: The silicon bridge structure includes a silicon bridge body and a silicon bridge metal column; In the step of mounting a silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, the silicon bridge body is located on the surface of the silicon wafer, and the silicon bridge metal pillar is located on a side of the silicon bridge structure facing away from the silicon wafer; The step of forming a first redistribution layer on a side of the silicon bridge structure facing away from the silicon wafer and a side of the target metal column facing away from the silicon wafer comprises: forming the first redistribution layer on a side of the silicon bridge metal column facing away from the silicon wafer and a side of the target metal column facing away from the silicon wafer; The first redistribution layer connects the silicon bridge metal pillar and the target metal pillar.

5. The method for preparing a chip packaging structure according to claim 4, characterized in that: The step of thinning the side of the silicon wafer facing away from the target metal pillar until the silicon wafer and the internal metal pillar are removed further includes: Part of the target metal pillar and part of the silicon bridge body are thinned.

6. The method for preparing a chip packaging structure according to claim 4, characterized in that: After the step of mounting a silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars and before the step of forming a first redistribution layer on the side of the silicon bridge structure facing away from the silicon wafer and the side of the target metal pillar facing away from the silicon wafer, the method further includes: forming a first plastic encapsulation layer on a surface of one side of the silicon wafer, wherein the first plastic encapsulation layer covers the target metal column and the silicon bridge structure; Thinning the first plastic encapsulation layer until the target metal column and the silicon bridge metal column are exposed; The first redistribution layer is formed on a side of the first plastic packaging layer facing away from the silicon wafer.

7. The method for preparing a chip packaging structure according to claim 6, characterized in that: The step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer comprises: A first pad is formed on a side of the first redistribution layer facing away from the silicon wafer; the first pad is connected to the silicon bridge metal column and the target metal column through the first redistribution layer; A plurality of the chips are flip-chip mounted on a side of the first pad facing away from the first redistribution layer; and chip pins of the chips are connected to the first pad.

8. The method for preparing a chip packaging structure according to claim 7, characterized in that: After the step of flip-chipping a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, and before the step of thinning the side of the silicon wafer facing away from the target metal pillar, until the step of removing the silicon wafer and the internal metal pillar, the method further includes: Forming a second plastic encapsulation layer on a surface of the first redistribution layer facing away from the silicon wafer, wherein the second plastic encapsulation layer covers the plurality of chips and the first pad; The second plastic sealing layer is thinned.

9. The method for preparing a chip packaging structure according to claim 2, characterized in that: The step of mounting a silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars comprises: A silicon bridge structure is mounted on the surface of the silicon wafer between two adjacent target metal column groups.

10. The method for preparing a chip packaging structure according to claim 1, characterized in that: The step of removing a portion of the height of the silicon wafer so that a portion of the height of the metal pillar is exposed on the remaining surface of the silicon wafer includes: A wet etching process or a dry etching process is used to remove a portion of the height of the silicon wafer, so that a portion of the height of the metal column is exposed to the remaining surface of the silicon wafer.

11. The method for preparing a chip packaging structure according to claim 6, characterized in that: The conductive material is copper; the metal column is a copper column; The chips are HBM chips and SOC chips; The material of the first plastic sealing layer is epoxy resin.

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