Packaging heat dissipation structure for large-size high-power artificial intelligence chip

Abstract

The invention discloses a packaging heat dissipation structure for a large-size high-power artificial intelligence chip, and belongs to the technical field of chip heat dissipation. The wafer-level packaging completed multi-chip structure is located on one side of the substrate, the wafer-level packaging completed multi-chip structure comprises a plurality of chips and cofferdams, each chip comprises a functional surface and a back surface which are oppositely arranged, the cofferdams are arranged on the peripheries of the chips in a surrounding mode, and the surfaces, close to the sides of the back surfaces of the chips, of the cofferdams are flush with the back surfaces of the chips; the metal heat dissipation cover is arranged on one side of the substrate in a covering mode, the metal heat dissipation cover and the substrate define a containing cavity used for containing the wafer-level packaging multi-chip structure, and the metal heat dissipation cover is fixedly connected with the cofferdam located on the outermost periphery through adhesive; the chips, the cofferdams between the adjacent chips, the metal heat dissipation cover and the adhesive jointly define a liquid metal heat dissipation channel, the liquid metal heat dissipation channel is filled with liquid metal, the tail end of the liquid metal heat dissipation channel is closed, and the packaging heat dissipation structure has high heat dissipation capacity.

Description

Technical Field

[0001] The present invention relates to the field of chip heat dissipation technology, and more specifically to a packaging heat dissipation structure for large-size and high-power artificial intelligence chips. Background Art

[0002] With the rapid development of semiconductor integrated circuit technology, electronic devices are moving towards miniaturization and high power density. The power density of chips continues to increase, which causes a sharp increase in heat per unit area. The overall structure needs to dissipate heat in time, otherwise the chip will fail in a high temperature environment, and may even cause damage to a single device, ultimately affecting the performance of the entire system or even causing system failure.

[0003] A Chinese patent application with publication number CN118398574A discloses a double-sided heat dissipation chip packaging structure, which transfers the heat of the chip through the substrate to the ambient space through a thermal conductive adhesive layer. However, with the rapid development of artificial intelligence, the demand for high-computing power chips is gradually increasing, and the requirements for the heat dissipation capacity of the chip are also increasing. The traditional thermal conductive adhesive layer is far from meeting its needs, so the existing technology has shortcomings. Summary of the invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a packaging and heat dissipation structure for large-size and high-power artificial intelligence chips with high heat dissipation capacity.

[0005] To achieve the above object, the present invention provides the following technical solutions: The present invention provides a packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip, wherein the packaging and heat dissipation structure of the chip comprises: substrate; A wafer-level packaged multi-chip structure is completed, located on one side of the substrate, the wafer-level packaged multi-chip structure includes a plurality of chips and a cofferdam, the chip includes a functional surface and a back surface that are relatively arranged, the cofferdam is arranged around the periphery of the chip, and the surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip; A metal heat dissipation cover is disposed on one side of the substrate and forms a housing cavity with the substrate for accommodating the completed wafer-level packaged multi-chip structure. The metal heat dissipation cover is fixedly connected to the outermost cofferdam by adhesive; The chips, the dams between adjacent chips, the metal heat dissipation cover and the adhesive together form a liquid metal heat dissipation channel. Both ends of the liquid metal heat dissipation channel extend away from the chip and penetrate the metal heat dissipation cover. The liquid metal heat dissipation channel is filled with liquid metal and the ends are closed.

[0006] As a further improvement of the present invention, the liquid metal heat dissipation channel includes a first channel directly in contact with the back side of the chip and a second channel extending in a direction perpendicular to the chip surface and penetrating the metal heat dissipation cover.

[0007] As a further improvement of the present invention, the thickness of the first channel along a direction perpendicular to the chip surface is the same as the thickness of the adhesive.

[0008] As a further improvement of the present invention, the thickness of the first channel along the direction perpendicular to the chip surface is 0.1mm-1mm, the thickness of the second channel along the direction parallel to the chip surface is 0.5mm-1.5mm, and the length of the second channel along the direction perpendicular to the chip surface is 2mm-9mm.

[0009] As a further improvement of the present invention, the orthographic projection of the liquid metal heat dissipation channel on the chip covers the chip and the cofferdam between adjacent chips.

[0010] As a further improvement of the present invention, the material of the cofferdam is a plastic packaging material.

[0011] As a further improvement of the present invention, the interior of the metal heat dissipation cover also has a liquid cooling channel, and the liquid cooling channel is arranged close to the back side of the chip and is located in the space surrounded by the liquid metal heat dissipation channel.

[0012] As a further improvement of the present invention, the completed wafer-level packaged multi-chip structure further includes a rewiring layer, and the rewiring layer is fixed to one side of the functional surface of the chip; The completed wafer-level packaged multi-chip structure further includes micro-bumps, wherein the micro-bumps are located between the chip and the rewiring layer; The completed wafer-level packaged multi-chip structure further includes an adapter plate, the adapter plate is fixed to a side of the rewiring layer away from the chip and the cofferdam, and the adapter plate has a vertical interconnection structure; The completed wafer-level packaged multi-chip structure further includes a welding portion, one end of which is fixed to a side of the adapter plate away from the chip and the cofferdam, and the welding portion is electrically connected to the rewiring layer through a vertical interconnection structure of the adapter plate, and the other end of the welding portion is fixed to a side of the substrate; The welding part is a nickel-palladium-gold pad, a nickel-gold pad, a titanium-copper pad or a BGA solder ball; The periphery of the welding portion is filled with an underfill.

[0013] As a further improvement of the present invention, the substrate is a printed circuit board, a glass substrate, a silicon substrate or a ceramic substrate.

[0014] The present invention provides a method for manufacturing a packaging heat dissipation structure for a large-size and high-power artificial intelligence chip, which is applied to the manufacturing of the packaging heat dissipation structure for the large-size and high-power artificial intelligence chip, and comprises the following steps: A completed wafer-level packaged multi-chip structure is provided, wherein the completed wafer-level packaged multi-chip structure comprises a plurality of chips and a cofferdam, wherein the chip comprises a functional surface and a back surface that are arranged opposite to each other, the cofferdam is arranged around the periphery of the chip, and the surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip; Flipping the completed wafer-level packaged multi-chip structure onto one side of a substrate; A metal heat dissipation cover is arranged on one side of the substrate, and together with the substrate, forms a housing cavity for accommodating the completed wafer-level packaged multi-chip structure. The metal heat dissipation cover is fixedly connected to the cofferdam located at the outermost portion by adhesive to obtain a packaged heat dissipation structure of the chip; wherein the plurality of chips, the cofferdams between adjacent chips, the metal heat dissipation cover and the adhesive together form a liquid metal heat dissipation channel, both ends of the liquid metal heat dissipation channel extend in a direction away from the chip and penetrate the metal heat dissipation cover, and the liquid metal heat dissipation channel is filled with liquid metal and the ends are closed.

[0015] The manufacturing method of the chip packaging heat dissipation structure of the technical solution of the present invention is simple in process. In the manufactured chip packaging heat dissipation structure, the liquid metal is in direct contact with the back of the chip, and has strong thermal conductivity for the heat generated when the chip is working; the two ends of the liquid metal heat dissipation channel extend away from the chip and pass through the metal heat dissipation cover, which is conducive to increasing the heat dissipation area; the end of the liquid metal heat dissipation channel is closed, which can prevent the flow of liquid metal from affecting the heat dissipation effect. The above-mentioned whole can improve the heat dissipation capacity, and is particularly suitable for the packaging heat dissipation of large-size and high-power artificial intelligence chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a chip packaging heat dissipation structure according to an embodiment of the present invention; Figure 2 for Figure 1 A partial enlarged schematic diagram of the dotted box; Figure 3 A flowchart of a method for manufacturing a chip packaging heat dissipation structure according to an embodiment of the present invention; Figure 4 It is a schematic diagram of a wafer in which a chip and an adapter board are assembled in a method for manufacturing a chip packaging heat dissipation structure according to an embodiment of the present invention; Figure 5 It is a schematic diagram of a wafer after being cut in a method for manufacturing a chip packaging heat dissipation structure according to an embodiment of the present invention; Figure 6It is a schematic diagram of flip-chip bonding of a substrate and filling of an underfill material in a method for manufacturing a chip packaging heat dissipation structure according to an embodiment of the present invention.

[0017] : 100, chip package heat dissipation structure; 110, substrate; 120, completed wafer-level package multi-chip structure; 121, chip; 1211, functional surface; 1212, back side; 122, cofferdam; 123, redistribution layer; 124, micro-bump; 125, adapter plate; 1251, vertical interconnection structure; 1252, vertical end; 1253, horizontal end; 126, welding part; 127, bottom filler; 130, metal heat dissipation cover; 131, liquid metal heat dissipation channel; 132, liquid metal; 133, first channel; 134, second channel; 135, liquid cooling channel; 136, input and output valves; 140, adhesive. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The same parts are represented by the same reference numerals. It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the accompanying drawings, and the words "bottom surface" and "top surface", "inner" and "outer" refer to directions toward or away from the geometric center of a specific component, respectively.

[0019] The term "and / or" in the following text is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0020] like Figure 1 and Figure 2 As shown, a chip package heat dissipation structure 100 according to an embodiment of the present invention includes a substrate 110 , a completed wafer-level packaged multi-chip structure 120 , and a metal heat dissipation cover 130 .

[0021] In this embodiment, the wafer-level packaged multi-chip structure 120 is located on one side of the substrate 110, and the wafer-level packaged multi-chip structure 120 includes a plurality of chips 121 and a cofferdam 122. The chip 121 includes a functional surface 1211 and a back surface 1212 that are relatively arranged. The cofferdam 122 is arranged around the periphery of the chip 121, and the surface of the cofferdam 122 close to the back surface 1212 of the chip 121 is flush with the back surface 1212 of the chip 121. Among them, there are functional areas and pads on the functional surface 1211 of the chip 121. Among them, "several" refers to an indefinite amount, which can be one, two or more than two. When the number of chips 121 is two or more, a cofferdam 122 is arranged around the periphery of each chip 121. Among them, the cofferdam 122 is located in the fan-out area in the wafer-level assembly process from chip 121 to adapter board 125, and is usually present between the edge of the chip and the chip in the multi-chip to adapter board 125 package.

[0022] In this embodiment, the metal heat dissipation cover 130 is covered on one side of the substrate 110, and together with the substrate 110, forms a receiving cavity for receiving the completed wafer-level packaged multi-chip structure 120. The metal heat dissipation cover 130 is fixedly connected to the outermost cofferdam 122 by adhesive 140. The metal heat dissipation cover 130 and one side of the substrate 110 can be connected in any manner, such as by gluing.

[0023] In this embodiment, a plurality of chips 121, a cofferdam 122 between adjacent chips 121, a metal heat dissipation cover 130 and an adhesive 140 together form a liquid metal heat dissipation channel 131. Both ends of the liquid metal heat dissipation channel 131 extend away from the chip 121 and penetrate the metal heat dissipation cover 130. The liquid metal heat dissipation channel 131 is filled with liquid metal 132 and the ends are closed. The liquid metal 132 is used to dissipate heat from the chip 121. In the chip package heat dissipation structure 100 of the present invention, the metal heat dissipation cover 130 can dissipate heat from a plurality of chips 121 at the same time.

[0024] Among them, the liquid metal 132 is a low melting point alloy that is liquid at room temperature, or a solid sheet alloy that is liquid when heated to the melting point. The composition is, for example, a gallium-based composite metal material or other composite metal materials, such as gallium-indium-tin alloy, indium-bismuth-tin alloy or indium-bismuth-zinc alloy, etc. It has stable properties and excellent thermal conductivity (the heat transfer coefficient can reach 20W / m•K to 75W / m•K). The liquid metal 132 can be filled into the above-mentioned liquid metal heat dissipation channel 131 by extrusion. When the chip 121 is working, the liquid metal 132 is in liquid state, which is conducive to achieving better thermal conductivity.

[0025] In this embodiment, the liquid metal 132 is located inside the metal heat dissipation cover 130, and the injection port of the liquid metal 132 is finally closed, which can prevent the liquid metal 132 from overflowing, and can maintain the effective filling of the liquid metal 132 under long-term operation, thereby achieving long-term reliability of the overall packaging structure.

[0026] The overall structure of the chip package heat dissipation structure 100 of this embodiment is relatively simple. The liquid metal 132 is in direct contact with the back surface 1212 of the chip 121, and has a strong thermal conductivity for the heat generated by the chip 121 when it is working; the two ends of the liquid metal heat dissipation channel 131 extend away from the chip 121 and penetrate the metal heat dissipation cover 130, which is conducive to increasing the heat dissipation area; the end of the liquid metal heat dissipation channel 131 is closed, which can prevent the flow of liquid metal 132 from affecting the heat dissipation effect. The above overall structure can improve the heat dissipation capacity, especially suitable for the packaging heat dissipation of large-size and high-power artificial intelligence chips.

[0027] On the basis of the above-mentioned embodiment, the liquid metal heat dissipation channel 131 includes a first channel 133 directly in contact with the back surface 1212 of the chip 121 and a second channel 134 extending in a direction perpendicular to the surface of the chip 121 and penetrating the metal heat dissipation cover 130. The heat generated by the chip 121 during operation is conducted to the liquid metal 132 in the first transverse channel 133, and then the heat is conducted to the liquid metal 132 in the second longitudinal channel 134.

[0028] Based on the above-mentioned embodiment, the thickness of the first channel 133 along the direction perpendicular to the surface of the chip 121 is the same as the thickness of the adhesive 140. Figure 1 shown.

[0029] Based on the above embodiment, the thickness of the first channel 133 along the direction perpendicular to the surface of the chip 121 is 0.1mm-1mm, the thickness of the second channel 134 along the direction parallel to the surface of the chip 121 is 0.5mm-1.5mm, and the length of the second channel 134 along the direction perpendicular to the surface of the chip 121 is 2mm-9mm. Further, the thickness of the first channel 133 along the direction perpendicular to the surface of the chip 121 may be but is not limited to 0.1mm, 0.2mm, 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm or 1mm; the thickness of the second channel 134 along the direction parallel to the surface of the chip 121 may be but is not limited to 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm or 1.5mm; the length of the second channel 134 along the direction perpendicular to the surface of the chip 121 may be but is not limited to 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 7.7mm, 8mm or 9mm, with 7.7mm being preferred.

[0030] Based on the above embodiment, the orthographic projection of the liquid metal heat dissipation channel 131 on the chip 121 covers the chip 121 and the cofferdam 122 between the adjacent chip 121. In this way, the back side 1212 of the chip 121 is provided with liquid metal 132, which can fully dissipate the heat of the chip 121.

[0031] Based on the above-mentioned embodiment, the material of the cofferdam 122 is a plastic packaging material. For example, the cofferdam 122 can be epoxy molding compound (EMC), specifically, a plastic packaging material used for epoxy wafer-level packaging.

[0032] On the basis of the above-mentioned embodiment, the metal heat dissipation cover 130 further has a liquid cooling channel 135 inside, which is arranged near the back side 1212 of the chip 121 and is located in the space surrounded by the liquid metal heat dissipation channel 131. Figure 1 The cooling liquid is filled or discharged into the liquid cooling channel 135 in the direction of the middle arrow to exchange heat with the liquid metal 132 of the liquid metal heat dissipation channel 131, thereby taking away the heat generated by the chip 121 and improving the heat dissipation performance. The cooling liquid can be water or a high molecular organic liquid.

[0033] On the basis of the aforementioned embodiment, the wafer-level package multi-chip structure 120 further includes a redistribution layer 123 (RDL), which is fixed to one side of the functional surface 1211 of the chip 121. Specifically, the redistribution layer 123 is fixed to a pad on the functional surface 1211 of the chip 121. The redistribution layer 123 is a metal layer added to the chip 121 to redistribute electrical connections.

[0034] On the basis of the above-mentioned embodiments, the wafer-level packaged multi-chip structure 120 further includes micro-bumps 124, and the micro-bumps 124 are located between the chip 121 and the redistribution layer 123. It should be noted that the micro-bumps 124 may not be provided in other embodiments.

[0035] On the basis of the above-mentioned embodiments, the wafer-level packaged multi-chip structure 120 further includes an adapter plate 125, which is fixed to the side of the rewiring layer 123 away from the chip 121 and the cofferdam 122, and has a vertical interconnection structure 1251. The vertical interconnection structure 1251 of the adapter plate 125 includes an interconnected vertical end 1252 and a horizontal end 1253, the vertical end 1252 runs through the body of the adapter plate 125 and is connected to the rewiring layer 123, and the horizontal end 1253 is located on the side of the body of the adapter plate 125 away from the rewiring layer 123.

[0036] Specifically, the adapter plate 125 is provided with a through hole for one end of the vertical interconnection structure 1251 to pass through, specifically for the vertical end 1252 of the vertical interconnection structure 1251 to pass through. Further, the adapter plate 125 can be a silicon adapter plate or a glass adapter plate. When the adapter plate 125 is a silicon adapter plate, it has a through silicon via structure (TSV); when the adapter plate 125 is a glass adapter plate, it has a through glass via structure (TGV).

[0037] On the basis of the above-mentioned embodiment, the wafer-level package multi-chip structure 120 further includes a welding portion 126. One end of the welding portion 126 is fixed to a side of the adapter plate 125 away from the chip 121 and the cofferdam 122, and the welding portion 126 is electrically connected to the rewiring layer 123 through the vertical interconnection structure 1251 of the adapter plate 125. Specifically, the welding portion 126 is electrically connected to the horizontal end 1253 of the vertical interconnection structure 1251 to achieve electrical connection with the rewiring layer 123. The other end of the welding portion 126 is fixed to one side of the substrate 110.

[0038] On the basis of the above-mentioned embodiment, the soldering portion 126 is a nickel-palladium-gold soldering pad, a nickel-gold soldering pad, a titanium-copper soldering pad or a BGA (Ball Grid Array) solder ball.

[0039] On the basis of the above-mentioned embodiment, the periphery of the welding part 126 is filled with an underfill 127. The underfill 127 may be an organic material, which supports the welding part 126 and prevents expansion and contraction.

[0040] Based on the above embodiments, the substrate 110 is a printed circuit board, a glass substrate, a silicon substrate or a ceramic substrate. Of course, the substrate 110 is not limited thereto, and can also be any substrate that can be used in the art.

[0041] In the chip packaging heat dissipation structure using the technical solution of the present invention, the liquid metal is in direct contact with the back of the chip, and has a strong thermal conductivity for the heat generated when the chip is working; the two ends of the liquid metal heat dissipation channel extend away from the chip and penetrate the metal heat dissipation cover, which is conducive to increasing the heat dissipation area; the end of the liquid metal heat dissipation channel is closed, which can prevent the liquid metal flow from affecting the heat dissipation effect. The above overall can improve the heat dissipation capacity, especially suitable for the packaging heat dissipation of large-size and high-power artificial intelligence chips.

[0042] like Figure 3 The method for manufacturing a chip packaging heat dissipation structure according to an embodiment of the present invention comprises the following steps: S10. Provide a completed wafer-level packaged multi-chip structure, wherein the completed wafer-level packaged multi-chip structure includes a plurality of chips and a cofferdam, wherein the chip includes a functional surface and a back surface that are relatively arranged, and the cofferdam is arranged around the periphery of the chip, and the surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip.

[0043] Specifically in this implementation method, please combine Figure 1 and Figure 4-Figure 6 The manufacturing method of the chip packaging heat dissipation structure 100 of the above embodiment comprises the following steps: According to the CoWoS (Chip on Wafer on Substrate, wafer-level packaging) process flow, after the CoW process is completed, Figure 4 The wafer shown is assembled by components such as chips 121 and transfer plates 125, and the wafer includes a plurality of completed wafer-level packaged multi-chip structures 120. The completed wafer-level packaged multi-chip structure 120 includes a plurality of chips 121, a cofferdam 122, a redistribution layer 123, micro-bumps 124, a transfer plate 125 with a vertical interconnection structure 1251, and a soldering portion 126. Among them, the cofferdam 122 is arranged around the periphery of the chip 121, and the surface of the cofferdam 122 close to the back side 1212 of the chip 121 is flush with the back side 1212 of the chip 121; the rewiring layer 123 is fixed on the side of the functional surface 1211 of the chip 121; the micro-bumps 124 are located between the chip 121 and the rewiring layer 123; the adapter board 125 is fixed on the side of the rewiring layer 123 away from the chip 121 and the cofferdam 122; the welding part 126 is fixed on the side of the adapter board 125 away from the chip 121 and the cofferdam 122, and the welding part 126 is electrically connected to the rewiring layer 123 through the vertical interconnection structure 1251 of the adapter board 125.

[0044] Place the above assembled wafer along Figure 4 Cut along the dotted line to get Figure 5 The two completed wafer level package multi-chip structures 120 are shown as follows. Figure 5 As shown, the completed wafer-level package multi-chip structure 120 includes a chip 121, a dam 122, a rewiring layer 123, micro-bumps 124, an adapter plate 125 with a vertical interconnect structure 1251, and a welding portion 126. It should be noted that Figure 4 and Figure 5 This is only a partial illustration, and the present invention does not limit the number of components such as chips 121, cofferdams 122, redistribution layers 123, micro-bumps 124, adapter plates 125 with vertical interconnect structures 1251, and soldering parts 126 in the wafer-level package multi-chip structure 120.

[0045] S20, flipping the completed wafer-level packaged multi-chip structure onto one side of the substrate.

[0046] Specifically, the substrate 110 is flip-chip soldered and filled with the bottom filler 127 to obtain Figure 6 The structure shown.

[0047] S30. A metal heat dissipation cover is disposed on one side of the substrate, and together with the substrate, forms a housing cavity for accommodating a multi-chip structure of wafer-level packaging. The metal heat dissipation cover is fixedly connected to the outermost cofferdam by adhesive to obtain a chip packaging heat dissipation structure; wherein, a plurality of chips, cofferdams between adjacent chips, the metal heat dissipation cover and the adhesive together form a liquid metal heat dissipation channel, and both ends of the liquid metal heat dissipation channel extend away from the chip and pass through the metal heat dissipation cover, and the liquid metal heat dissipation channel is filled with liquid metal and the ends are closed.

[0048] Specifically, the metal heat dissipation cover 130 is covered on one side of the substrate 110, and can be fixedly connected by gluing. At the same time, the metal heat dissipation cover 130 and the substrate 110 form a receiving cavity for accommodating the wafer-level packaged multi-chip structure 120. The metal heat dissipation cover 130 is fixedly connected to the outermost cofferdam 122 by gluing glue 140. Figure 1 The chip package heat dissipation structure 100 shown in the figure includes a plurality of chips 121, a cofferdam 122 between adjacent chips 121, a metal heat dissipation cover 130 and an adhesive 140, which together form a liquid metal heat dissipation channel 131. Both ends of the liquid metal heat dissipation channel 131 extend away from the chip 121 and penetrate the metal heat dissipation cover 130. The liquid metal heat dissipation channel 131 is filled with liquid metal 132 and the ends are closed.

[0049] The manufacturing method of the chip packaging heat dissipation structure of the technical solution of the present invention is simple in process. In the manufactured chip packaging structure, the liquid metal is in direct contact with the back of the chip, and has strong thermal conductivity for the heat generated when the chip is working; the two ends of the liquid metal heat dissipation channel extend away from the chip and penetrate the metal heat dissipation cover, which is conducive to increasing the heat dissipation area; the end of the liquid metal heat dissipation channel is closed, which can prevent the flow of liquid metal from affecting the heat dissipation effect. The above-mentioned overall structure can improve the heat dissipation capacity, and is particularly suitable for the packaging and heat dissipation of large-size and high-power artificial intelligence chips.

[0050] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A packaging and heat dissipation structure for large-size and high-power artificial intelligence chips, characterized in that: The chip packaging and heat dissipation structure comprises: substrate; A wafer-level packaged multi-chip structure is completed, located on one side of the substrate, the wafer-level packaged multi-chip structure includes a plurality of chips and a cofferdam, the chip includes a functional surface and a back surface that are relatively arranged, the cofferdam is arranged around the periphery of the chip, and the surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip; A metal heat dissipation cover is disposed on one side of the substrate and forms a housing cavity with the substrate for accommodating the completed wafer-level packaged multi-chip structure. The metal heat dissipation cover is fixedly connected to the outermost cofferdam by adhesive; The chips, the dams between adjacent chips, the metal heat dissipation cover and the adhesive together form a liquid metal heat dissipation channel. Both ends of the liquid metal heat dissipation channel extend away from the chip and penetrate the metal heat dissipation cover. The liquid metal heat dissipation channel is filled with liquid metal and the ends are closed.

2. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 1 is characterized in that: The liquid metal heat dissipation channel includes a first channel directly in contact with the back side of the chip and a second channel extending in a direction perpendicular to the surface of the chip and penetrating the metal heat dissipation cover.

3. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 2 is characterized in that: The thickness of the first channel along a direction perpendicular to the chip surface is the same as the thickness of the adhesive.

4. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 2 or 3, characterized in that: The thickness of the first channel along a direction perpendicular to the chip surface is 0.1 mm-1 mm, the thickness of the second channel along a direction parallel to the chip surface is 0.5 mm-1.5 mm, and the length of the second channel along a direction perpendicular to the chip surface is 2 mm-9 mm.

5. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 1 is characterized in that: The orthographic projection of the liquid metal heat dissipation channel on the chip covers the chip and the cofferdam between the adjacent chips.

6. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 1 is characterized in that: The material of the cofferdam is plastic packaging material.

7. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 1 is characterized in that: The metal heat dissipation cover also has a liquid cooling channel inside. The liquid cooling channel is arranged close to the back side of the chip and is located in the space surrounded by the liquid metal heat dissipation channel.

8. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 1 is characterized in that: The completed wafer-level packaged multi-chip structure further includes a rewiring layer, and the rewiring layer is fixed to one side of the functional surface of the chip; The completed wafer-level packaged multi-chip structure further includes micro-bumps, wherein the micro-bumps are located between the chip and the rewiring layer; The completed wafer-level packaged multi-chip structure further includes an adapter plate, the adapter plate is fixed to a side of the rewiring layer away from the chip and the cofferdam, and the adapter plate has a vertical interconnection structure; The completed wafer-level packaged multi-chip structure further includes a welding portion, one end of which is fixed to a side of the adapter plate away from the chip and the cofferdam, and the welding portion is electrically connected to the rewiring layer through a vertical interconnection structure of the adapter plate, and the other end of the welding portion is fixed to a side of the substrate; The welding part is a nickel-palladium-gold pad, a nickel-gold pad, a titanium-copper pad or a BGA solder ball; The periphery of the welding portion is filled with an underfill.

9. The packaging and heat dissipation structure for a large-size and high-power artificial intelligence chip according to claim 1, characterized in that: The substrate is a printed circuit board, a glass substrate, a silicon substrate or a ceramic substrate.

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