Manufacturing method of isolation structure of semiconductor device and semiconductor device

Abstract

The embodiment of the invention relates to a manufacturing method of an isolation structure of a semiconductor device and the semiconductor device. The manufacturing method of the isolation structure of the semiconductor device comprises the following steps: forming an epitaxial layer on a substrate; forming a buried layer between the substrate and the epitaxial layer; a first groove and a second groove are formed, the first groove extends into the buried layer from the surface of the epitaxial layer, and the second groove extends into the substrate from the surface of the epitaxial layer; first deep trench isolation is formed in the first trench, second deep trench isolation is formed in the second trench, a fourth trench is formed between the first deep trench isolation and the second deep trench isolation, the fourth trench extends from the surface of the epitaxial layer to the interior of the epitaxial layer, and a certain distance is formed between the bottom of the fourth trench and the top of the buried layer; forming a first conductive core in the fourth trench; and forming a second conductive core portion extending from the sidewall and the bottom of the trench in a direction away from the fourth trench, the second conductive core portion extending at least to the top of the buried layer in the vertical direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more specifically, to a method for manufacturing an isolation structure of a semiconductor device and a semiconductor device. Background Art

[0002] Hybrid integration technology that integrates different types of transistors into the same semiconductor substrate or semiconductor layer has been widely used in integrated circuits. For example, integrated circuits using hybrid integration technology include: complementary metal oxide semiconductor (CMOS) integrated circuits composed of N-type MOS transistors and P-type MOS transistors, power integrated circuits composed of high-voltage transistors and low-voltage transistors, and hybrid integrated circuits composed of analog circuits and digital circuits.

[0003] In CMOS integrated circuits, different analog circuit functions, such as amplifiers, filters, oscillators, etc., are realized based on complementary N-type MOS transistors and P-type MOS transistors. Basic logic gate circuits can also be realized, thereby realizing various complex digital circuit functions. Since different types of transistors are used in CMOS integrated circuits, it is necessary to form an isolation structure to define the active area of ​​each transistor so that adjacent transistors are separated from each other and work independently without current leakage between each other. In addition, a buried layer may be formed under the well region in the semiconductor layer to improve the source-substrate breakdown voltage characteristics of the semiconductor device. When the isolation structure of the semiconductor device is reasonably designed, the CMOS integrated circuit has the characteristics of low power consumption, high precision, high speed and low noise.

[0004] The isolation structure of semiconductor devices may include trench isolations of different depths. For example, shallow trench isolation (abbreviated as STI) is used to separate the N-type MOS transistor and the P-type MOS transistor of the same circuit unit, and deep trench isolation (abbreviated as DTI) is used to separate the active area of ​​the transistor from the conductive channel of the buried layer. However, deep trench isolation itself may also damage the crystal structure of the semiconductor layer, forming an additional current leakage path in the semiconductor layer, thereby increasing the power consumption and reliability degradation of the transistor, and even possible breakdown damage.

[0005] Therefore, it is desirable to provide a semiconductor device isolation structure and a method for manufacturing the same which can suppress leakage current to improve device reliability. Summary of the invention

[0006] The purpose of the present disclosure is to provide a method for manufacturing an isolation structure of a semiconductor device and a semiconductor device, which can effectively solve the problems in the prior art.

[0007] According to one aspect of the present invention, there is provided a method for manufacturing an isolation structure of a semiconductor device, comprising: forming an epitaxial layer on a substrate; forming a buried layer between the substrate and the epitaxial layer; forming a first trench and a second trench, the first trench extending from the surface of the epitaxial layer into the buried layer, and the second trench extending from the surface of the epitaxial layer into the substrate; forming a first deep trench isolation in the first trench, forming a second deep trench isolation in the second trench, and forming a fourth trench between the first deep trench isolation and the second deep trench isolation, the fourth trench extending from the surface of the epitaxial layer to the interior thereof, and a certain distance between the bottom of the fourth trench and the top of the buried layer; forming a first conductive core in the fourth trench; and forming a second conductive core extending from the sidewall and bottom of the trench in a direction away from the fourth trench, wherein in a vertical direction, the second conductive core extends at least to the top of the buried layer.

[0008] Optionally, the first conductive core is a doped conductive layer having a second doping type; the first conductive core fills the fourth trench and is in direct contact with the bottom and sidewalls of the fourth trench; through a thermal process, the dopant in the second conductive core diffuses outside the fourth trench to form a second conductive core of the second doping type in the epitaxial layer outside the fourth trench, and the second conductive core contacts the first conductive core to form a first conductive channel.

[0009] Optionally, after forming the first trench, the method further includes a step of implanting ions into the epitaxial layer on the first side of the first trench and the epitaxial layer on the second side of the fourth trench through the opening of the first trench, wherein the epitaxial layer has a first doping type and the ion implantation implants dopants having the same doping type as the epitaxial layer into the epitaxial layer.

[0010] Optionally, the dopant is implanted into the first side and the second side of the first trench by controlling the opening size of the first trench and the angle of ion implantation.

[0011] Optionally, the method further includes: forming a third trench; and forming a second conductive channel in the third trench; wherein the opening widths of the first trench, the second trench and the third trench increase sequentially.

[0012] Optionally, the first trench, the second trench and the third trench are formed simultaneously.

[0013] Optionally, after forming the first trench, the second trench and the third trench, the method further includes: forming a conformal outer insulating layer in the first trench, the second trench and the third trench, the outer insulating layer in the first trench constituting an insulating liner for isolating the first deep trench, and the outer insulating layer in the second trench constituting an insulating liner for isolating the second deep trench; forming an intermediate insulating layer in the first trench, the second trench and the third trench, the intermediate insulating layer filling the first trench and closing the opening of the first trench, the intermediate insulating layer filling the second trench and closing the opening of the second trench, and the intermediate insulating layer Conformally covering the outer insulating layer in the third trench; etching back the intermediate insulating layer to form an opening penetrating the outer insulating layer and the intermediate insulating layer at the bottom of the third trench, the outer insulating layer and the intermediate insulating layer on the sidewalls of the third trench are retained to form an insulating liner for the second conductive channel, the intermediate insulating layer in the first trench is retained to form an insulating core for the first deep trench isolation, and the intermediate insulating layer in the second trench is retained to form an insulating core for the second deep trench isolation; filling the third trench and the opening at the bottom of the third trench with a conductive layer to form a conductive core for the second conductive channel.

[0014] Optionally, during the process of forming the intermediate insulating layer, an air gap is formed inside the intermediate insulating layer in the first trench.

[0015] Optionally, during the process of forming the intermediate insulating layer, an air gap is formed inside the intermediate insulating layer in the second trench; during the process of back-etching the intermediate insulating layer, the opening of the air gap inside the intermediate insulating layer in the second trench is opened; while filling the third trench and the opening at the bottom of the third trench with a conductive layer, the interior of the intermediate insulating layer in the second trench is filled with a conductive layer to form a pseudo conductive core.

[0016] Optionally, during the process of forming the intermediate insulating layer, an air gap is formed inside the intermediate insulating layer in the second groove; during the process of back-etching the intermediate insulating layer, the opening of the air gap inside the intermediate insulating layer in the second groove is still closed, and the air gap inside the intermediate insulating layer in the second groove is retained.

[0017] According to another aspect of the present invention, a semiconductor device is provided, which adopts the above-mentioned semiconductor device and includes: a substrate; an epitaxial layer located on the substrate; a buried layer located between the substrate and the epitaxial layer; a first deep trench isolation located in a peripheral area of ​​the semiconductor device and surrounding an active area of ​​a transistor, the first deep trench isolation extending from a surface of the epitaxial layer to the buried layer; a second deep trench isolation located in a peripheral area of ​​the semiconductor device and surrounding the first deep trench isolation, the second deep trench isolation extending from a surface of the epitaxial layer to the substrate; and a first conductive channel located between the first deep trench isolation and the second deep trench isolation; wherein a trench is formed between the first deep trench isolation and the second deep trench isolation, the trench extending from a surface of the epitaxial layer to an interior thereof, and the bottom of the trench has a certain distance from a top of the buried layer; the first conductive channel includes a first conductive core located in the trench, and a second conductive core extending from a sidewall and a bottom of the trench in a direction away from the fourth trench, and in a vertical direction, the second conductive core extends at least to the top of the buried layer.

[0018] According to the semiconductor device of the embodiment of the present disclosure, in the peripheral region of the semiconductor device, the first deep trench isolation extends from the surface of the epitaxial layer into the buried layer, separating the first conductive channel located in the peripheral region from the active region of the transistor. The first deep trench isolation blocks the lateral flow path of the leakage current along the bottom of the first deep trench isolation.

[0019] The first deep trench isolation includes a first insulating core and a first insulating liner surrounding the first insulating core. At least one insulating layer in the first insulating liner is used to repair the damage to the sidewall of the trench caused by deep etching of the epitaxial layer and the buried layer to form a trench, thereby reducing the crystal defects and / or dislocation defects at the silicon / silicon oxide interface between the first deep trench isolation and the epitaxial layer and the buried layer, so as to block the vertical flow path of the leakage current along the sidewall of the first deep trench isolation. Therefore, the semiconductor device adopts the first deep trench isolation to suppress the leakage current, thereby reducing the power consumption of the semiconductor device and improving the reliability of the semiconductor device. The first insulating core serves as a filling layer for the first deep trench isolation. On the one hand, it can reduce the stress generated by the first deep trench isolation in the epitaxial layer, and on the other hand, it can reduce the parasitic capacitance introduced by the first deep trench isolation, further improving the performance of the semiconductor device.

[0020] In a preferred embodiment, the first deep trench isolation further includes an air gap provided in the first insulating core. Since the dielectric constant of air is smaller than that of the dielectric material, the air gap is used to reduce the equivalent dielectric constant of the first insulating core, thereby further reducing the parasitic capacitance of the semiconductor device introduced by the first deep trench isolation, and further improving the performance of the semiconductor device.

[0021] In a preferred embodiment, a second deep trench isolation is further provided in the peripheral region of the semiconductor device. The second deep trench isolation extends from the surface of the epitaxial layer to the substrate below the buried layer, separating the first conductive channel and the second conductive channel located in the peripheral region from each other. Not only can the breakdown voltage of the semiconductor device be improved due to the improved isolation performance of the second deep trench isolation, but also the size of the semiconductor device can be reduced because the spacing between the first conductive channel and the second conductive channel is allowed to be reduced at the same breakdown voltage.

[0022] In this embodiment, the first conductive channel includes a first conductive core and a second conductive core, the first conductive core is composed of a conductive material, such as doped polysilicon, and the second conductive core is, for example, a doped region formed in an epitaxial layer. The first conductive core is arranged in a fourth trench, and the fourth trench extends from the surface of the epitaxial layer to the inside thereof, and there is a certain distance between the bottom thereof and the top of the buried layer. The second conductive core extends from the bottom of the fourth trench toward the buried layer and at least reaches the top of the buried layer, and the first conductive core and the second conductive core contact each other and communicate to form a first conductive channel.

[0023] On a side of the first conductive channel close to the first transistor and the second transistor, a first deep trench isolation serves as an insulating isolation for diffusion of the first conductive core, preventing dopants in the first conductive core from diffusing into the active areas of the first transistor and the second transistor; on a side of the first conductive channel close to the second conductive channel, a second deep trench isolation serves as an insulating isolation for the first conductive core, preventing dopants in the first conductive core from diffusing into the second conductive channel, so as to avoid a short circuit between the first conductive channel and the second conductive channel.

[0024] In a preferred embodiment, the epitaxial layer between the first deep trench isolation and the second deep trench isolation forms an insulating isolation region, wherein the doping concentration of the upper portion of the insulating isolation region is greater than the doping concentration of the lower portion thereof. The first conductive core directly contacts the bottom and sidewalls of the fourth trench, and the dopant in the first conductive core diffuses from the sidewalls and bottom of the fourth trench toward the outside of the fourth trench, wherein the dopant diffused to the epitaxial layer is of the opposite type to the dopant in the epitaxial layer, and most or all of the dopant diffused to the upper portion of the insulating isolation region is neutralized, and after the dopant diffused to the lower portion of the insulating isolation region neutralizes the dopant in the epitaxial layer, an inverted doping region, i.e., the second conductive core, is formed.

[0025] In a preferred embodiment, the first deep trench isolation, the second deep trench isolation, and the second conductive channel are formed in the first trench, the second trench, and the third trench, respectively. In a preferred embodiment, by selecting the same opening width of the first conductive channel and the first deep trench isolation, a common trench etching process can be used to simultaneously form the first trench, the second trench, and the third trench. This can not only reduce the process steps and the number of masks for manufacturing the isolation structure, but also avoid the depth deviation of the first conductive channel and the first deep trench isolation caused by the independent etching steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other purposes, features and advantages of the embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation, in which: Figure 1a , Figure 1b and Figure 1c A schematic perspective view, a top view, and a cross-sectional view respectively illustrate a semiconductor device according to a first embodiment of the present disclosure; Figure 2 A schematic cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure; Figures 3a to 3k Schematic cross-sectional views of a method for manufacturing an isolation structure of a semiconductor device according to a fourth embodiment of the present disclosure at different stages are respectively shown. DETAILED DESCRIPTION

[0027] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0028] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0029] Furthermore, the terms "top", "bottom", "above", "below", "over", "below", etc., as used herein, are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that embodiments of the present disclosure are capable of operation in other orientations than described or illustrated herein.

[0030] In addition, the terms "shallow trench", "medium trench" and "deep trench" used in this article are used for descriptive purposes and are not necessarily used to define the absolute value of the trench depth. In the case of describing the "shallow trench", "medium trench" and "deep trench" in the same semiconductor device, they are only used to indicate the relative depth relationship between multiple trenches and other device structures of the semiconductor device, and are not necessarily used to describe the relative depth relationship between multiple trenches and other device structures of the semiconductor device. For example, when describing a "deep trench" in a semiconductor device, the trench mentioned may extend below the well region of the semiconductor device, or may further extend into the buried layer of the semiconductor device, or may further extend below the buried layer of the semiconductor device.

[0031] Embodiments of the present disclosure generally relate to semiconductor devices or integrated circuits (ICs). More specifically, some embodiments relate to semiconductor devices or CMOS integrated circuits having complementary N-type MOS transistors and P-type MOS transistors integrated on the same substrate. CMOS integrated circuits can be used for analog integrated circuits such as amplifiers, or digital integrated circuits such as logic circuits. The embodiments of the present disclosure form a plurality of trench structures of different depths while sharing existing trench process steps, and together with a buried layer (e.g., an N+ buried layer (NBL)), effectively isolate different device units in the same integrated circuit from each other.

[0032] Figure 1a , Figure 1b and Figure 1c A schematic perspective view, a top view and a cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure are respectively shown, wherein Figure 1b The top view shown uses line AA to show the interception position of the cross-sectional view. Unless otherwise specified, the interception positions of the cross-sectional views in the drawings of the present disclosure are all along line AA.

[0033] In the present disclosure, the semiconductor device 100 may be any combination of different types of active devices. For example, in a CMOS integrated circuit, it is a combination of an N-type MOS transistor and a P-type MOS transistor, and in a power integrated circuit, it is a combination of a high-voltage transistor and a low-voltage transistor. The high-voltage transistor is, for example, a lateral double diffused metal oxide semiconductor (LDMOS) transistor, and the low-voltage transistor is, for example, a conventional planar MOS transistor. In the following, the present disclosure is described in detail only by taking a CMOS integrated circuit as an example.

[0034] The semiconductor device 100 includes a substrate 101, an epitaxial layer 102, and a buried layer 103. The epitaxial layer 102 is, for example, a semiconductor layer disposed above the substrate 101. The buried layer 103 is, for example, a semiconductor layer disposed between the substrate 101 and the epitaxial layer 102.

[0035] The substrate 101 and the epitaxial layer 102 have a first doping type, respectively, and the buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In) or a combination thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. In one embodiment, the buried layer 103 may have a blanket structure having substantially the same horizontal extension as the substrate 101 and being laid flat on the substrate 101. In another embodiment, the buried layer 103 may have a patterned structure. The embodiments of the present disclosure are not strictly limited to this.

[0036] The semiconductor device 100 includes a plurality of device regions. Figure 1a , 1b The semiconductor device 100 shown in FIG. 1 c includes a core region 110 and a peripheral region 120 .

[0037] In the core region 110 of the semiconductor device 100, a well region 104 of a first transistor 111 and a well region 105 of a second transistor 112 are provided, which are doped regions in the epitaxial layer 102 respectively. The well region 104 of the first transistor 111 has a first doping type, a source region 106 and a drain region 107 of a second doping type are provided in the well region 104, and a gate stack is provided above the well region 104, the gate stack includes a gate dielectric 107 and a gate conductor 108 stacked in sequence, wherein the gate dielectric 107 is sandwiched between the gate conductor 108 and the epitaxial layer 108. For example, the gate dielectric 107 is composed of silicon oxide, and the gate conductor 108 is composed of doped polysilicon. For an N-type MOS transistor, the well region 104 of the first transistor 111 is doped to a P-type, and the source region 106 and the drain region 107 are doped to an N-type, respectively. For a P-type MOS transistor, the well region 104 of the first transistor 111 is doped to N-type, and the source region 106 and the drain region 107 are doped to P-type, respectively. The well region 104 of the first transistor 111 serves as the body region of the transistor. When a gate voltage is applied to the gate conductor 108, a channel is formed in the well region 104 of the first transistor 111, which is used to control the conductive path between the source region 106 and the drain region 107, thereby controlling the conduction state of the first transistor 111.

[0038] The first transistor 111 and the second transistor 112 are an N-type MOS transistor and a P-type MOS transistor that complement each other. The well region 105 of the second transistor 112 has a second doping type, and a source region and a drain region of a first doping type are arranged in the well region 105, and a gate stack is arranged above the well region. Since the device structure of the second transistor 112 is similar to that of the first transistor 111, the internal structure of the second transistor 112 will not be described in detail.

[0039] Furthermore, in the core region 110, a shallow trench isolation 121 is provided for isolating the first transistor 111 from the second transistor 112. In order to isolate the first transistor 111 from the second transistor 112, the shallow trench isolation 121 extends from the surface of the epitaxial layer 102 to the well region of the first transistor 111 and the second transistor 112 to a depth D5.

[0040] A first conductive via 10 and a second conductive via 20 are provided in the peripheral region 120 of the semiconductor device 100. The first conductive via 10 extends from the surface of the epitaxial layer 102 to the top of the buried layer 103 to a depth D4, and is used to provide an electrical connection path from the buried layer 103 to the surface of the epitaxial layer 102. The second conductive via 20 extends from the surface of the epitaxial layer 102 to below the buried layer 103 until the inside of the substrate 101 reaches a depth D3, and is used to provide an electrical connection path from the substrate 101 to the surface of the epitaxial layer 102.

[0041] Further, in the peripheral region 120, a plurality of shallow trench isolations 122, a first deep trench isolation 30, and a second deep trench isolation 40 are also provided around the core region 110. In order to isolate the first transistor 111 and the second transistor 112 from adjacent transistors, the shallow trench isolation 122 extends from the surface of the epitaxial layer 102 to a depth D5 substantially the same as that of the shallow trench isolation 121. In order to isolate the active regions of the first transistor 111 and the second transistor 112 from the first conductive channel 10 and the second conductive channel 20, the first deep trench isolation 30 is provided inside the first conductive channel 10 and the second conductive channel 20, that is, compared with the first conductive channel 10, the second deep trench isolation 40 and the second conductive channel 20, the first deep trench isolation 30 is closer to the well region 104 of the first transistor 111 and the well region 105 of the second transistor 112. The first deep trench isolation 30 extends from the surface of the epitaxial layer 102 to the inside of the buried layer 103 to a depth D1. In order to isolate the first conductive channel 10 and the second conductive channel 20 from each other, the second deep trench isolation 40 is disposed between the first conductive channel 10 and the second conductive channel 20. The second deep trench isolation 40 extends from the surface of the epitaxial layer 102 to the substrate 101 below the buried layer 103, reaching a depth D2. The depth D4 of the first conductive channel 10, the depth D1 of the first deep trench isolation 30, the depth D2 of the second deep trench isolation 40, and the depth D3 of the second conductive channel 20 increase in sequence.

[0042] The first conductive channel 10 is used to electrically connect the buried layer 103 to the surface of the epitaxial layer 102. In one embodiment, the first conductive channel 10 includes a first conductive core 12a and a second conductive core 12b, wherein the first conductive core 12a is composed of a conductive material, such as doped polysilicon, and the second conductive core 12b is, for example, a doped region formed in the epitaxial layer 102. Other types of conductive cores 12a are also feasible. The first conductive core 12a is arranged in the fourth groove. It is worth noting that the fourth groove extends from the surface of the epitaxial layer 102 to the inside thereof, and there is a certain distance between its bottom and the top of the buried layer 103. The second conductive core 12b extends from the sidewall and bottom of the fourth trench toward a direction away from the fourth trench, wherein in the horizontal direction, the second conductive core 12b extends from the sidewall of the fourth trench toward the first deep trench isolation 30 and the second deep trench isolation 40, respectively, and is isolated from the active area of ​​the semiconductor device via the first deep trench isolation 30, and is isolated from the second conductive channel 20 via the second deep trench isolation 40; in the vertical direction, the second conductive core 12b extends from the bottom of the fourth trench toward the buried layer 103 and at least reaches the top of the buried layer 103. The first conductive core 12a and the second conductive core 12b contact each other, and together constitute a first conductive channel 10 in contact with the buried layer 103.

[0043] Furthermore, the epitaxial layer 102 between the first deep trench isolation 30 and the second deep trench isolation 40 forms an insulating isolation region S01, and the first conductive core 12a directly contacts the bottom and side walls of the fourth trench. The dopant in the first conductive core 12a diffuses from the side walls and bottom of the fourth trench toward the outside of the fourth trench. The dopant diffused into the insulating isolation region S01 (epitaxial layer 102) is of opposite type to the dopant in the insulating isolation region S01 (epitaxial layer 102). Although part of the dopant diffused into the insulating isolation region S01 is neutralized, an inverted doping region, namely the second conductive core 12b, will eventually be formed in the insulating isolation region S01.

[0044] Further, on the side of the first conductive channel 10 close to the first transistor 111 and the second transistor 112, the first deep trench isolation 30 serves as an insulating isolation for the diffusion of the first conductive core 12a, preventing the dopant in the first conductive core 12a from diffusing into the active regions of the first transistor 111 and the second transistor 112; on the side of the first conductive channel 10 close to the second conductive channel 20, the second deep trench isolation 40 serves as an insulating isolation for the first conductive core 12a, preventing the dopant in the first conductive core 12a from diffusing into the second conductive channel 20, so as to avoid a short circuit between the first conductive channel 10 and the second conductive channel 20. In other words, the second conductive core 12b is distributed throughout the insulating isolation region S01.

[0045] With this arrangement, the first conductive channel 10 penetrates the epitaxial layer 102, wherein the first conductive core 12a and the second conductive core 12b connect the buried layer 103 to the surface of the epitaxial layer 102. Therefore, in the working state of the semiconductor device 100, the buried layer 103 is biased to any desired potential via the first conductive channel 10. On the one hand, the bias voltage of the buried layer 103 can be used to improve the source-substrate breakdown voltage characteristics of the semiconductor device, and on the other hand, the shielding effect of the buried layer 103 can be used to suppress crosstalk between adjacent semiconductor devices. In this embodiment, the power supply voltage VDD is applied to the buried layer 103 via the first conductive channel 10 to obtain the desired bias voltage and shielding effect.

[0046] The second conductive channel 20 is disposed in the third trench for electrically connecting the substrate 101 to the surface of the epitaxial layer 102. In one embodiment, the second conductive channel 20 includes an insulating liner 21 and a conductive core 22. The insulating liner 21 is composed of an oxide, such as silicon oxide, and the conductive core 22 is composed of a conductive material, such as doped polysilicon. Other types of insulating liners 21 and conductive cores 22 are also feasible. The insulating liner 21 is formed on a portion of the sidewall and the bottom of the trench, and includes an opening formed at the bottom of the trench. The conductive core 22 fills the trench and the opening, that is, extends from the surface of the epitaxial layer 102 to the bottom of the trench, and contacts the substrate 101. The insulating liner 21 of the second conductive channel 20 isolates the conductive core 22 from the epitaxial layer 102 and the buried layer 103.

[0047] With this arrangement, the second conductive path 20 penetrates the epitaxial layer 102 and the buried layer 103, and the conductive core 22 therein connects the substrate 101 to the surface of the epitaxial layer 102. Therefore, in the working state of the semiconductor device 100, the substrate 101 is biased to any desired potential via the second conductive path 20. This can connect the substrate 101 to any desired potential on the one hand, thereby suppressing noise and interference, and on the other hand, can avoid latch-up problems. In this embodiment, the substrate 101 is grounded via the second conductive path 20 to obtain the desired anti-interference effect.

[0048] In this embodiment, the first conductive core 12a of the first conductive channel 10 and the conductive core 22 of the second conductive channel 20 are both composed of doped polysilicon, and the second conductive core 12b of the first conductive channel 10 is composed of a doped region formed in the epitaxial layer 102. The first conductive core 12a and the second conductive core 12b of the first conductive channel 10 have the same doping type as the buried layer 103 and a higher doping concentration, so a low resistance path of the buried layer 103 can be formed. The conductive core 22 of the second conductive channel 20 has the same doping type as the substrate 101 in contact with it and a higher doping concentration, so a low resistance path of the substrate 101 can be formed. In other embodiments, it is also feasible for the first conductive channel 10 and the second conductive channel 20 to use other types of conductive cores, as long as the semiconductor layer in contact with them can be electrically connected to the surface of the epitaxial layer 102.

[0049] The first deep trench isolation 30 is disposed in the first trench for isolating the active areas of the first transistor 111 and the second transistor 112 from the first conductive channel 10. In one embodiment, the first deep trench isolation 30 includes an insulating liner 31 and an insulating core 32. The insulating liner 31 and the insulating core 32 are composed of oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating liner 31 and insulating core 32 are also feasible. The insulating liner 31 is formed on the sidewall and bottom of the trench. The insulating core 32 fills the trench. The insulating liner 31 and the insulating core 32 of the first deep trench isolation 30 form a composite insulating layer to improve isolation performance.

[0050] The second deep trench isolation 40 is arranged in the second trench for isolating the first conductive channel 10 and the second conductive channel 20 from each other. In one embodiment, the second deep trench isolation 40 includes an insulating liner 41 and an insulating core 42. The insulating liner 41 and the insulating core 42 are composed of oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating liner 41 and insulating core 42 are also feasible. In a preferred embodiment, the insulating liner 41 and the insulating core 42 are respectively composed of silicon oxide. The insulating liner 41 is formed on the sidewall and the bottom of the trench. The insulating core 42 fills the inner space of the trench. The insulating liner 41 and the insulating core 42 of the second deep trench isolation 40 form a composite insulating layer to improve the isolation performance. Due to the improved isolation performance of the second deep trench isolation 40, the breakdown voltage of the semiconductor device can be improved, and since the spacing between the first conductive channel and the second conductive channel is allowed to be reduced at the same breakdown voltage, the size of the semiconductor device can be reduced.

[0051] In the peripheral region 120 of the semiconductor device 100, the first deep trench isolation 30 and the second deep trench isolation 40 respectively form an insulating isolation ring around the active regions of the first transistor 111 and the second transistor 112, the depth of the insulating isolation ring being greater than the depth of the shallow trench isolation 122 and at least reaching the position of the buried layer 103. The first conductive channel 10 is located in the region between the first deep trench isolation 30 and the second deep trench isolation 40, the first deep trench isolation 30 isolates the conductive core 12 of the first conductive channel 10 from the active region of the transistor, the second deep trench isolation 40 isolates the conductive core 12 of the first conductive channel 10 from the second conductive channel 20, the first deep trench isolation 30 and the second deep trench isolation 40 act as insulating isolation for the conductive core 12 of the first conductive channel 10, so that the insulating isolation layer around the conductive core 12 can be omitted for the first conductive channel 10.

[0052] In this embodiment, the bottom of the fourth trench does not reach the buried layer 103. In one embodiment, the distance between the bottom of the fourth trench and the bottom of the buried layer is, for example, 2 microns to 3 microns. Based on the deep trench etching process, a larger trench opening size is required to obtain a deeper trench. In the embodiment of the present application, the depth of the fourth trench is shortened, so that the opening size of the fourth trench is correspondingly reduced, thereby reducing the overall size of the device.

[0053] In this embodiment, the doped conductive material is filled into the fourth trench to form the first conductive core 12a of the first conductive channel 10, and the dopant of the first conductive core 12a in the fourth trench diffuses downward to the top of the buried layer 103 and contacts the buried layer 103, thereby forming a conductive path from the buried layer 103 to the surface of the epitaxial layer 102. In the horizontal direction, the dopant of the first conductive core 12a in the fourth trench diffuses to all sides, and the insulation isolation of the first deep trench isolation 30 and the second deep trench isolation 40 allows the dopant of the first conductive core 12a in the fourth trench to diffuse only in the area defined by the first deep trench isolation 30 and the second deep trench isolation 40. In other words, the first deep trench isolation 30 prevents the dopant of the first conductive core 12a in the fourth trench from diffusing into the active areas of the first transistor 111 and the second transistor 112, and the second deep trench isolation 40 prevents the dopant of the conductive material in the fourth trench from diffusing to the side of the second conductive channel 20, further preventing short circuit with the second conductive channel 20.

[0054] Furthermore, it should be understood that although the isolation structure described above is used to isolate the CMOS

[0055] N-type MOS transistors and P-type MOS transistors in an integrated circuit. However, it should be understood that the above isolation structure can also be used to isolate device regions of other types of integrated circuits, and the embodiments of the present disclosure are not strictly limited to this.

[0056] Figure 2 1 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device 200 according to the second embodiment includes a core region and a peripheral region surrounding the core region, and the core region of the semiconductor device 200 according to the second embodiment is completely the same as the core region of the semiconductor device 100 according to the first embodiment. Figure 2 Only the peripheral area of ​​the semiconductor device 100 is shown, and the core area of ​​the semiconductor device 100 is not described in detail.

[0057] The semiconductor device 200 includes a substrate 101, an epitaxial layer 102 disposed on the substrate 101, and a buried layer 103 disposed in at least one of the substrate 101 and the epitaxial layer 102. The substrate 101 and the epitaxial layer 102 have a first doping type, respectively, and the buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is a P type, the second doping type is an N type. Similarly, when the first doping type is an N type, the second doping type is a P type.

[0058] A first conductive channel 10 and a second conductive channel 20 are provided in the peripheral region 120 of the semiconductor device 300. The first conductive channel 10 extends from the surface of the epitaxial layer 102 to at least the top of the buried layer 103, and is used to provide an electrical connection path from the buried layer 103 to the surface of the epitaxial layer 102. The second conductive channel 20 extends from the surface of the epitaxial layer 102 to the bottom of the buried layer 103 and to the inside of the substrate 101, and is used to provide an electrical connection path from the substrate 101 to the surface of the epitaxial layer 102.

[0059] Further, in the peripheral region 120, a plurality of shallow trench isolations 122, a first deep trench isolation 30, and a second deep trench isolation 40 are also provided around the core region 110. In order to isolate the first transistor 111 and the second transistor 112 from adjacent transistors, the shallow trench isolation 122 extends from the surface of the epitaxial layer 102 to a depth D5 substantially the same as that of the shallow trench isolation 121. In order to isolate the active regions of the first transistor 111 and the second transistor 112 from the first conductive channel 10 and the second conductive channel 20, the first deep trench isolation 30 is provided inside the first conductive channel 10 and the second conductive channel 20, that is, compared with the first conductive channel 10 and the second conductive channel 20, the first deep trench isolation 30 is closer to the well region 104 of the first transistor 111 and the well region 105 of the second transistor 112. The first deep trench isolation 30 extends from the surface of the epitaxial layer 102 to the inside of the buried layer 103 to a depth D1. In order to isolate the first conductive channel 10 and the second conductive channel 20 from each other, the second deep trench isolation 40 is disposed between the first conductive channel 10 and the second conductive channel 20. The second deep trench isolation 40 extends from the surface of the epitaxial layer 102 to the substrate 101 below the buried layer 103, reaching a depth D2. The depth D4 of the first conductive channel 10, the depth D1 of the first deep trench isolation 30, the depth D2 of the second deep trench isolation 40, and the depth D3 of the second conductive channel 20 increase in sequence.

[0060] The first conductive channel 10 is used to electrically connect the buried layer 103 to the surface of the epitaxial layer 102. In one embodiment, the first conductive channel 10 includes a first conductive core 12a and a second conductive core 12b, wherein the first conductive core 12a is composed of a conductive material, such as doped polysilicon, and the second conductive core 12b is, for example, a doped region formed in the epitaxial layer 102. Other types of conductive cores 12a are also feasible. The first conductive core 12a is arranged in the fourth groove. It is worth noting that the fourth groove extends from the surface of the epitaxial layer 102 to the inside thereof, and there is a certain distance between its bottom and the top of the buried layer 103. The second conductive core 12b extends from the sidewall and bottom of the fourth trench toward a direction away from the fourth trench, wherein in the horizontal direction, the second conductive core 12b extends from the sidewall of the fourth trench toward the first deep trench isolation 30 and the second deep trench isolation 40, respectively, and is isolated from the active area of ​​the semiconductor device via the first deep trench isolation 30, and is isolated from the second conductive channel 20 via the second deep trench isolation 40; in the vertical direction, the second conductive core 12b extends from the bottom of the fourth trench toward the buried layer 103 and at least reaches the top of the buried layer 103. The first conductive core 12a and the second conductive core 12b contact each other, and together constitute a first conductive channel 10 in contact with the buried layer 103.

[0061] Furthermore, the epitaxial layer 102 between the first deep trench isolation 30 and the second deep trench isolation 40 forms an insulating isolation region S01, and the first conductive core 12a directly contacts the bottom and side walls of the fourth trench. The dopant in the first conductive core 12a diffuses from the side walls and bottom of the fourth trench toward the outside of the fourth trench. The dopant diffused into the insulating isolation region S01 (epitaxial layer 102) is of opposite type to the dopant in the insulating isolation region S01 (epitaxial layer 102). Although part of the dopant diffused into the insulating isolation region S01 is neutralized, an inverted doping region, namely the second conductive core 12b, will eventually be formed in the insulating isolation region S01.

[0062] Further, on the side of the first conductive channel 10 close to the first transistor 111 and the second transistor 112, the first deep trench isolation 30 serves as an insulating isolation for the diffusion of the first conductive core 12a, preventing the dopant in the first conductive core 12a from diffusing into the active regions of the first transistor 111 and the second transistor 112; on the side of the first conductive channel 10 close to the second conductive channel 20, the second deep trench isolation 40 serves as an insulating isolation for the first conductive core 12a, preventing the dopant in the first conductive core 12a from diffusing into the second conductive channel 20, so as to avoid a short circuit between the first conductive channel 10 and the second conductive channel 20. In other words, the second conductive core 12b is distributed throughout the insulating isolation region S01.

[0063] Furthermore, on a side of the first conductive channel 10 close to the first transistor 111 and the second transistor 112, a first deep trench isolation 30 serves as an insulating isolation for the diffusion of the first conductive core 12a, preventing dopants in the first conductive core 12a from diffusing into the active areas of the first transistor 111 and the second transistor 112; on a side of the first conductive channel 10 close to the second conductive channel 20, a second deep trench isolation 40 serves as an insulating isolation for the first conductive core 12a, preventing dopants in the first conductive core 12a from diffusing into the second conductive channel 20, so as to avoid a short circuit between the first conductive channel 10 and the second conductive channel 20.

[0064] The second conductive channel 20 is disposed in the third trench for electrically connecting the substrate 101 to the surface of the epitaxial layer 102. In one embodiment, the second conductive channel 20 includes an insulating liner 21 and a conductive core 22. The insulating liner 21 is composed of an oxide, such as silicon oxide, and the conductive core 22 is composed of a conductive material, such as doped polysilicon. Other types of insulating liners 21 and conductive cores 22 are also feasible. The insulating liner 21 is formed on a portion of the sidewall and the bottom of the trench, and includes an opening formed at the bottom of the trench. The conductive core 22 fills the trench and the opening, that is, extends from the surface of the epitaxial layer 102 to the bottom of the trench, and contacts the substrate 101. The insulating liner 21 of the second conductive channel 20 isolates the conductive core 22 from the epitaxial layer 102 and the buried layer 103.

[0065] In this embodiment, the insulating liner 21 of the second conductive channel 20 is a stack composed of multiple insulating layers, the outermost insulating layer of the multiple insulating layers is located on the side wall of the groove, and at least one intermediate insulating layer is located between the outermost insulating layer and the conductive core 22. In one embodiment, the multiple insulating layers in the insulating liner 21 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. The outermost insulating layer in the insulating liner 21 can repair the damage to the side wall of the groove when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the groove, so as to facilitate the deposition of the intermediate insulating layer thereon. The intermediate insulating layer covers the surface of the existing insulating layer in the groove, and the thickness of the intermediate insulating layer is greater than the outermost insulating layer, which is used to enhance the isolation performance between the conductive core 22 and the epitaxial layer 102 and the buried layer 103. The intermediate insulating layer is arranged inside the insulating liner 21 in the groove, and the intermediate insulating layer also includes an opening extending from the surface of the epitaxial layer 102 to the bottom of the groove. The conductive core 22 fills the inner space of the trench and the bottom opening of the trench.

[0066] Figure 2In the illustrated embodiment, the insulating liner 21 of the second conductive channel 20 is a stack of insulating layers 1101 and 1102, wherein the outermost insulating layer 1101 of the plurality of insulating layers is located on the sidewalls of the trench, and the intermediate insulating layer 1102 is located between the outermost insulating layer 1101 and the conductive core 22. In one embodiment, the insulating layers 1101 and 1102 in the insulating liner 21 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. The outermost insulating layer 1101 in the insulating liner 21 can repair the damage to the sidewalls of the trench when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the trench, so as to facilitate the deposition of the intermediate insulating layer 1102 thereon. The intermediate insulating layer 1102 covers the surface of the outermost insulating layer 1101 in the trench, and the thickness of the intermediate insulating layer 1102 is greater than that of the outermost insulating layer 1101, which is used to enhance the isolation performance between the conductive core 22 and the epitaxial layer 102 and the buried layer 103. The outermost insulating layer 1101 and the intermediate insulating layer 1102 also include an opening formed at the bottom of the trench. The conductive core 22 fills the inner space of the trench and the bottom opening of the trench.

[0067] The first conductive core 12a of the first conductive channel 10 and the conductive core 22 of the second conductive channel 20 are both composed of doped polysilicon. The first conductive core 12a of the first conductive channel 10 has the same doping type as the buried layer 103 and a higher doping concentration, so a low resistance path of the buried layer 103 can be formed. The conductive core 22 of the second conductive channel 20 has the same doping type as the substrate 101 in contact with it and a higher doping concentration, so a low resistance path of the substrate 101 can be formed. In other embodiments, it is also feasible for the first conductive channel 10 and the second conductive channel 20 to use other types of conductive cores, as long as the semiconductor layer in contact with them can be electrically connected to the surface of the epitaxial layer 102.

[0068] A contact region 101a is further provided in the substrate 101 below the second conductive channel 20. The contact region 101a has the same doping type as the substrate 101, and has a greater doping concentration than the substrate 101. The contact region 101a is opposite to the opening of the insulating liner 21 of the second conductive channel 20, and the conductive core 22 of the second conductive channel 20 contacts the contact region 101a, forming a good conductive contact with the substrate 101 via the contact region 101a.

[0069] The first deep trench isolation 30 is disposed in the first trench to isolate the active regions of the first transistor 111 and the second transistor 112 from the first conductive channel 10. In one embodiment, the first deep trench isolation 30 includes an insulating liner 31 and an insulating core 32. The insulating liner 31 is formed on the sidewall and bottom of the trench. The insulating core 32 fills the trench. The insulating liner 31 and the insulating core 32 of the first deep trench isolation 30 form a composite insulating layer to improve isolation performance.

[0070] In one embodiment, the insulating liner 31 and the insulating core 32 are composed of oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In a preferred embodiment, the insulating liner 31 and the insulating core 32 are respectively composed of silicon oxide. The insulating liner 31 can repair the damage caused to the side wall of the trench when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the trench, so as to facilitate the deposition of the insulating core 32 thereon. The insulating core 32 covers the surface of the existing insulating layer in the trench, and the insulating core 32 fills the internal space of the trench to enhance the isolation performance of the first deep trench isolation 30 and reduce stress. On the other hand, it can reduce the parasitic capacitance introduced by the deep trench isolation of the semiconductor device.

[0071] In a preferred embodiment, the first deep trench isolation 30 further includes an air gap 32a provided in the insulating core 32. Since the dielectric constant of air is smaller than that of dielectric material, the air gap 32a is used to reduce the equivalent dielectric constant of the insulating core 32, thereby further reducing the parasitic capacitance of the semiconductor device introduced by the deep trench isolation.

[0072] The second deep trench isolation 40 is arranged in the second trench for isolating the first conductive channel 10 and the second conductive channel 20 from each other. In one embodiment, the second deep trench isolation 40 includes an insulating liner 41 and an insulating core 42. The insulating liner 41 and the insulating core 42 are composed of oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating liner 41 and insulating core 42 are also feasible. In a preferred embodiment, the insulating liner 41 and the insulating core 42 are respectively composed of silicon oxide. The insulating liner 41 is formed on the sidewall and the bottom of the trench. The insulating core 42 fills the inner space of the trench. The insulating liner 41 and the insulating core 42 of the second deep trench isolation 40 form a composite insulating layer to improve the isolation performance. Due to the improved isolation performance of the second deep trench isolation 40, the breakdown voltage of the semiconductor device can be improved, and since the spacing between the first conductive channel and the second conductive channel is allowed to be reduced at the same breakdown voltage, the size of the semiconductor device can be reduced.

[0073] In this embodiment, the insulating liner 41 of the second deep trench isolation 40 includes an insulating layer located on the sidewall and bottom of the trench, which can repair the damage to the sidewall of the trench caused when the epitaxial layer 102, the buried layer 103 and the substrate 101 are deeply etched to form the trench. The insulating core 42 fills the inner space of the trench, which can reduce stress on the one hand and reduce the parasitic capacitance of the semiconductor device introduced by the deep trench isolation on the other hand.

[0074] In a preferred embodiment, the second deep trench isolation 40 and the second conductive channel 30 use a common trench etching process to reduce manufacturing costs. The opening width of the second trench of the second deep trench isolation 40 is smaller than the opening width of the third trench of the second conductive channel 20. Therefore, in the same etching step, the etching depth reached by the second deep trench isolation 40 is also smaller than the etching depth reached by the second conductive channel 20. That is, the trenches of the second conductive channel 20 and the second deep trench isolation 40 reach different depths.

[0075] In a preferred embodiment, the second deep trench isolation 40 and the second conductive channel 30 use a common trench filling process to reduce manufacturing costs. Therefore, the second deep trench isolation 40 also includes a dummy conductive core 43 provided in the insulating core 42. The dummy conductive core 43 is located in the opening inside the insulating core 42 and is separated from the epitaxial layer 102, the buried layer 103 and the substrate 101 by the insulating liner 41 and the insulating core 42. The dummy conductive core 43 is composed of a conductive material, such as doped polysilicon. Other types of dummy conductive cores 43 are also feasible.

[0076] Figures 3a to 3k Schematic cross-sectional views of a method for manufacturing an isolation structure of a semiconductor device according to a second embodiment of the present disclosure at different stages are respectively shown. Figures 3a to 3k The manufacturing method shown can be used to manufacture Figure 2 The semiconductor device 200 shown in FIG. Figure 2 The description of the semiconductor device 200 may be incorporated herein.

[0077] like Figure 3a As shown, an initial semiconductor structure including a substrate 101, an epitaxial layer 102, and a buried layer 103 is provided. The epitaxial layer 102 is, for example, a semiconductor layer disposed above the substrate 101. The buried layer 103 is, for example, a doped region disposed in one of the substrate 101 and the epitaxial layer 102, or a semiconductor layer disposed between the substrate 101 and the epitaxial layer 102.

[0078] The substrate 101 and the epitaxial layer 102 have a first doping type, respectively, and the buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. In one embodiment, an ion implantation process is used to implant a dopant of the second doping type into the substrate 101. By selecting a high dose of dopant, a portion of the substrate 101 is inverted to form a doped region of the second doping type, thereby forming a buried layer 103 of the second doping type in the substrate 101, and then, epitaxial growth is performed on the substrate 101 to form the epitaxial layer 102.

[0079] In one embodiment, by selecting the energy of ion implantation, the buried layer 103 extends downward from the surface of the substrate 101 by a predetermined distance, and further, the epitaxial layer 102 is formed by epitaxial growth on the surfaces of the substrate 101 and the buried layer 103. In another embodiment, by selecting the energy of ion implantation, the buried layer 103 is located below the surface of the substrate 101 and extends downward by a predetermined distance, and further, the epitaxial layer 102 is formed by epitaxial growth on the surface of the substrate 101. The embodiments of the present disclosure are not strictly limited to this. The epitaxial layer 102 can be used to form different device regions. The embodiments of the present disclosure are not strictly limited to this. The buried layer 103 can be a doped region arranged between the substrate 101 and the epitaxial layer 102.

[0080] In one embodiment, the buried layer 103 may have a blanket structure, which has substantially the same horizontal extension as the substrate 101 and is laid flat on the substrate 101. In another embodiment, the buried layer 103 may have a patterned structure. The embodiments of the present disclosure are not strictly limited to this. The epitaxial layer 102 may be used to form different device regions.

[0081] like Figure 3b As shown, a first trench TR1, a second trench TR2, and a second trench TR3 are formed by a trench etching process. The first trench TR1, the second trench TR2, and the second trench TR3 extend downward from the surface of the epitaxial layer 102, respectively. The first trench TR1 reaches the inside of the buried layer 103 after penetrating the epitaxial layer 102, and the second trench TR2 and the third trench TR3 reach the inside of the substrate 101 after penetrating the epitaxial layer 102 and the buried layer 103.

[0082] The trench etching process includes patterning steps to form a hard mask HM1, and etching away exposed portions of the epitaxial layer 102, the buried layer 103 and the substrate 101 through openings in the hard mask HM1. The hard mask HM1 includes, for example, a protective stack composed of multiple oxide and / or nitride layers.

[0083] In one embodiment, the step of forming the hard mask HM1 includes: growing an oxide layer HM11 on the surface of the epitaxial layer 102; depositing a nitride layer HM12 on the oxide layer HM11; and patterning the protective stack to form the hard mask HM1. In other embodiments, the hard mask HM1 may have other structures, which are not strictly limited by the embodiments of the present disclosure. In one embodiment, patterning the protective stack includes: forming a patterned resist mask on the protective stack, and patterning the protective stack via the patterned resist mask, transferring the patterns of the first trench TR1, the second trench TR2, and the third trench TR3 from the resist mask to the protective stack to form the hard mask HM1.

[0084] Next, the exposed portions of the epitaxial layer 102, the buried layer 103 and the substrate 101 are removed by etching through the openings in the hard mask HM1, and anisotropic etching (e.g., plasma etching) is used to etch downward from the surface of the epitaxial layer 102 in a vertical direction to transfer the patterns of the first trench TR1, the second trench TR2 and the third trench TR3 from the hard mask HM1 to the epitaxial layer 102, the buried layer 103 and the substrate 101.

[0085] Since the depths of the first trench TR1, the second trench TR2 and the third trench TR3 are relatively large, the plasma etching of the first trench TR1, the second trench TR2 and the third trench TR3 requires greater energy and longer time, causing damage to the trench sidewalls, which may result in a large number of silicon lattice defects on the exposed surfaces of the epitaxial layer 102, the buried layer 103 and the substrate 101 on the trench sidewalls.

[0086] According to the characteristics of the etching process, generally, the larger the opening width of the groove, the faster its etching rate. Under the same etching time, the larger the opening width of the groove, the greater the groove depth formed. In one embodiment, the opening width of the first trench TR1 is smaller than the opening width of the second trench TR2, and the opening width of the second trench TR2 is smaller than the opening width of the third trench TR3. In the same etching step, the etching depth reached by the first trench TR1 is also smaller than the etching depth reached by the second trench TR2. Similarly, the etching depth of the second trench TR2 is smaller than the etching depth of the third trench TR3. Therefore, the first trench TR1, the second trench TR2 and the third trench TR3 with different depths are formed simultaneously by using a common trench etching process.

[0087] After forming the first trench TR1 , the second trench TR2 , and the third trench TR3 , the resist mask is removed by solvent dissolution or ashing. In other embodiments, the hard mask HM1 may be patterned by other processes, which are not strictly limited in the embodiments of the present disclosure.

[0088] Although not shown in the figure, after forming the first trench TR1, the second trench TR2 and the third trench TR3, a step of ion implantation into the epitaxial layer 102 on the first side and the second side of the first trench TR1 may be further included. In this step, a dopant of a first doping type is implanted into the epitaxial layer 102 on the first side and the second side of the first trench TR1 through the opening of the first trench TR1, and the implantation direction of the dopant is inclined relative to the vertical direction, so that the dopant can be implanted into the epitaxial layer 102 on the first side and the second side of the first trench TR1 through the opening of the first trench TR1, so as to increase the doping concentration of the epitaxial layer 102 on the first side and the second side of the first trench TR1.

[0089] Furthermore, the first side of the first trench TR1 (eg Figure 3b The left side of the first trench TR1 is close to the second trench TR2, and the epitaxial layer 102 between the first side of the first trench TR1 and the second trench TR2 forms an insulating isolation region S01. Figure 3a The epitaxial layer 102 on the second side of the first trench TR1 forms the active region of the first transistor and the second transistor. The ion implantation step increases the doping concentration of the insulating isolation region on the first side of the first trench TR1 and the active region on the second side of the first trench TR1. The increase in the doping concentration of the insulating isolation region S01 will offset the second doping type dopant diffused to the region in the subsequent steps, and the increase in the doping concentration of the active region will increase the threshold holding voltage of the vertical parasitic MOS tube, making it difficult to be turned on by the voltage of the second trench isolation 40.

[0090] Further, the implantation depth H of the first doping type dopant is related to the opening size CD of the first trench TR1 and the implantation angle α of the dopant. Table 1 shows the corresponding relationship between the opening size CD of the first trench, the implantation angle α of the dopant and the implantation depth H of the dopant.

[0091] Table 1 Correspondence between the opening size CD of the first trench, the implantation angle α of the dopant and the implantation depth H of the dopant

[0092] It can be seen from Table 1 that when the injection angle α of the dopant is constant, the larger the opening size CD of the first trench TR1, the greater the injection depth H of the dopant; when the opening size CD of the first trench TR1 is constant, the larger the injection angle α of the dopant, the smaller the injection depth H of the dopant of the first doping type.

[0093] The dopant is implanted to a predetermined depth by controlling the implantation angle α of the dopant and the opening size CD of the first trench TR1. In this embodiment, the first doping type dopant is implanted into the epitaxial layer 102 on the first side and the second side of the upper portion of the first trench TR1, that is, the doping concentration of the upper portion of the insulating isolation region and the active region is increased. In one embodiment, for example, the dopant boron (B) is implanted, and the tilt angle is, for example, 5 degrees.

[0094] See also Figure 3c and Figure 3d , an outermost insulating layer 1101 and an intermediate insulating layer 1102 are formed in the first trench TR1 , the second trench TR2 , and the third trench TR3 .

[0095] The outermost insulating layer 1101 is located on the sidewalls of the trench, and the intermediate insulating layer 1102 is located on the surface of the outermost insulating layer 1101. In one embodiment, the insulating layers 1101 and 1102 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. The outermost insulating layer 1101 can repair the damage to the sidewalls of the trench when the epitaxial layer 102, the buried layer 103 and the substrate 101 are deeply etched to form the trench, so as to facilitate the deposition of the intermediate insulating layer 1102 thereon. The intermediate insulating layer 1102 covers the surface of the outermost insulating layer 1101 in the trench.

[0096] Specifically, see Figure 3c , a conformal outermost insulating layer 1101 is formed in the first trench TR1, the second trench TR2 and the third trench TR3. In this step, for example, a thermal oxidation process is used to form the outer insulating layer 1101, and the outer insulating layer 1101 is, for example, an oxide layer. The outer insulating layer 1101 covers the sidewalls of the first trench TR1, the second trench TR2 and the third trench TR3. After the outer insulating layer 1101 is formed, gaps are retained in the first trench TR1, the second trench TR2 and the third trench TR3. In other embodiments, since the opening size of the first trench TR1 is the smallest, after the outer insulating layer 1101 is formed, the first trench TR1 may also be filled with the outer insulating layer 1101. In one embodiment, the thickness of the outer insulating layer 1101 is, for example, 3000 angstroms to 5000 angstroms.

[0097] See also Figure 3d, an intermediate insulating layer 1102 is formed in the first trench TR1, the second trench TR2, and the third trench TR3. The intermediate insulating layer 1102 is located on the surface of the outer insulating layer 1101 and covers the surface of the hard mask HM1 and the sidewalls of the opening of the hard mask HM1. In this step, for example, a deposition process is used to form the intermediate insulating layer 1102, and the intermediate insulating layer 1102 is, for example, TEOS (Tetraethoxysilane). In one embodiment, the total thickness of the outer insulating layer 1101 and the intermediate insulating layer 1102 is, for example, 5000 angstroms to 7000 angstroms.

[0098] After forming the intermediate insulating layer 1102, the first trench TR1 is completely filled with the insulating layer, and due to the rapid sealing of the deposition process, an air gap 32a is formed inside the intermediate insulating layer 1102, and the second trench TR2 is completely filled with the insulating layer, and due to the rapid sealing of the deposition process, an air gap 32b is formed inside the intermediate insulating layer 1102. Since the opening size of the third trench TR3 is the largest, the intermediate insulating layer 1102 is formed, and the third trench TR3 still has a gap 32c, and the opening of the third trench TR3 is still open. In one embodiment, the width of the gap retained in the third trench TR3 is, for example, 0.4 microns to 0.8 microns. Further, the air gaps inside the first trench TR1 and the second trench TR2 help to reduce mechanical stress.

[0099] See also Figure 3e An opening penetrating the outer insulating layer 1101 and the intermediate insulating layer 1102 is formed at the bottom of the third trench TR3.

[0100] In this step, anisotropic etching, for example, plasma etching, is used, and the hard mask HM1 is still used for shielding, and the exposed portions of the outer insulating layer 1101 and the intermediate insulating layer 1102 are removed in a direction perpendicular to the substrate surface. In the third trench TR3, since the opening of the third trench TR3 is still open and the third trench TR3 still has a gap 32c, the portions of the intermediate insulating layer 1102 located on the sidewall and bottom of the trench are etched at the same time. The portions of the outermost insulating layer 1101 and the intermediate insulating layer 1102 located on the sidewall of the trench serve as an additional hard mask, and together with the hard mask HM1, are used to define the pattern of the portions of the outermost insulating layer 1101 and the intermediate insulating layer 1102 located at the bottom of the trench. By controlling the etching time, the exposed portions of the outermost insulating layer 1101 and the intermediate insulating layer 1102 located at the bottom of the trench can be completely removed to form an opening. At this time, the portions of the outermost insulating layer 1101 and the intermediate insulating layer 1102 located on the sidewalls of the trench are also etched back, but the portions located on the sidewalls of the trench are still completely retained. In the second trench TR2, since the opening of the second trench TR2 is closed by the intermediate insulating layer 1102, the intermediate insulating layer 1102 at the opening of the second trench TR2 is etched first. Through the same etching steps, the intermediate insulating layer 1102 at the opening of the second trench TR2 is etched away, so that the opening of the air gap 32b is opened, and the outermost insulating layer 1101 and the intermediate insulating layer 1102 located on the side wall of the groove are also etched back, so that the air gap 32b is further increased. However, since the opening size of the second trench TR2 is smaller than the opening size of the third trench TR3, the etching rate of the second trench TR2 is lower than that of the third trench TR3. Through the same etching steps, the outer insulating layer 1101 and the intermediate insulating layer 1102 located on the side wall and bottom of the groove are still completely retained, that is, no opening is formed at the bottom of the second trench TR2. In other embodiments, the opening of the air gap 32b in the intermediate insulating layer 1102 may not be opened, and the air gap 32b in the intermediate insulating layer 1102 is retained. In the subsequent process of forming the conductive layer 1001, the conductive layer 1001 will not be filled into the air gap 32b; in the first trench TR1, since the opening of the first trench TR1 is completely closed by the intermediate insulating layer 1102, the intermediate insulating layer 1102 at the opening of the first trench TR1 is preferentially etched, and since the opening size of the first trench TR1 is the smallest, the etching rate in the first trench TR1 is lower than that in the second trench TR2 and the third trench TR3. Through the same etching steps, a part of the intermediate insulating layer 1102 at the opening of the first trench TR1 is still retained, so that the opening of the air gap 32a is still closed by the intermediate insulating layer 1102. In a preferred embodiment, an annealing step may also be included to ensure the compactness of the intermediate insulating layer 1102.

[0101] After the etching is completed, at least part of the liner (middle insulating layer 1102) on the surface of the hard mask HM1 is retained, or the liner (middle insulating layer 1102) on the surface of the hard mask HM1 is completely removed, and the hard mask HM1 serves as an etching stop layer, wherein a part of the hard mask HM1 may be lost. In one embodiment, the thickness of the hard mask HM1 lost is less than 500 angstroms. After the above steps are completed, the outermost insulating layer 1101 in the first trench TR1 forms the insulating liner 31 of the first trench isolation 30, and the middle insulating layer 1102 forms the insulating core 32 of the first trench isolation 30, and the insulating core 32 has an air gap 32a inside. The outermost insulating layer 1101 in the second trench TR2 forms the insulating liner 41 of the second trench isolation 40, and the middle insulating layer 1102 forms the insulating core 42 of the second trench isolation 40. The insulating core 42 has an open air gap 32b inside, so that a dummy conductive core 43 is formed in the air gap 32b while the conductive core 22 of the second conductive channel 20 is subsequently formed. The outermost insulating layer 1101 and the middle insulating layer 1102 in the third trench TR3 form the insulating liner 21 of the second conductive channel 20, and the air gap 32c inside the middle insulating layer 1102 is used to form the conductive core 22 of the second conductive channel 20 in a subsequent step.

[0102] During the above-mentioned insulating layer filling and etching process, by controlling the opening sizes of the first trench TR1, the second trench TR2 and the third trench TR3, the insulating layers in the first trench TR1, the second trench TR2 and the third trench TR3 can be formed through the same filling and etching steps, and different filling forms are formed in the first trench TR1, the second trench TR2 and the third trench TR3.

[0103] Furthermore, the method further includes a step of forming a contact region 101a of the substrate 101. In this step, a dopant of a first doping type is injected into the substrate 101 exposed at the bottom of the third trench TR3 through the opening at the bottom of the third trench TR3 to form the contact region 101a of the substrate 101. The contact region 101a enables the subsequently formed conductive layer 1001 to form a good conductive contact with the substrate 101.

[0104] See also Figure 3f , a conductive layer 1001 is deposited, and the conductive layer 1001 fills the inner space (air gap 32 c ) of the third trench TR3 , the bottom opening, and the inner space (air gap 32 b ) of the second trench TR2 .

[0105] The conductive layer 1001 contacts the substrate 101 or the contact area 101a through the opening at the bottom of the third trench TR3. The conductive layer 1001 has the same doping type as the substrate 101 and a higher doping concentration, thereby forming a low resistance path of the substrate 101. Inside the third trench TR3, the conductive layer 1001 is separated from the epitaxial layer 102 and the buried layer 103 by the outermost insulating layer 1101 and the intermediate insulating layer 1102. Inside the second trench TR2, the conductive layer 1001 is separated from the substrate 101, the epitaxial layer 102, and the buried layer 103 by the outermost insulating layer 1101 and the intermediate insulating layer 1102. Outside the second trench TR2 and the third trench TR3, the conductive layer 1001 covers the surface of the hard mask HM1 or the retained intermediate insulating layer 1102. In one embodiment, the conductive layer 1001 includes polysilicon with a first doping type. Other types of conductive layers 1001 are also feasible.

[0106] Further, multiple deposition steps and multiple etching steps are performed alternately to form the final conductive layer 1001. In one embodiment, the conductive layer 1001 is formed by the steps of a first deposition, back etching, and a second deposition. Based on the characteristics of deep groove deposition, the deposition rate at the groove opening during the deposition of the conductive layer 1001 is greater than the deposition rate inside the groove, resulting in a relatively large air gap inside the groove when the opening of the groove is closed by the conductive layer 1001, thereby affecting the conductive connection of the substrate 101. Therefore, in this embodiment, after the first deposition, a back etching process is added to open the opening of the groove, provide a path for the deposition of the conductive layer 1001 inside the groove, reduce the air gap inside the groove, and improve the deposition quality of the conductive layer 1001 inside the groove.

[0107] See also Figure 3g By removing the portion of the conductive layer 1001 outside the second trench TR2 and the third trench TR3 , a dummy conductive core 43 is formed in the second trench TR2 , and a conductive core 22 is formed in the third trench TR3 .

[0108] In one embodiment, one or more protective layers in the hard mask HM1 are used as stop layers, and chemical mechanical polishing (CMP) is used to remove the portion of the conductive layer 1001 outside the first trench TR1 and the second trench TR1, and the portion of the conductive layer 1001 located in the second trench TR2 is retained to form the dummy conductive core 43, and the portion located in the third trench TR3 is retained to form the conductive core 22. In the process of removing the conductive layer 1001 by chemical mechanical polishing (CMP), a portion of the hard mask HM1 may be lost. In one embodiment, the thickness of the hard mask HM1 lost is less than 500 angstroms. In another embodiment, one or more protective layers in the hard mask HM1 are used as stop layers, and the conductive layer 1001 is etched to remove the portion of the conductive layer 1001 located outside the second trench TR2 and the third trench TR3, and the portion of the conductive layer 1001 located inside the second trench TR2 and the third trench TR3 is etched back. In yet another embodiment, after the chemical mechanical planarization, the portion of the conductive layer 1001 located inside the second trench TR2 and the third trench TR3 is etched back.

[0109] See also Figure 3h A fourth trench TR4 is formed in the epitaxial layer 102 (ie, the insulating isolation region S01 ) between the first trench TR1 and the second trench TR2 by using a trench etching process. The fourth trench TR4 extends downward from the surface of the epitaxial layer 102 to the inside of the epitaxial layer 102 .

[0110] The trench etching process includes forming a patterned resist mask on the surface of the hard mask HM1, etching the hard mask HM1 through the resist mask, and transferring the pattern of the fourth trench TR4 from the resist mask to the hard mask HM1. Then, etching the epitaxial layer 102 through the hard mask HM1, and transferring the pattern of the fourth trench TR4 from the hard mask HM1 to the epitaxial layer 102.

[0111] It is worth noting that the bottom of the fourth trench TR4 does not reach the buried layer 103. In one embodiment, the distance between the bottom of the fourth trench TR4 and the bottom of the buried layer 103 is, for example, 2 microns to 3 microns. Based on the deep trench etching process, a larger trench opening size is required to obtain a deeper trench. In this application, the depth of the fourth trench TR4 is shortened, so that the opening size of the fourth trench TR4 is correspondingly reduced, saving the area of ​​the device and reducing the overall size of the device.

[0112] In one embodiment, the opening size of the fourth trench TR4 is, for example, the first size, so as to ensure that the bottom of the fourth trench TR4 reaches the buried layer 103. In this embodiment, the opening size of the fourth trench TR4 can be set to a second size smaller than the first size, so that there is a certain distance between the bottom of the fourth trench TR4 and the bottom of the buried layer 103.

[0113] See also Figure 3i , depositing a conductive layer 1002, which fills the inner space of the fourth trench TR4, and covers the surface of the hard mask HM1 outside the fourth trench TR4. The conductive layer 1002 is, for example, doped polysilicon, and has the same doping type as the buried layer 103.

[0114] See also Figure 3j , by removing the portion of the conductive layer 1002 outside the fourth trench TR4, a first conductive core 12a located in the fourth trench TR4 is formed. In one embodiment, one or more protective layers in the hard mask HM1 are used as stop layers, and chemical mechanical polishing (CMP) is used to remove the portion of the conductive layer 1002 located outside the fourth trench TR4. In another embodiment, one or more protective layers in the hard mask HM1 are used as stop layers, and the conductive layer 1002 is etched to remove the portion of the conductive layer 1002 located outside the fourth trench TR4, and the portion of the conductive layer 1002 located inside the fourth trench TR4 is etched back to form the first conductive core 12a located in the fourth trench TR4. At the same time, the first conductive core 12a in the fourth trench TR4, the dummy conductive core 43 in the second trench TR2, and the conductive core 22 in the third trench TR3 are etched back, so that the dummy conductive core 43 in the second trench TR2, the conductive core 22 in the third trench TR3, and the first conductive core 12a in the fourth trench TR4 are flush with the surface of the epitaxial layer 102. In another embodiment, after the above-mentioned chemical mechanical planarization, the first conductive core 12a in the fourth trench TR4 is etched back, and at the same time, the dummy conductive core 43 in the second trench TR2 and the conductive core 22 in the third trench TR3 are etched back.

[0115] See also Figure 3k , remove the hard mask HM1. For example, wet etching is used to remove the hard mask HM1, such as using phosphoric acid solution to remove the nitride layer in the hard mask HM1, and using diluted hydrofluoric acid to remove the oxide layer in the hard mask HM1.

[0116] After the above-mentioned method for manufacturing the isolation structure of the semiconductor device, the active region structure of the transistor is formed in the core region of the semiconductor device according to known processes and steps, so as to obtain the complete structure of the final semiconductor device.

[0117] It is worth noting that, during the high temperature process of forming the active region structure of the transistor, the dopant in the first conductive core 12a in the fourth trench TR4 diffuses toward the outside of the fourth trench TR4 through the bottom and sidewall of the fourth trench TR4. In the vertical direction, the dopant in the conductive layer 1002 in the fourth trench TR4 diffuses downward and at least diffuses to the top of the buried layer 103, so that the epitaxial layer 102 between the bottom of the fourth trench TR4 and the top of the buried layer 103 is inverted; in the horizontal direction, the dopant in the conductive layer 1002 in the fourth trench TR4 will also diffuse laterally to the epitaxial layer 102 (i.e., the insulating isolation region S01) on both sides of the fourth trench TR4. The fourth trench TR4 is formed in the insulating isolation region S01 (the epitaxial layer 102 between the first deep trench isolation 30 and the second deep trench isolation 40), the insulating isolation region S01 has a first doping type, the conductive layer 1002 has a second doping type, and the dopant of the second doping type diffused to the upper part of the insulating isolation region S01 is partially neutralized, but still makes the insulating isolation region S01 inverted. In other words, the second conductive core 12a is a doping region formed in the epitaxial layer 102. The first conductive core 12a and the second conductive core 12b are in contact with each other to form a conductive path from the buried layer 103 to the surface of the epitaxial layer 102.

[0118] Combination of the above Figures 3a to 3k A method for manufacturing an isolation structure of a semiconductor device is described. The method includes a first conductive channel 10 and a second conductive channel 20, a first deep trench isolation 30, and a second deep trench isolation 40 in a peripheral region 120 of a semiconductor device 300. The first deep trench isolation 30 surrounds an active region of a transistor to isolate the first conductive channel 10 from the active region of the transistor, and the second deep trench isolation 40 is located between the first conductive channel 10 and the second conductive channel 20 to isolate the first conductive channel 10 from the second conductive channel 20.

[0119] See also Figure 3k The first conductive channel 10 includes a first conductive core 12a and a second conductive core 12b, and the first conductive core 12a and the second conductive core 12b are in contact with each other to form a conductive path from the buried layer 103 to the surface of the epitaxial layer 102. The first conductive channel 10 includes a conductive core 12. The first conductive channel 10 is used to provide an electrical connection path from the buried layer 103 to the surface of the epitaxial layer 102. The second conductive channel 20 extends from the surface of the epitaxial layer 102 to the bottom of the buried layer 103 and reaches the inside of the substrate 101. The second conductive channel 20 includes a conductive core 22 and an insulating liner 21 surrounding the conductive core 22. The second conductive channel provides an electrical connection path from the substrate 101 to the surface of the epitaxial layer 102. The first deep trench isolation 30 includes an insulating core 32 and an insulating liner 31 surrounding the insulating core 32.

[0120] According to the method for manufacturing the isolation structure of the semiconductor device of the second embodiment, the insulating liner 31 in the first deep trench isolation 30 is formed on the sidewall and a part of the bottom of the trench. The insulating core 32 fills the trench. The insulating liner 31 and the insulating core 32 of the first deep trench isolation 30 form a composite insulating layer to improve the isolation performance. Compared with the existing semiconductor device isolation structure, in the semiconductor device isolation structure disclosed in the present invention, the insulating liner 31 is used as a conformal layer in the trench, which can be used to repair the damage to the sidewall of the trench when the epitaxial layer 102 is deeply etched to form the trench, thereby reducing the crystal defects and / or dislocation defects at the silicon / silicon oxide interface. The insulating core 32 is used as a filling layer in the trench, which can reduce stress on the one hand, and on the other hand, can reduce the parasitic capacitance introduced by the semiconductor device due to the deep trench isolation. Therefore, the semiconductor device disclosed in the present invention adopts the above-mentioned improved isolation structure process to block the vertical flow path of the leakage current between the well region and the buried layer of the transistor, thereby reducing the power consumption of the semiconductor device and improving the reliability of the semiconductor device.

[0121] In the etching step for forming the first, second and third grooves, if the opening widths of the plurality of grooves are different, the etching depths reached by the plurality of grooves are different after the same etching time. The larger the opening width of the groove, the greater the etching depth of the groove. On the contrary, the smaller the opening width of the groove, the smaller the etching depth of the groove.

[0122] In this embodiment, the first deep trench isolation 30, the second deep trench isolation 30, and the second conductive channel 20 are formed in the first trench, the second trench, and the third trench, respectively. In a preferred embodiment, by selecting the opening widths of the first trench, the second trench, and the third trench, a common trench etching process can be used to simultaneously form the first trench, the second trench, and the third trench with different depths. This can not only reduce the process steps and the number of masks for manufacturing the isolation structure, but also avoid the depth deviation of the first trench, the second trench, and the third trench due to the independent etching steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the semiconductor device.

[0123] According to the second embodiment, the method for manufacturing the isolation structure of the semiconductor device includes forming a first deep trench isolation extending from the surface of the epitaxial layer to the buried layer, and utilizing the lateral and vertical flows of the leakage current to reduce the power consumption of the semiconductor device and improve the reliability of the semiconductor device.

[0124] Furthermore, the isolation structure manufacturing method also includes forming a second deep trench isolation extending from the surface of the epitaxial layer into the substrate. The second deep trench isolation is located between the first conductive channel and the second conductive channel, and the insulating liner and the insulating core in the second deep trench isolation form a composite insulating layer to improve the isolation performance between the first conductive channel and the second conductive channel.

[0125] The embodiments of the present disclosure are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made, including but not limited to changes in the local structure of the circuit, and replacement of the type or model of components. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and the modified use based on the present disclosure. The present disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an isolation structure of a semiconductor device, comprising: forming an epitaxial layer on a substrate; forming a buried layer between the substrate and the epitaxial layer; forming a first trench and a second trench, wherein the first trench extends from the surface of the epitaxial layer into the buried layer, and the second trench extends from the surface of the epitaxial layer into the substrate; forming a first deep trench isolation in the first trench, forming a second deep trench isolation in the second trench, forming a fourth trench between the first deep trench isolation and the second deep trench isolation, wherein the fourth trench extends from the surface of the epitaxial layer to the inside thereof, and a certain distance exists between the bottom of the fourth trench and the top of the buried layer; forming a first conductive core in the fourth trench; as well as A second conductive core is formed extending from the sidewall and the bottom of the trench toward a direction away from the fourth trench. In the vertical direction, the second conductive core at least extends to the top of the buried layer.

2. The method according to claim 1, wherein: The first conductive core is a doped conductive layer and has a second doping type; the first conductive core fills the fourth trench and is in direct contact with the bottom and sidewall of the fourth trench; Through a thermal process, dopants in the second conductive core diffuse out of the fourth trench to form a second conductive core of a second doping type in the epitaxial layer outside the fourth trench, and the second conductive core contacts the first conductive core to form a first conductive channel.

3. The method according to claim 1, wherein: After forming the first trench, the method also includes a step of implanting ions into the epitaxial layer on the first side of the first trench and the epitaxial layer on the second side of the fourth trench through the opening of the first trench, wherein the epitaxial layer has a first doping type, and the ion implantation implants dopants having the same doping type as the epitaxial layer into the epitaxial layer.

4. The method according to claim 3, wherein: By controlling the opening size of the first trench and the angle of ion implantation, dopants are implanted into the first side and the second side of the first trench.

5. The method according to claim 1, wherein: Also includes: forming a third groove; as well as forming a second conductive channel in the third trench; Wherein, the opening widths of the first groove, the second groove and the third groove increase sequentially.

6. The method according to claim 5, wherein: The first trench, the second trench, and the third trench are formed simultaneously.

7. The method according to claim 6, wherein: After forming the first trench, the second trench and the third trench, the method further includes: forming a conformal outer insulating layer in the first trench, the second trench and the third trench, wherein the outer insulating layer in the first trench constitutes an insulating liner for the first deep trench isolation, and the outer insulating layer in the second trench constitutes an insulating liner for the second deep trench isolation; forming an intermediate insulating layer in the first trench, the second trench and the third trench, the intermediate insulating layer filling the first trench and closing the opening of the first trench, the intermediate insulating layer filling the second trench and closing the opening of the second trench, and the intermediate insulating layer conformally covering the outer insulating layer in the third trench; Etch back the middle insulating layer to form an opening penetrating the outer insulating layer and the middle insulating layer at the bottom of the third trench, the outer insulating layer and the middle insulating layer on the sidewall of the third trench are retained to form an insulating liner of the second conductive channel, the middle insulating layer in the first trench is retained to form an insulating core of the first deep trench isolation, and the middle insulating layer in the second trench is retained to form an insulating core of the second deep trench isolation; The third trench and the opening at the bottom of the third trench are filled with a conductive layer to form a conductive core of the second conductive channel.

8. The method according to claim 7, wherein: During the process of forming the intermediate insulating layer, an air gap is formed inside the intermediate insulating layer in the first trench.

9. The method according to claim 7, wherein: During the process of forming the intermediate insulating layer, an air gap is formed inside the intermediate insulating layer in the second trench; During the process of etching back the intermediate insulating layer, the opening of the air gap in the intermediate insulating layer in the second trench is opened; While the third trench and the opening at the bottom of the third trench are filled with a conductive layer, the interior of the intermediate insulating layer in the second trench is filled with a conductive layer to form a dummy conductive core.

10. The method according to claim 7, wherein: During the process of forming the intermediate insulating layer, an air gap is formed inside the intermediate insulating layer in the second trench; During the process of etching back the intermediate insulating layer, the opening of the air gap in the intermediate insulating layer in the second trench is still closed, and the air gap inside the intermediate insulating layer in the second trench is retained.

11. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 10; the semiconductor device comprises: substrate; an epitaxial layer located on the substrate; a buried layer between the substrate and the epitaxial layer; A first deep trench isolation is located in a peripheral region of the semiconductor device and surrounds an active region of a transistor, wherein the first deep trench isolation extends from a surface of the epitaxial layer into the buried layer; a second deep trench isolation located in a peripheral region of the semiconductor device and surrounding the first deep trench isolation, the second deep trench isolation extending from a surface of the epitaxial layer into the substrate; and A first conductive channel is located between the first deep trench isolation and the second deep trench isolation; A trench is formed between the first deep trench isolation and the second deep trench isolation, the trench extends from the surface of the epitaxial layer to the inside thereof, and the bottom of the trench is at a certain distance from the top of the buried layer; The first conductive channel includes a first conductive core located in the trench, and a second conductive core extending from the sidewall and bottom of the trench toward a direction away from the fourth trench. In the vertical direction, the second conductive core extends at least to the top of the buried layer.

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