Static random access memory, gate structure and forming method thereof
By using the LELE process architecture and the amorphous carbon layer and oxide layer as hard mask layer in miniature SRAM, the problems of rounded corners and depressions of the gate structure ends are solved, and the effect of reducing leakage and meeting the minimum voltage is achieved.
Patent Information
- Application Number
- CN202411617743.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-03-07
AI Technical Summary
The gate structure ends in miniature SRAM have rounded corners and depressions, resulting in excessive leakage of the device and the minimum voltage cannot be met.
Using the LELE process architecture and an amorphous carbon layer and an oxide layer as the hard mask layer, an opening pattern is formed on the hard mask layer through multiple etching processes and transferred to the polysilicon material layer to form a gate structure.
The shape of the gate terminal is effectively controlled, the leakage problem is reduced, and the minimum voltage of the SRAM can meet the standards.
Smart Images
Figure CN119581320A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a static random access memory, a gate structure and a forming method thereof. Background Art
[0002] Some products require a large area of static random access memory (SRAM). The size of the bit cell of the SRAM directly affects the PPA (performance, power, area) competitiveness of the process platform, so a shrunken SRAM design is often required. Due to the shrunken design of SRAM, there are higher requirements for the process technology, especially the gate (poly) process flow. Figure 1 This is a SEM image of the gate structure formed by single-step etching in the prior art. Using the existing process, the end (Poly head) of the gate structure 11a in the miniaturized SRAM will have rounding and pitting problems, which will cause the device leakage to be too high, and the minimum voltage (V min ) cannot meet the standard. Summary of the invention
[0003] The object of the present invention is to provide a gate structure and a method for forming the same, so as to solve at least one of the problems that the ends of the gate structure in a miniaturized SRAM have rounded corners and depressions, resulting in excessive device leakage and failure to meet the minimum voltage of the SRAM.
[0004] In order to solve the above technical problems, the present invention provides a method for forming a gate structure, comprising:
[0005] Providing a substrate, on which a polysilicon material layer and a hard mask layer are formed, wherein the hard mask layer includes an amorphous carbon layer and an oxide layer;
[0006] Performing a first etching process to form a first opening pattern on the hard mask layer along a first direction, wherein the first opening pattern is used to form a gate structure;
[0007] Performing a second etching process to form a second opening pattern on the hard mask layer along a second direction, wherein the second opening pattern is used to cut the gate structure, and the second direction is perpendicular to the first direction;
[0008] Performing a third etching process to remove the oxide layer in the hard mask layer;
[0009] A fourth etching process is performed to etch the polysilicon material layer using the amorphous carbon layer in the hard mask layer as a mask, and the first opening pattern and the second opening pattern in the hard mask layer are transferred to the polysilicon material layer to form a gate structure.
[0010] Optionally, before performing the first etching process, the process includes:
[0011] forming a first photoresist layer, wherein the first photoresist layer covers the oxide layer;
[0012] A first exposure process is performed to form a patterned first photoresist layer, wherein the patterned first photoresist layer includes a first opening pattern, and the first opening pattern in the patterned first photoresist layer exposes the oxide layer in a first direction.
[0013] Optionally, after performing the first etching process, a wet etching process is used to remove the patterned first photoresist layer.
[0014] Optionally, before performing the second etching process, the method includes:
[0015] forming a second photoresist layer, wherein the second photoresist layer covers the oxide layer;
[0016] A second exposure process is performed to form a patterned second photoresist layer, wherein the patterned second photoresist layer includes a second opening pattern, and the second opening pattern in the patterned second photoresist layer exposes the oxide layer in a second direction.
[0017] Optionally, after performing the second etching process, a wet etching process is used to remove the patterned second photoresist layer.
[0018] Optionally, the first etching process, the second etching process and the fourth etching process are all dry etching processes, and the third etching process is a wet etching process.
[0019] Optionally, after forming the gate structure, the method further comprises:
[0020] Performing a linear oxidation process to form a linear oxide layer, wherein the linear oxide layer covers the amorphous carbon layer, the sidewall of the gate structure and the surface of the substrate, and the linear oxide layer on the sidewall of the gate structure constitutes a sidewall of the gate structure;
[0021] A fifth etching process is performed to remove the amorphous carbon layer, and the sidewall of the gate structure protects the end shape of the gate structure.
[0022] Optionally, the fifth etching process is an oxidation stripping process.
[0023] Based on the same inventive concept, the present invention further provides a gate structure, which is prepared by any of the above-mentioned methods for forming the gate structure.
[0024] Based on the same inventive concept, the present invention also provides a static random access memory including the gate structure described above.
[0025] In a method for forming a gate structure provided by the present invention, a first etching process is first performed to form a first opening pattern on a hard mask layer along a first direction, and the first opening pattern is used to form a gate structure; then a second etching process is performed to form a second opening pattern on the hard mask layer along a second direction, and the second opening pattern is used to cut the gate structure; then a third etching process is performed to remove the oxide layer in the hard mask layer; finally, a fourth etching process is performed to use the amorphous carbon layer in the hard mask layer as a mask to etch the polysilicon material layer to form a gate structure. The present invention uses a LELE process architecture and a technical solution of using an amorphous carbon layer and an oxide layer as a hard mask layer. The oxide layer in the hard mask layer effectively protects the amorphous carbon layer, and the LELE process architecture can well control the shape of the gate terminal, reducing the leakage problem of the gate structure, so that the minimum voltage of the SRAM can meet the standard. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0027] Figure 1 This is a SEM image of a gate structure formed by single-step etching in the prior art.
[0028] Figure 2 is a flow chart of a method for forming a gate structure according to an embodiment of the present invention.
[0029] Figure 3 It is a schematic structural diagram of forming a patterned first photoresist layer according to an embodiment of the present invention.
[0030] Figure 4 It is a structural schematic diagram of forming a first opening pattern on a hard mask layer according to an embodiment of the present invention.
[0031] Figure 5 It is a schematic structural diagram of removing the patterned first photoresist layer according to an embodiment of the present invention.
[0032] Figure 6 It is a schematic top view of a structure in which a first opening pattern is formed on a hard mask layer according to an embodiment of the present invention.
[0033] Figure 7 It is a schematic structural diagram of forming a patterned second photoresist layer according to an embodiment of the present invention.
[0034] Figure 8 It is a structural schematic diagram of forming a second opening pattern on a hard mask layer according to an embodiment of the present invention.
[0035] Fig. 9 It is a schematic structural diagram of removing the patterned second photoresist layer according to an embodiment of the present invention.
[0036] Fig.10 It is a schematic top view of a structure in which a second opening pattern is formed on a hard mask layer according to an embodiment of the present invention.
[0037] Fig.11 It is a schematic diagram of the structure of removing the oxide layer in an embodiment of the present invention.
[0038] Fig.12 It is a schematic structural diagram of forming a gate structure according to an embodiment of the present invention.
[0039] Fig.13 It is a schematic structural diagram of forming a gate structure sidewall according to an embodiment of the present invention.
[0040] Fig.14 It is a schematic structural diagram of removing an amorphous carbon layer according to an embodiment of the present invention.
[0041] Fig.15 1 is a schematic top view of a gate structure formed according to an embodiment of the present invention.
[0042] Fig.16 is a SEM image of the gate structure of an embodiment of the present invention.
[0043] In the attached figure:
[0044] 10-substrate; 11-polysilicon material layer; 11a-gate structure; 12-amorphous carbon layer; 13-oxide layer; 14-patterned first photoresist layer; 14a-first opening pattern; 15-patterned second photoresist layer; 15a-second opening pattern; 16-linear oxide layer. DETAILED DESCRIPTION
[0045] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0046] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0047] Figure 2 FIG. 1 is a flow chart of a method for forming a gate structure according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a gate structure, including:
[0048] Step S10, providing a substrate, on which a polysilicon material layer and a hard mask layer are formed, wherein the hard mask layer includes an amorphous carbon layer and an oxide layer;
[0049] Step S20, performing a first etching process to form a first opening pattern on the hard mask layer along a first direction, wherein the first opening pattern is used to form a gate structure;
[0050] Step S30, performing a second etching process to form a second opening pattern on the hard mask layer along a second direction, wherein the second opening pattern is used to cut the gate structure, and the second direction is perpendicular to the first direction;
[0051] Step S40, performing a third etching process to remove the oxide layer in the hard mask layer;
[0052] Step S50, performing a fourth etching process, using the amorphous carbon layer in the hard mask layer as a mask to etch the polysilicon material layer, and transferring the first opening pattern and the second opening pattern in the hard mask layer to the polysilicon material layer to form a gate structure.
[0053] Figure 3It is a schematic structural diagram of forming a patterned first photoresist layer according to an embodiment of the present invention. Figure 4 It is a structural schematic diagram of forming a first opening pattern on a hard mask layer according to an embodiment of the present invention. Figure 5 It is a schematic structural diagram of removing the patterned first photoresist layer according to an embodiment of the present invention. Figure 6 It is a schematic top view of a structure in which a first opening pattern is formed on a hard mask layer according to an embodiment of the present invention. Figure 7 It is a schematic structural diagram of forming a patterned second photoresist layer according to an embodiment of the present invention. Figure 8 It is a structural schematic diagram of forming a second opening pattern on a hard mask layer according to an embodiment of the present invention. Fig. 9 It is a schematic structural diagram of removing the patterned second photoresist layer according to an embodiment of the present invention. Fig.10 It is a schematic top view of a structure in which a second opening pattern is formed on a hard mask layer according to an embodiment of the present invention. Fig.11 It is a schematic diagram of the structure of removing the oxide layer in an embodiment of the present invention. Fig.12 It is a schematic structural diagram of forming a gate structure according to an embodiment of the present invention. Fig.13 It is a schematic structural diagram of forming a gate structure sidewall according to an embodiment of the present invention. Fig.14 It is a schematic structural diagram of removing an amorphous carbon layer according to an embodiment of the present invention. Fig.15 1 is a schematic top view of a gate structure formed according to an embodiment of the present invention. Fig.16 1 is a SEM image of the gate structure of an embodiment of the present invention. In order to make the above-mentioned purpose, features and beneficial effects of the present invention more clearly understood, the following is a SEM image of the gate structure of an embodiment of the present invention. Figures 3 to 16 The specific embodiments of the present invention are described in detail.
[0054] like Figure 3 As shown, a substrate 10 is provided. The substrate 10 can provide an operating platform for subsequent processes. The substrate 10 can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 is a silicon substrate.
[0055] Please continue to refer to Figure 3, a polysilicon material layer 11, an amorphous carbon layer 12 and an oxide layer 13 are formed on the substrate 10. The polysilicon material layer 11 is used to form a gate structure, and the amorphous carbon layer 12 and the oxide layer 13 are used as hard mask layers to protect the ends of the gate structure in the subsequent etching process to avoid rounding problems at the ends of the gate structure. The polysilicon material layer 11, the amorphous carbon layer 12 and the oxide layer 13 can be formed by a chemical vapor deposition process.
[0056] Please continue to refer to Figure 3 , forming a first photoresist layer, the first photoresist layer covers the oxide layer 13. The first photoresist layer is a three-layer photoresist material (Tri-layer). The three-layer photoresist material specifically refers to photoresist (resist), Si-containing anti-reflective coating (SiARC) and spin-coated organic carbon. Perform a first exposure process to form a patterned first photoresist layer 14, the patterned first photoresist layer 14 includes a first opening pattern 14a, the first opening pattern 14a is an opening in a first direction, and the first opening pattern is used to form a gate structure. The first opening pattern 14a in the patterned first photoresist layer 14 exposes the oxide layer 13 in the first direction.
[0057] Please refer to Figure 4 , performing a first etching process, using the patterned first photoresist layer 14 as a mask, sequentially etching the oxide layer 13 and the amorphous carbon layer 12, transferring the first opening pattern 14a in the patterned first photoresist layer 14 to the oxide layer 13 and the amorphous carbon layer 12, and forming a first opening pattern 14a on the amorphous carbon layer 12 and the oxide layer 13 along a first direction, wherein the first opening pattern 14a is a pattern of a gate structure, and the first opening pattern 14a is used to form a gate structure. The first etching process is, for example, a dry etching process.
[0058] Please refer to Figure 5 After the first opening pattern 14a is formed in the oxide layer 13 and the amorphous carbon layer 12, if the patterned first photoresist layer 14 has not been completely consumed, a photoresist removal process is required, and the residual patterned photoresist is usually removed by an ashing process or a stripping method. In this embodiment, a wet stripping process is used to remove the patterned first photoresist layer 14.
[0059] Please refer to Figure 6 After removing the patterned first photoresist layer 14, the remaining oxide layer 13 and the amorphous carbon layer 12 are in the shape of a subsequent gate structure, and the remaining oxide layer 13 and the amorphous carbon layer 12 extend along the first direction.
[0060] Please refer to Figure 7, forming a second photoresist layer, wherein the second photoresist layer covers the oxide layer 13. The second photoresist layer is a three-layer photoresist material (Tri-layer). The three-layer photoresist material specifically refers to a photoresist (resist), an anti-reflective coating (SiARC) containing Si, and spin-coated organic carbon. Perform a second exposure process to form a patterned second photoresist layer 15. The patterned second photoresist layer 15 includes a second opening pattern 15a, the second opening pattern 15a is an opening in a second direction, the second opening pattern 15a is a gate line end cutting pattern (Poly Cut, POC), and the second opening pattern 15a is used to cut the gate structure. The second opening pattern 15a in the patterned second photoresist layer 15 exposes the oxide layer 13 in the second direction. Wherein, the first direction is perpendicular to the second direction.
[0061] Please refer to Figure 8 , performing a second etching process, using the patterned second photoresist layer 15 as a mask, sequentially etching the oxide layer 13 and the amorphous carbon layer 12, transferring the second opening pattern 15a in the patterned second photoresist layer 15 to the oxide layer 13 and the amorphous carbon layer 12, and forming a second opening pattern 15a on the amorphous carbon layer 12 and the oxide layer 13 along a second direction, wherein the second opening pattern 15a is a gate line end cutting pattern, and the second opening pattern 15a is used to cut the gate structure. The second etching process is, for example, a dry etching process.
[0062] Please refer to Fig. 9 After the second opening pattern 15a is formed in the oxide layer 13 and the amorphous carbon layer 12, if the patterned second photoresist layer 15 has not been completely consumed, a photoresist removal process is required, and the residual patterned photoresist is usually removed by an ashing process or a stripping method. In this embodiment, a wet stripping process is used to remove the patterned second photoresist layer 15.
[0063] Please refer to Fig.10 After removing the patterned second photoresist layer 15, a second opening pattern 15a is formed in the oxide layer 13 and the amorphous carbon layer 12. The second opening pattern 15a is perpendicular to the remaining oxide layer 13 and the amorphous carbon layer 12.
[0064] Please refer to Fig.11 , perform a third etching process to remove the oxide layer 13. The third etching process is a wet etching process. The etching solution of the third etching process is, for example, HF.
[0065] Please refer to Fig.12, a fourth etching process is performed, using the amorphous carbon layer 12 as a mask to etch the polysilicon material layer 11 to form a gate structure 11a. The fourth etching process is, for example, a dry etching process. In the fourth etching process, the first opening pattern 14a and the second opening pattern 15a in the amorphous carbon layer 12 are simultaneously transferred to the polysilicon material layer 11, and the gate structure 11a is formed while the gate structure 11a is cut into segments.
[0066] Please refer to Fig.13 , a linear oxidation process is performed to form a linear oxide layer, which covers the amorphous carbon layer 12, the sidewalls of the gate structure 11a and the surface of the substrate 10. The linear oxide layer 16 located on the sidewalls of the gate structure 11a constitutes the sidewalls of the gate structure. The linear oxide layer is used to protect the end of the gate structure 11a and the surface of the substrate 10 from being damaged in the subsequent etching process.
[0067] Please refer to Fig.14 After forming the sidewall 16 of the gate structure, a fifth etching process is performed to remove the amorphous carbon layer 12. The fifth etching process is an oxidation stripping process. Due to the protection of the linear oxide layer 16, the oxidation stripping process has no effect on the shape of the end of the gate structure 11a, solves the problem of the rounding of the end of the gate structure 11a, reduces the leakage of the device, and makes the minimum voltage (V min Meanwhile, since the linear oxide layer 16 covers the surface of the substrate 10, in the fifth etching process, the linear oxide layer 16 protects the substrate surface from being damaged.
[0068] Please refer to Fig.14 and Fig.15 The present embodiment further provides a gate structure, which is prepared by any of the above-mentioned gate structure forming methods, including a substrate 10 and an active area 10a located in the substrate, and a gate structure 11a is formed on the substrate 10 and the active area 10a. The gate structure 11a is vertically arranged with respect to the active area 10a, and the gate structures on adjacent active areas 10a are isolated from each other.
[0069] This embodiment also provides a static random access memory, including the gate structure described above.
[0070] Please refer to Fig.16, the gate structure 11a formed in this embodiment is cut by the second opening pattern 15a. This embodiment adopts the LELE process architecture and uses the amorphous carbon layer and the oxide layer (Carbon+Oxide) as the hard mask layer structure to form the gate structure 11a. In the process of forming the gate structure 11a, after forming the first opening pattern 14a and the second opening pattern 15a in the hard mask layer, when removing the oxide layer in the hard mask layer, since the amorphous carbon layer protects the polysilicon material layer, the etching process of the oxide layer will not affect the polysilicon material layer. After forming the gate structure and growing the linear oxide layer (Side wall liner oxide) of the side wall of the gate structure, the amorphous carbon layer (poly head Carbon) on the gate structure is removed by the oxidation stripping (O2 stripe) process. The linear oxide layer 16 fully protects the end of the gate structure and the corner silicon (Corner Si) on the substrate, solving the problems of carbon damage (Carbon damage) and the depression (polypitting) of the gate structure.
[0071] From the above, it can be seen that in a method for forming a gate structure provided by an embodiment of the present invention, a first etching process is first performed to form a first opening pattern on a hard mask layer along a first direction, and the first opening pattern is used to form a gate structure; then a second etching process is performed to form a second opening pattern on the hard mask layer along a second direction, and the second opening pattern is used to cut the gate structure; then a third etching process is performed to remove the oxide layer in the hard mask layer; finally, a fourth etching process is performed to use the amorphous carbon layer in the hard mask layer as a mask to etch the polysilicon material layer to form a gate structure. The present invention uses a LELE process architecture and a technical solution of using an amorphous carbon layer and an oxide layer as a hard mask layer. The oxide layer in the hard mask layer effectively protects the amorphous carbon layer, and the LELE process architecture can well control the shape of the gate terminal, reducing the leakage problem of the gate structure, so that the minimum voltage of the SRAM can meet the standard.
[0072] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a gate structure, characterized in that: include: Providing a substrate, on which a polysilicon material layer and a hard mask layer are formed, wherein the hard mask layer includes an amorphous carbon layer and an oxide layer; Performing a first etching process to form a first opening pattern on the hard mask layer along a first direction, wherein the first opening pattern is used to form a gate structure; Performing a second etching process to form a second opening pattern on the hard mask layer along a second direction, wherein the second opening pattern is used to cut the gate structure, and the second direction is perpendicular to the first direction; Performing a third etching process to remove the oxide layer in the hard mask layer; A fourth etching process is performed to etch the polysilicon material layer using the amorphous carbon layer in the hard mask layer as a mask, and the first opening pattern and the second opening pattern in the hard mask layer are transferred to the polysilicon material layer to form a gate structure.
2. The method for forming a gate structure according to claim 1, wherein: Before performing the first etching process, the method includes: forming a first photoresist layer, wherein the first photoresist layer covers the oxide layer; A first exposure process is performed to form a patterned first photoresist layer, wherein the patterned first photoresist layer includes a first opening pattern, and the first opening pattern in the patterned first photoresist layer exposes the oxide layer in a first direction.
3. The method for forming a gate structure according to claim 2, wherein: After performing the first etching process, the patterned first photoresist layer is removed by a wet etching process.
4. The method for forming a gate structure according to claim 1, wherein: Before performing the second etching process, the method comprises: forming a second photoresist layer, wherein the second photoresist layer covers the oxide layer; A second exposure process is performed to form a patterned second photoresist layer, wherein the patterned second photoresist layer includes a second opening pattern, and the second opening pattern in the patterned second photoresist layer exposes the oxide layer in a second direction.
5. The method for forming a gate structure according to claim 4, wherein: After performing the second etching process, the patterned second photoresist layer is removed by a wet etching process.
6. The method for forming a gate structure according to claim 1, wherein: The first etching process, the second etching process and the fourth etching process are all dry etching processes, and the third etching process is a wet etching process.
7. The method for forming a gate structure according to claim 1, wherein: After forming the gate structure, the method comprises: Performing a linear oxidation process to form a linear oxide layer, wherein the linear oxide layer covers the amorphous carbon layer, the sidewall of the gate structure and the surface of the substrate, and the linear oxide layer on the sidewall of the gate structure constitutes a sidewall of the gate structure; A fifth etching process is performed to remove the amorphous carbon layer, and the sidewall of the gate structure protects the end shape of the gate structure.
8. The method for forming a gate structure according to claim 7, wherein: The fifth etching process is an oxidation stripping process.
9. A gate structure, characterized in that: The gate structure is prepared by the method for forming the gate structure as claimed in any one of claims 1 to 8.
10. A static random access memory, characterized in that: Comprising the gate structure as claimed in claim 9.