Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate which is provided with a first surface and a second surface, comprises an IGBT region and a diode region, and is internally provided with a drift region of a first conduction type; forming a diode anode of the second conductive type in the diode region; forming an oxide layer covering the anode of the diode on the first surface; forming a carrier injection barrier layer in the IGBT region; forming an active gate in the IGBT region; forming a body region of a second conductive type on the carrier injection barrier layer; and forming an emitter region of the first conduction type in the IGBT region. According to the invention, the oxide layer is formed on the diode anode and the carrier injection barrier layer is not formed, and when the contact hole is formed, the oxide layer is removed, so that no carrier injection barrier layer exists between the metal layer and the diode anode, the hole extraction speed during reverse recovery is accelerated, the reverse recovery loss is reduced, the number of masks is saved, and the production efficiency is improved. The production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In order to improve the power density of an insulated gate bipolar transistor (IGBT), the IGBT and a diode (eg, a fast recovery diode, FRD) may be integrated on a chip to form a reverse conducting IGBT (RCIGBT).

[0003] In the current related technology, for the RCIGBT integrated with FRD and IGBT, there is a problem of poor reverse recovery performance of FRD and IGBT. Since the optimization directions of IGBT and FRD are opposite, if the turn-on loss and reverse recovery loss are reduced by controlling the life of FRD, the turn-on loss of IGBT will be large. If the FRD anode concentration is optimized, more masks are required, resulting in increased costs. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, the present invention provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0006] Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the substrate comprising an IGBT region and a diode region, the diode region being located at a first side of the IGBT region, and a drift region of a first conductivity type being formed in the substrate;

[0007] forming a diode anode of a second conductivity type in the diode region, extending from the first surface into the drift region;

[0008] forming an oxide layer on the first surface to at least cover the anode of the diode;

[0009] forming a carrier injection blocking layer on a side of the drift region in the IGBT region close to the first surface;

[0010] forming an active gate in the IGBT region, the active gate extending from the first surface into the drift region and away from the second surface;

[0011] forming a body region of a second conductivity type on a side of the carrier injection blocking layer close to the first surface, so that at least a portion of the body region is located on the carrier injection blocking layer, wherein the body region is also located on both sides of the active gate;

[0012] An emitter region of a first conductivity type extending from the first surface into the body region is formed in the IGBT region, and the emitter region is located at both sides of the active gate.

[0013] In one embodiment, the substrate further includes a terminal region located at a second side of the IGBT region, and the manufacturing method further includes forming at least one well region of the second conductivity type in the terminal region while forming the second conductivity type diode anode.

[0014] In one embodiment, a field oxide layer is formed in the terminal region, and the field oxide layer in the terminal region is formed simultaneously with the oxide layer covering the anode of the diode.

[0015] In one embodiment, the manufacturing method further comprises:

[0016] forming an insulating layer covering the first surface and the oxide layer, and forming a contact hole and an opening exposing at least a portion of the surface of the diode anode in the insulating layer, wherein the contact hole penetrates the emitter region and exposes at least a portion of the body region;

[0017] A conductive connection structure electrically connected to the emitter region and the diode anode is formed, the conductive connection structure covers the insulating layer and fills the contact hole and the opening.

[0018] In one embodiment, the doping concentration of the diode anode is lower than the doping concentration of the body region.

[0019] In one embodiment, the manufacturing method further comprises:

[0020] forming a collector region of a second conductivity type extending from the second surface into the substrate in the IGBT region and the terminal region;

[0021] An electrode layer of the first conductivity type is formed in the diode region and extends from the second surface into the substrate.

[0022] Another aspect of the present application provides a semiconductor device, comprising:

[0023] A substrate having a first surface and a second surface opposite to each other, the substrate comprising an IGBT region and a diode region, the diode region being located at a first side of the IGBT region, and a drift region of a first conductivity type being formed in the substrate;

[0024] A diode anode of a second conductivity type is located in the diode region and extends from the first surface into the drift region and directly contacts the drift region;

[0025] A carrier injection blocking layer, located on a side of the drift region of the IGBT region close to the first surface;

[0026] An active gate, located in the IGBT region, the active gate extending from the first surface into the drift region and away from the second surface;

[0027] A body region of a second conductivity type, at least partially located on the carrier injection blocking layer, and the body region is located on both sides of the active gate;

[0028] An emitter region of a first conductivity type extends from the first surface into the body region.

[0029] In one embodiment, the substrate further includes a terminal region, the terminal region is located at the second side of the IGBT region, the terminal region includes at least one well region of the second conductivity type, and the well region and the diode anode have the same doping concentration.

[0030] In one embodiment, the semiconductor device further comprises:

[0031] an insulating layer covering a portion of the first surface, wherein a contact hole and an opening exposing at least a portion of the surface of the anode of the diode are formed in the insulating layer, wherein the contact hole penetrates the emitter region and exposes at least a portion of the body region;

[0032] A conductive connection structure is electrically connected to the emitter region and the diode anode, and the conductive connection structure covers the insulating layer and fills the contact hole and the opening.

[0033] In one embodiment, the semiconductor device further comprises:

[0034] A collector region of the second conductivity type, located in the IGBT region and the terminal region, and extending from the second surface into the substrate;

[0035] The electrode layer of the first conductive type is located in the diode region and extends from the second surface into the substrate.

[0036] The semiconductor device and manufacturing method of the embodiment of the present application, before the carrier injection blocking layer, blocks the injection into the diode region when the carrier injection blocking layer is formed by forming an oxide layer on the diode anode, so that the carrier injection blocking layer is not formed in the diode region, thereby accelerating the hole extraction speed during reverse recovery and reducing the reverse recovery loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0038] In the attached figure:

[0039] Figure 1 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown;

[0040] Figure 2A-2L A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0041] Next, the present invention will be more fully described in conjunction with the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0042] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0043] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present invention. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0047] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0048] IGBT devices are mainly developing towards higher cell density, larger wafer size, thinner chip thickness, that is, higher operating junction temperature. Currently, their performance is close to their theoretical limit. An important subsequent development trend of IGBT devices is towards multi-functional integration. For example, IGBT and diodes (such as freewheeling diodes FWD or fast recovery diodes FRD) are integrated on-chip to reduce power device costs and increase power density, forming RCIGBT.

[0049] RCIGBT forms a partial N+ region in the P+ collector region on the back of a conventional IGBT through one or two photolithography steps, thereby forming a PIN diode structure consisting of the P well, N-drift region, and N+ collector region on the front of the IGBT, i.e., a diode structure consisting of three parts: a P-type semiconductor, an intrinsic semiconductor (I-type, i.e., an undoped semiconductor), and an N-type semiconductor, forming a conductive channel from the emitter to the collector of the IGBT. RCIGBT increases the area of ​​a single chip, reduces thermal resistance, and increases power density.

[0050] In the current related technologies, for RCIGBT integrating FRD and IGBT, there is a problem of poor reverse recovery performance of FRD and IGBT. Since the optimization directions of IGBT and FRD are opposite, if the turn-on loss and reverse recovery loss are reduced by controlling the life of FRD, the turn-on loss of IGBT will be relatively large. If the FRD anode concentration is optimized, more masks are required, resulting in increased costs.

[0051] Therefore, in view of the existence of the above-mentioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as Figure 1 As shown, it mainly includes the following steps:

[0052] Step S110: providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other, the substrate comprises an IGBT region and a diode region, the diode region is located at a first side of the IGBT region, and a drift region having a first conductivity type is formed in the substrate;

[0053] Step S120: forming a diode anode of a second conductivity type extending from the first surface into the drift region in the diode region;

[0054] Step S130: forming an oxide layer on the first surface that at least covers the anode of the diode;

[0055] Step S140: forming a carrier injection blocking layer on a side of the drift region in the IGBT region close to the first surface;

[0056] Step S150: forming an active gate in the IGBT region, the active gate extending from the first surface into the drift region and away from the second surface;

[0057] Step S160: forming a body region of a second conductivity type on a side of the carrier injection blocking layer close to the first surface, so that at least a portion of the body region is located on the carrier injection blocking layer, wherein the body region is also located on both sides of the active gate;

[0058] Step S170: forming an emitter region of a first conductivity type extending from the first surface to the body region in the IGBT region, wherein the emitter region is located at two sides of the active gate.

[0059] In an embodiment of the present application, before the carrier injection blocking layer is formed, an oxide layer is formed on the diode anode to block the injection into the diode region when the carrier injection blocking layer is formed, so that the carrier injection blocking layer is not formed in the diode region, thereby accelerating the hole extraction speed during reverse recovery and reducing the reverse recovery loss.

[0060] Below, reference Figure 1 , Figures 2A to 2L The method for manufacturing a semiconductor device of the present invention is described in detail, wherein: Figure 1 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; Figure 2A-2L The cross-sectional schematic diagram of the semiconductor device obtained by sequentially implementing the method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. In the following description, N and P represent the conductivity type of the semiconductor. In the following description, the first conductivity type is set to N type and the second conductivity type is set to P type.

[0061] Embodiment 1

[0062] The method for manufacturing a semiconductor device of the present application comprises the following steps:

[0063] First, if Figure 1 As shown, step S110 is executed. Figure 2A As shown, a substrate 200 is provided, the substrate 200 has a first surface 201 and a second surface 202 relative to each other, and includes an IGBT region, a diode region and a terminal region in the substrate 200, the diode region is located on the first side of the IGBT region, the terminal region is located on the second side of the IGBT region, and a drift region with a first conductivity type is formed in the substrate, for example, a drift region of the first conductivity type is formed between the first surface 201 and the second surface 202.

[0064] Exemplarily, the substrate 200 may be any suitable semiconductor substrate, such as a silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or may be ceramic substrates such as alumina, quartz or glass substrates, etc.

[0065] Then, step S120 is performed. Figure 2B As shown, ions of the second conductivity type are injected into the terminal region and the diode region in the substrate 200 to form a second conductivity type diode anode 203 extending from the first surface 201 to the drift region in the substrate 200 in the diode region, and at least one second conductivity type well region 204 extending from the first surface 201 to the drift region is formed in the terminal region, and annealing is performed. It is worth mentioning that the second conductivity type well region 204 in the terminal region can be used as a guard ring of the terminal region to improve the withstand voltage performance of the IGBT structure. Exemplarily, a plurality of well regions 204 arranged at intervals can be formed.

[0066] Then, step S130 is performed. Figure 2C As shown, an oxide layer 205 covering at least the diode anode 203 is formed on the first surface 201. While forming the oxide layer 205, a field oxide layer is also formed in the terminal region, and the field oxide layer covers the first surface 201 between the well regions 204 in the terminal region. Exemplarily, the process of forming the field oxide layer and the oxide layer includes but is not limited to the Local Oxidation of Silicon (LOCOS) process. By synchronously forming the oxide layer 205 and the field oxide layer in the terminal region, when the subsequent carrier injection blocking layer and the body region are formed, there is no need to form an additional mask on the diode anode 203, thereby saving a mask plate, reducing costs and simplifying the process.

[0067] Then, step S140 is performed to form a carrier injection barrier layer 206 on one side of the drift region of the IGBT region close to the first surface 201. The carrier injection barrier layer 206 can increase the emitter carrier concentration in the IGBT working state, thereby reducing the on-state voltage drop. Exemplarily, the first conductive type of carrier injection barrier layer can be formed by deep ion injection and / or diffusion. Since an oxide layer is formed on the surface of the diode anode in the diode region, when the carrier injection barrier layer is formed in the IGBT region, the diode region will not form a carrier injection barrier layer. At this time, due to the presence of the oxide layer, there is no need to add a mask to prevent the formation of a carrier injection barrier layer on the diode region, thereby saving a mask.

[0068] Next, execute step S150, such as Figure 2E As shown, a patterned mask layer (not shown) is formed on the first surface 201 of the IGBT region of the substrate 200, and the patterned mask layer defines the position and size of the predetermined active gate trench 2071, and then the substrate 200 is etched from the first surface 201 to form the active gate trench 2071, the active gate trench 2071 is away from the second surface 202, and the active gate trench 2071 extends into the drift region. Exemplarily, the number of active gate trenches 2071 is at least one, and when there are multiple active gate trenches 2071, the multiple active gate trenches 2071 are spaced apart in a direction parallel to the first surface 201. Then, a gate dielectric layer (not shown) is formed on the inner surface of the active gate trench 2071, and the gate dielectric layer can be formed by any suitable method, for example, by chemical vapor deposition, physical vapor deposition or thermal oxidation. Optionally, the material of the gate dielectric layer may include silicon oxide or other suitable insulating materials.

[0069] Then, if Figure 2F As shown, a gate material layer (eg, a polysilicon layer) is deposited to fill the active gate trench 2071 to form an active gate 207 .

[0070] Then, step S160 is performed. Figure 2G As shown, a second conductivity type body region 208 is formed on one side of the carrier injection blocking layer 206 close to the first surface 201, and a second conductivity type body region 208 is also formed on part of the second conductivity type well region 204 in the terminal region. The body region 208 on the carrier injection blocking layer 206 is located on both sides of the active gate 207, and is annealed to obtain the following: Figure 2HThe structure shown. Similarly, since an oxide layer is formed on the surface of the diode anode of the diode region, when forming the body region of the second conductivity type, due to the presence of the oxide layer, no mask is added and no body region will be formed in the diode region, thereby saving one mask. In some examples, the doping concentration of the diode anode is lower than the doping concentration of the body region, that is, the doping concentration injected when forming the well region of the second conductivity type in the terminal region and forming the diode anode of the second conductivity type is lower than the doping concentration of the body region of the second conductivity type. Therefore, it can be considered that when forming the well region of the second conductivity type and the diode anode of the second conductivity type, low-concentration conductive ion implantation is used, thereby reducing the concentration of the diode anode to further reduce reverse recovery loss.

[0071] Next, execute step S170, such as Fig.2I As shown, a dopant of the first conductivity type is implanted and / or diffused on the first surface 201 where the IGBT region is located to form an emitter region 209 of the first conductivity type extending from the first surface 201 to the body region 208, and the emitter region 209 is located at one end of the body region 208 close to the active gate 207. The emitter region 209 of the first conductivity type is also referred to as a source region of the first conductivity type. Exemplarily, the body region of the second conductivity type of the terminal region is not implanted with a dopant of the first conductivity type, so that no emitter region is formed.

[0072] Then, if Figure 2J As shown, an insulating layer 210 is formed on the first surface 201 of the substrate 200 to cover the first surface 201, and a patterned mask layer (not shown) is formed on the insulating layer 210, the patterned mask layer defines the position and size of the predetermined contact hole 211 and the position and size of the diode anode 203, and then the substrate 200 is etched from the first surface 201 to form a contact hole 211 in the insulating layer 210, the contact hole 211 passes through the emitter region 209 and exposes at least a portion of the body region 208, and at the same time, at least a portion of the oxide layer 205 on the diode anode 203 is removed to form an opening exposing at least a portion of the surface of the diode anode 203, the contact hole in the insulating layer enables the emitter region to be electrically connected to the emitter region metal layer (that is, the metal layer in the electrical connection structure 212) to realize the electrical function of the semiconductor device.

[0073] Then, if Figure 2KAs shown, a conductive connection structure 212 is formed on the insulating layer 210, the first surface 201 on the diode anode 203, and the contact hole 211. The conductive connection structure includes a conductive plug formed after filling the contact hole 211, an emitter metal layer in the IGBT region, and a metal layer on the diode anode 203. The conductive plug is electrically connected to the emitter metal layer. Since the emitter region 209 is on the side of the body region 208 close to the first surface 201, the conductive plug can electrically connect the body region 208 and the emitter region 209 to the emitter metal layer to achieve the electrical function of the semiconductor device. The metal layer on the diode anode 203 is electrically connected to the diode anode. In some examples, a through hole exposing at least a portion of the surface of the well region 204 is also formed in the insulating layer 210, and the electrical connection structure is also in contact with the well region 204 and electrically connected.

[0074] Then, if Figure 2L As shown, the second surface 202 of the substrate 200 is thinned, and then the second conductive type ion implantation is performed in the IGBT region and the terminal region to form a collector region 213 of the second conductive type extending from the thinned second surface 202 to the substrate 200; the first conductive type ion implantation is performed in the diode region to form an electrode layer 214 of the first conductive type extending from the thinned second surface 202 to the substrate 200, and the position where the collector region 213 and the electrode layer 214 contact can be considered as the boundary position between the IGBT region and the diode region. Exemplarily, the collector region 213 and the electrode layer 214 have the same thickness, and the thickness direction is also the arrangement direction of the first surface and the second surface. Then, metal covering is performed on the side of the collector region 213 and the electrode layer 214 away from the first surface of the substrate 200 (that is, on the second surface of the substrate 200) to form a collector metal layer, so as to form a collector in the IGBT region and a diode cathode in the diode region.

[0075] So far, the description of the key steps of the method for manufacturing a semiconductor device of the present invention has been completed. The complete method for manufacturing a semiconductor device may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0076] In summary, the manufacturing method of the embodiment of the present application forms an oxide layer on the diode anode and does not form a carrier injection blocking layer on the diode anode. When forming a contact hole, the oxide layer is removed so that there is no carrier injection blocking layer between the metal layer and the diode anode, thereby accelerating the hole extraction speed during reverse recovery and reducing the reverse recovery loss. In addition, a lower doping concentration than the body region is used to inject the substrate to form the diode anode, so that the concentration of the diode anode is reduced, further reducing the reverse recovery loss. At the same time, since the oxide layer is formed before the carrier injection blocking layer is formed, and the oxide layer is removed simultaneously when the contact hole is formed, the oxide layer in the diode region can prevent the carrier injection blocking layer and the body region from being formed in the diode region when the carrier injection blocking layer and the body region are formed, thereby saving the number of masks and reducing production costs.

[0077] Embodiment 2

[0078] The present invention further provides a semiconductor device, which can be manufactured by the method for manufacturing the semiconductor device in the above-mentioned embodiment 1. Some details of this embodiment can be referred to the relevant description of the method in the above text, and will not be repeated here.

[0079] Specifically, Figure 2LAs shown, the semiconductor device includes: a substrate 200, a diode anode 203 of the second conductivity type, a carrier injection blocking layer 206, an active gate 207, a body region 208 of the second conductivity type, an emitter region 209 of the first conductivity type, an insulating layer 210 and a conductive connection structure 212. The substrate 200 has a first surface 201 and a second surface 202 opposite to each other, and a drift region of the first conductivity type is arranged between the first surface 201 and the second surface 202. The substrate 200 includes a terminal region, an IGBT region and a diode region, wherein the terminal region includes at least one well region 204 of the second conductivity type, the diode region is located on the first side of the IGBT region, and the terminal region is located on the second side of the IGBT region; the diode anode 203 is located in the diode region, the carrier injection blocking layer 206 and the active gate 207 are both located in the IGBT region, the carrier injection blocking layer 206 is on the side of the drift region close to the first surface 201, the diode anode 203 and the active gate 207 both extend from the first surface 201 into the drift region, and the active gate 207 is located on the second side of the IGBT region; The gate 207 is away from the second surface 202, and the diode anode 203 is in direct contact with the drift region; the body region 208 is located on the carrier injection blocking layer 206 and between the well region 204 of the terminal region, and the body region 208 on the carrier injection blocking layer is located on both sides of the active gate 207; the emitter region 209 is located on the body region and extends from the first surface 201 to the body region 208; the insulating layer 210 is located on the first surface 201 and covers the first surface 201, and a contact hole and an opening exposing at least part of the surface of the diode anode 203 are formed in the insulating layer 210. The conductive connection structure 212 covers the insulating layer 210 and fills the contact hole and the opening, thereby achieving electrical connection with the emitter region 209 and the diode anode 203.

[0080] In some embodiments, the doping concentration of the diode anode is lower than the doping concentration of the body region.

[0081] In some embodiments, continuing as Figure 2L As shown, the semiconductor device further includes a collector region 213 of the second conductivity type and an electrode layer 214 of the first conductivity type, the collector region 213 of the second conductivity type is located in the IGBT region and the terminal region, the electrode layer 214 of the first conductivity type is located in the diode region, and both the collector region 213 and the electrode layer 214 extend from the second surface 202 into the substrate. A collector metal layer is also covered on the side of the collector region 213 and the electrode layer 214 facing away from the first surface of the substrate 200 (i.e., on the second surface of the substrate 200) to form a collector in the IGBT region and a diode cathode in the diode region.

[0082] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed in the present invention. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the substrate comprising an IGBT region and a diode region, the diode region being located at a first side of the IGBT region, and a drift region of a first conductivity type being formed in the substrate; forming a diode anode of a second conductivity type in the diode region, extending from the first surface into the drift region; forming an oxide layer on the first surface to at least cover the anode of the diode; forming a carrier injection blocking layer on a side of the drift region in the IGBT region close to the first surface; forming an active gate in the IGBT region, the active gate extending from the first surface into the drift region and away from the second surface; forming a body region of a second conductivity type on a side of the carrier injection blocking layer close to the first surface, so that at least a portion of the body region is located on the carrier injection blocking layer, wherein the body region is also located on both sides of the active gate; An emitter region of a first conductivity type extending from the first surface into the body region is formed in the IGBT region, and the emitter region is located at both sides of the active gate.

2. The manufacturing method according to claim 1, characterized in that The substrate further includes a terminal region, the terminal region is located at a second side of the IGBT region, and the manufacturing method further includes forming at least one well region of the second conductivity type in the terminal region while forming the anode of the diode of the second conductivity type.

3. The manufacturing method according to claim 2, characterized in that: A field oxide layer is formed in the terminal region, and the field oxide layer in the terminal region is formed simultaneously with the oxide layer covering the anode of the diode.

4. The manufacturing method according to claim 1, characterized in that: The manufacturing method further comprises: forming an insulating layer covering the first surface and the oxide layer, and forming a contact hole and an opening exposing at least a portion of the surface of the diode anode in the insulating layer, wherein the contact hole penetrates the emitter region and exposes at least a portion of the body region; A conductive connection structure electrically connected to the emitter region and the diode anode is formed, the conductive connection structure covers the insulating layer and fills the contact hole and the opening.

5. The manufacturing method according to claim 1, characterized in that: The doping concentration of the diode anode is lower than the doping concentration of the body region.

6. The manufacturing method according to claim 2, characterized in that: The manufacturing method further comprises: forming a collector region of a second conductivity type extending from the second surface into the substrate in the IGBT region and the terminal region; An electrode layer of the first conductivity type is formed in the diode region and extends from the second surface into the substrate.

7. A semiconductor device, characterized in that: include: A substrate having a first surface and a second surface opposite to each other, the substrate comprising an IGBT region and a diode region, the diode region being located at a first side of the IGBT region, and a drift region of a first conductivity type being formed in the substrate; A diode anode of a second conductivity type is located in the diode region and extends from the first surface into the drift region and directly contacts the drift region; A carrier injection blocking layer, located on a side of the drift region in the IGBT region close to the first surface; An active gate, located in the IGBT region, the active gate extending from the first surface into the drift region and away from the second surface; A body region of a second conductivity type, at least partially located on the carrier injection blocking layer, and the body region is located on both sides of the active gate; An emitter region of a first conductivity type extends from the first surface into the body region.

8. The semiconductor device according to claim 7, wherein: The substrate further includes a terminal region, the terminal region is located at the second side of the IGBT region, the terminal region includes at least one well region of the second conductivity type, and the well region and the diode anode have the same doping concentration.

9. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises: an insulating layer covering a portion of the first surface, wherein a contact hole and an opening exposing at least a portion of the surface of the anode of the diode are formed in the insulating layer, wherein the contact hole penetrates the emitter region and exposes at least a portion of the body region; A conductive connection structure is electrically connected to the emitter region and the diode anode, and the conductive connection structure covers the insulating layer and fills the contact hole and the opening.

10. The semiconductor device according to claim 8, wherein The semiconductor device further comprises: A collector region of the second conductivity type, located in the IGBT region and the terminal region, and extending from the second surface into the substrate; The electrode layer of the first conductive type is located in the diode region and extends from the second surface into the substrate.

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