Method and device for reducing RAM frequency in FIFO, terminal and medium

Abstract

The invention provides a method and a device for reducing RAM (Random Access Memory) frequency in FIFO (First In First Out), a terminal and a medium. The method comprises the following steps: caching wdata into a register reg0 and a register reg1 by using ping-pong operation; the cache data in the register reg0 and the register reg1 are spliced at the rising edge of the slow clock frequency to obtain spliced data with the data bit width being two times of the wdata data, and the spliced data are stored in a register regslowin; and the spliced data in the register (regslowin) is stored in the FIFO Memory (First In First Out Memory). According to the method and device for reducing the RAM frequency in the FIFO, the terminal and the medium, ping-pong buffering can be carried out in a fast clock domain, data splicing is carried out in a slow clock domain, the data are stored in the FIFO, and the problem that the FIFO design rate is not matched with the RAM rate is ingeniously solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital circuits, and in particular relates to a method, a device, a terminal and a medium for reducing the frequency of a RAM in a FIFO. Background Art

[0002] With the rapid development of the information age, the speed of data transmission and processing is constantly improving. FIFO (First In First Out) as a data structure provides an efficient and reliable mechanism for solving data flow management and synchronization problems. It is often used in data buffering and multi-bit signal cross-clock domain processing. For example, in a sensor data acquisition system, the sensor may collect data at a high rate, while the data processing unit may not be able to process the data in real time. At this time, FIFO can temporarily store data to ensure data integrity and real-time performance.

[0003] In digital system design, the combination of FIFO and RAM (Random Access Memory) provides a powerful data management solution and buffer mechanism, but it also faces the problem of RAM rate limitation. FIFO can access data at a higher rate than RAM. If the RAM rate is not enough to match the FIFO design rate, it will cause a bottleneck in system data transmission, resulting in problems such as FIFO overflow, data loss and delay, which will affect the overall performance and reliability of the system.

[0004] To solve the above problems, Texas Instruments proposed a fast FIFO storage system solution, which is implemented using slower storage units but can run at nearly three times the write and read frequency of existing RAM. The system mainly consists of RAM blocks, ring counters, and small FIFO storage units associated with RAM blocks, etc., and adopts a dual storage mechanism and dynamic data management. When the RAM read time is insufficient, data can be quickly transferred from the FIFO; when the FIFO is full, additional data is stored in the slower RAM, which acts as a buffer when the FIFO cannot receive more data. Once the FIFO is not full, the data is transferred from the RAM back to the FIFO, and the storage system runs at the speed of the FIFO again. The above solution uses 4 RAM blocks, increases hardware resources, and is more expensive. The dual storage mechanism makes the design more complicated and it becomes difficult to maintain efficient data transmission and storage as the system scales up. Summary of the invention

[0005] In view of this, the present invention aims to propose a method, device, terminal and medium for reducing RAM frequency in FIFO to solve the problem that FIFO design rate and RAM bandwidth are limited, affecting data transmission and storage efficiency.

[0006] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0007] In a first aspect, an embodiment of the present invention provides a method for reducing a RAM frequency in a FIFO, comprising:

[0008] After obtaining wdata data from an upstream module, as well as the bit width and clock frequency of the wdata data, and obtaining the highest supported clock frequency of the RAM, the clock frequency of the wdata data is compared with the highest supported clock frequency of the RAM to obtain a comparison result;

[0009] According to the comparison result, the wdata data is cached in register reg0 and register reg1 in a preset order by using a ping-pong operation; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data;

[0010] The cached data in the register reg0 and the register reg1 are spliced ​​at the rising edge of the slow clock frequency to obtain spliced ​​data with a data width twice that of the wdata data, and the spliced ​​data is stored in the register reg_slow_in; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock;

[0011] At the slow clock frequency, storing the spliced ​​data in the register reg_slow_in into the FIFO Memory;

[0012] When the subsequent module is used to read the spliced ​​data in the FIFO Memory, the spliced ​​data in the FIFO Memory is first stored in the register reg_slow_out at the slow clock frequency, and then the ping-pong operation is used to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFO Memory is read empty, the cached data in the register reg0 or the register reg1 is output as data_out according to the preset order, so that the external interface timing meets the standard FIFO logic.

[0013] Further, after obtaining the wdata data from the upstream module, the bit width and clock frequency of the wdata data, and obtaining the highest supported clock frequency of the RAM, the wdata data clock frequency is compared with the highest supported clock frequency of the RAM to obtain a comparison result, including:

[0014] Get the wdata data from the upstream module, as well as the bit width and clock frequency of the wdata data, and get the highest supported clock frequency of the RAM;

[0015] The wdata data clock frequency is compared with the highest supported clock frequency of the RAM to obtain a comparison result; wherein the comparison result includes two results, one result is that the wdata data clock frequency is not greater than the highest supported clock frequency of the RAM, and the other result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM.

[0016] Further, the step of caching the wdata data into register reg0 and register reg1 in a preset order by using a ping-pong operation according to the comparison result includes:

[0017] When the comparison result is that the clock frequency of the wdata data is not greater than the highest supported clock frequency of the RAM, the wdata data is directly stored in the FIFO Memory for direct reading by subsequent modules;

[0018] When the comparison result is that the clock frequency of the wdata data is greater than the highest supported clock frequency of the RAM, the wdata data is first stored in register reg0 and then in register reg1 using a ping-pong operation; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

[0019] Further, the step of splicing the cached data in the register reg0 and the register reg1 at the rising edge of the slow clock frequency to obtain spliced ​​data having a data width twice that of the wdata data, and storing the spliced ​​data in the register reg_slow_in includes:

[0020] After the data is stored in the register reg1, the cached data in the register reg0 and the register reg1 are spliced ​​at the rising edge of the slow clock frequency, the cached data in the register reg0 is placed in the low position, and the cached data in the register reg1 is placed in the high position, so as to obtain spliced ​​data with a data width twice that of the wdata data; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock;

[0021] At the slow clock frequency, the spliced ​​data is stored in the register reg_slow_in.

[0022] Further, when the subsequent module is used to read the spliced ​​data in the FIFO Memory, the spliced ​​data in the FIFO Memory is first stored in the register reg_slow_out at the slow clock frequency, and then the ping-pong operation is used to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFOMemory is read empty, the cached data in the register reg0 or the register reg1 is output as data_out according to the preset sequence, so that the external interface timing meets the standard FIFO logic, including:

[0023] When the subsequent module reads that the FIFO Memory is empty, if there is cached data in the register reg0, the cached data in the register reg0 is directly output as data_out at a fast clock frequency, otherwise it is not output; wherein the fast clock frequency is the same as the clock frequency corresponding to the wdata data;

[0024] When a subsequent module reads the spliced ​​data in the FIFO Memory, the spliced ​​data in the FIFO Memory is stored in a register reg_slow_out at the slow clock frequency;

[0025] Splitting the data in the register reg_slow_out to obtain high-order data and low-order data;

[0026] At the fast clock frequency, the low-order data is written into register reg2, and the high-order data is written into register reg3;

[0027] Data is selected from the register reg2 and the register reg3 through the mux logic as data_out for output, and the low-order data in the register reg2 is output first, and then the high-order data in the register reg3 is output.

[0028] In a second aspect, the present invention further provides a device for reducing RAM frequency in a FIFO, comprising:

[0029] A comparison module is used to obtain wdata data from an upstream module, as well as a bit width and a clock frequency of the wdata data, and after obtaining the highest supported clock frequency of the RAM, compare the clock frequency of the wdata data with the highest supported clock frequency of the RAM to obtain a comparison result;

[0030] An operation module, configured to cache the wdata data in registers reg0 and reg1 in a preset order by using a ping-pong operation according to the comparison result; wherein the bit widths of registers reg0 and reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in registers reg0 and reg1 are the same as the clock frequencies corresponding to the wdata data;

[0031] A splicing module, used for completing the splicing of the cached data in the register reg0 and the register reg1 at the rising edge of the slow clock frequency to obtain spliced ​​data with a data width twice that of the wdata data, and storing the spliced ​​data in the register reg_slow_in; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock;

[0032] A storage module, used for storing the spliced ​​data in the register reg_slow_in into the FIFO Memory at the slow clock frequency;

[0033] The splitting module is used to store the spliced ​​data in the FIFO Memory into the register reg_slow_out at the slow clock frequency when the subsequent module reads the spliced ​​data in the FIFO Memory, and then use the ping-pong operation to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFOMemory is read empty, the cached data in the register reg0 or the register reg1 is output as data_out according to the preset order, so that the external interface timing meets the standard FIFO logic.

[0034] Furthermore, the comparison module includes:

[0035] An acquisition unit, used to acquire wdata data from an upstream module, as well as the bit width and clock frequency of the wdata data, and to acquire the highest supported clock frequency of the RAM;

[0036] A comparison unit is used to compare the wdata data clock frequency with the highest supported clock frequency of the RAM to obtain a comparison result; wherein the comparison result includes two results, one result is that the wdata data clock frequency is not greater than the highest supported clock frequency of the RAM, and the other result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM.

[0037] Furthermore, the operation module includes:

[0038] A direct storage unit, used for directly storing the wdata data into the FIFO Memory when the comparison result shows that the clock frequency of the wdata data is not greater than the highest supported clock frequency of the RAM, so as to be directly read by subsequent modules;

[0039] A ping-pong unit is used to use a ping-pong operation to first store the wdata data into register reg0 and then into register reg1 when the comparison result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

[0040] In a third aspect, the present invention further provides a computing terminal, comprising:

[0041] one or more processors;

[0042] A storage device for storing one or more programs;

[0043] When the one or more programs are executed by the one or more processors, the one or more processors implement the method of reducing the RAM frequency in the FIFO as described above.

[0044] In a fourth aspect, the present invention further provides a storage medium comprising computer executable instructions, which, when executed by a computer processor, are used to perform the method of reducing the RAM frequency in the FIFO as described above.

[0045] In a fifth aspect, an embodiment of the present invention further provides a computer product, including a computer program, which, when executed by a processor, implements the above-mentioned method of reducing the RAM frequency in the FIFO.

[0046] Compared with the prior art, the method, device, terminal and medium for reducing RAM frequency in FIFO described in the present invention have the following advantages:

[0047] The method, device, terminal and medium for reducing the RAM frequency in FIFO described in the present invention can perform ping-pong buffering in a fast clock domain, and perform data splicing and storage in FIFO in a slow clock domain, which can cleverly solve the problem of mismatch between FIFO design rate and RAM rate, reduce the FIFO Memory frequency, and keep the total amount of data received per unit time unchanged, taking into account performance. At the same time, by using registers to complete ping-pong buffering and realize data splicing and splitting, the design is relatively simple and the cost is low. In addition, when the subsequent module reads that the FIFO Memory is empty, data pass-through can also be used to reduce system cavitation, and the utilization rate is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0049] Figure 1 A flow chart of a method for reducing RAM frequency in FIFO according to Embodiment 1 of the present invention;

[0050] Figure 2 A schematic diagram of a process of data splicing in reducing RAM frequency in FIFO according to Embodiment 1 of the present invention;

[0051] Figure 3 A timing diagram of data writing in reducing RAM frequency in FIFO according to the first embodiment of the present invention;

[0052] Figure 4 A timing diagram of data reading in reducing RAM frequency in FIFO according to the first embodiment of the present invention;

[0053] Figure 5 A schematic diagram of the structure of a device for reducing RAM frequency in a FIFO according to a second embodiment of the present invention;

[0054] Figure 6 A schematic diagram of the structure of a computing terminal provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0056] Embodiment 1

[0057] Figure 1 This is a flow chart of a method for reducing RAM frequency in FIFO according to Embodiment 1 of the present invention. This embodiment can be applied to data transmission in digital circuits, see Figure 1 , this method specifically includes the following steps:

[0058] Step 101, after obtaining wdata data from an upstream module, as well as the bit width and clock frequency of the wdata data, and obtaining the highest supported clock frequency of the RAM, the wdata data clock frequency is compared with the highest supported clock frequency of the RAM to obtain a comparison result.

[0059] Since RAM-based FIFO design is a commonly used buffering mechanism in digital circuit design, it also has certain limitations. For example, FIFO design requires high-speed data transmission, but the RAM rate cannot match the FIFO design rate. This situation will lead to data loss, FIFO overflow, processing delays, metastability, resource waste and other problems, greatly limiting the system's data throughput and reliability.

[0060] The main solutions and limitations of the existing technologies are as follows: 1. Use faster RAM or increase RAM resources: Increase bandwidth by upgrading the RAM rate and using larger RAM to match the design rate of the FIFO. Disadvantages: high cost, requires more hardware resources, and complex design. 2. Implement a dynamic rate and flow control mechanism: Improve resource utilization by dynamically modulating the rate and flow to prevent exceeding the RAM bandwidth limit. Disadvantages: Difficult to implement, and the real-time performance of the system may be affected. 3. Add additional buffers: Add additional buffers between RAM and FIFO to smooth out the peaks of data transmission rates and reduce time loss caused by waiting for RAM operations to complete. Disadvantages: Increase hardware costs and complex design. 4. Optimize data access patterns: Adjust data access patterns, such as using more efficient data packaging or batch processing techniques. Disadvantages: Limited optimization space, targeted at specific applications.

[0061] Therefore, in order to solve the problems existing in the existing solutions, this embodiment proposes a FIFO frequency reduction technology to match the rate limit of the RAM. The core is to reduce the FIFO frequency without sacrificing data throughput. By obtaining the wdata data of the upstream module, as well as the bit width and clock frequency of the wdata data, and comparing them with the highest supported clock frequency of the RAM, a comparison result can be obtained to determine whether the clock frequency of the RAM can meet the transmission requirements of the wdata data, and then subsequent processing can be performed with higher efficiency.

[0062] Specifically, step 101 may include the following steps:

[0063] Step 1011: Obtain wdata data from an upstream module, as well as the bit width and clock frequency of the wdata data, and obtain the highest supported clock frequency of the RAM.

[0064] Step 1012: compare the wdata data clock frequency with the highest supported clock frequency of the RAM to obtain a comparison result; wherein the comparison result includes two results, one result is that the wdata data clock frequency is not greater than the highest supported clock frequency of the RAM, and the other result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM.

[0065] In actual application, FIFO Memory is equivalent to the RAM mentioned below, and will not be described in detail later. Assume that the wdata data bit width from the upstream module is 100, the clock frequency is 1GHz, and the RAM only supports up to 500MHz. At this time, it is necessary to use registers to ping-pong cache the write data from the upstream module, and splice the data in the register before reading the RAM, and then split the data when it is read from the RAM. Conversely, assuming that the wdata data bit width from the upstream module is 100, the clock frequency is 500MHz, and the RAM also supports up to 500MHz, then there is no need to ping-pong cache the write data at this time, it can be directly stored in the RAM, and the subsequent data does not need to be split after being read from the RAM. This solution does not require additional hardware resources, is simple in design, low in cost, and easy to implement.

[0066] Step 102: Based on the comparison result, the wdata data is cached in register reg0 and register reg1 in sequence using a ping-pong operation; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

[0067] Exemplarily, in this embodiment, register reg0 and register reg1 are inserted before FIFO, and the wdata data from the upstream module is cached in register reg0[99:0] and register reg1[99:0] in sequence through ping-pong operation, and the clock frequency of the cached data is 1G_clk. Specifically, the wdata data is written to register reg0[99:0] and register reg1[99:0] at the rising edge of 1G_clk. The preset order given in this embodiment is to store it in register reg0 first and then in register reg1. When the data is directly output through data_out later, the data in register reg0 first stored is also output. Those skilled in the art can also adjust the sequence according to actual needs, for example, first store it in register reg1 and then store it in register reg0, which is the same as the principle given in this embodiment, so it will not be repeated here.

[0068] Specifically, in this embodiment, the preset sequence is to first store data in register reg0 and then store data in register reg1. Step 102 may specifically include the following steps:

[0069] Step 1021: When the comparison result is that the clock frequency of the wdata data is not greater than the highest supported clock frequency of the RAM, the wdata data is directly stored in the FIFO Memory for direct reading by subsequent modules.

[0070] Step 1022, when the comparison result is that the clock frequency of the wdata data is greater than the highest supported clock frequency of the RAM, the wdata data is first stored in register reg0 and then in register reg1 using a ping-pong operation; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

[0071] In actual application, register reg0 and register reg1 are both 100-bit registers, which can be represented as reg0[99:0] and reg1[99:0] respectively. By using two 100-bit registers, the ping-pong buffer is written into RAM after reaching 200 bits. It should be pointed out that 100 bits and 200 bits are just examples, that is, the register width is half of the RAM width. By adopting the above settings, only the two registers need to be recycled. After the register data is written into RAM, it can be used to cache new data, which is conducive to reducing the use of hardware resources and reducing the complexity of the design.

[0072] Step 103, complete the splicing of the cached data in the register reg0 and the register reg1 at the rising edge of the slow clock frequency to obtain spliced ​​data with a data bit width twice that of the wdata data, and store the spliced ​​data in the register reg_slow_in; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock.

[0073] Specifically, step 103 may include the following steps:

[0074] Step 1031, after the data is stored in the register reg1, the cached data in the register reg0 and the register reg1 are spliced ​​at the rising edge of the slow clock frequency, the cached data in the register reg0 is placed in the low position, and the cached data in the register reg1 is placed in the high position, to obtain spliced ​​data with a data width twice that of the wdata data; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock. Exemplarily, the slow clock frequency is 500M_clk, which is obtained by clock division of the clock frequency corresponding to the wdata data, 1G_clk, and the two are the same source clock.

[0075] Step 1032: Store the spliced ​​data into register reg_slow_in at the slow clock frequency.

[0076] Step 104: Store the spliced ​​data in the register reg_slow_in into the FIFO Memory at the slow clock frequency.

[0077] Step 105, when using the subsequent module to read the spliced ​​data in the FIFO Memory, first store the spliced ​​data in the FIFO Memory into the register reg_slow_out at the slow clock frequency, and then use the ping-pong operation to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFO Memory is read empty, the cached data in the register reg0 or the register reg1 is used as data_out for data direct output according to the preset order, so that the external interface timing meets the standard FIFO logic.

[0078] In actual application, register reg_slow_in and register reg_slow_out both use 200-bit registers, which can be represented as reg_slow_in[199:0] and reg_slow_out[199:0] respectively.

[0079] Specifically, step 105 may include the following steps:

[0080] Step 1051, when the subsequent module reads that the FIFO Memory is empty, if there is cached data in the register reg0, the cached data in the register reg0 is output as data_out at a fast clock frequency, otherwise it is not output; wherein the fast clock frequency is the same as the clock frequency corresponding to the wdata data. It should be noted that, assuming that the wdata data may have a difference between odd and even numbers, when it is an even number, the wdata data can be split, and when it is an odd number, the split wdata data will remain in the register reg0. In order to avoid data loss, the cached data in the register reg0 is output as data_out at a fast clock frequency through data direct output, which can ensure the integrity of the data.

[0081] Step 1052, when the subsequent module reads the spliced ​​data in the FIFO Memory, the spliced ​​data in the FIFO Memory is stored in the register reg_slow_out at the slow clock frequency. The data in the register reg_slow_out is then split to obtain high-order data and low-order data. Then, at the fast clock frequency, the low-order data is written into the register reg2, and the high-order data is written into the register reg3; wherein the fast clock frequency is the same as the clock frequency corresponding to the wdata data. Finally, data is selected from the register reg2 and the register reg3 through the mux logic as data_out for output, and the low-order data in the register reg2 is output first, and then the high-order data in the register reg3 is output. It should be noted that the order of registers reg2 and reg3 can also be adjusted according to actual needs, which is the same as the order of registers reg0 and reg1, and will not be repeated here.

[0082] Figure 2 This is a flow chart of data splicing in reducing RAM frequency in FIFO according to Embodiment 1 of the present invention. Figure 2 Assuming that the width (i.e., bit width) of the FIFO Memory is W, the depth is H, and the read / write clock frequency is F, when the highest supported clock frequency of a general RAM meets the data transmission requirements, a RAM (i.e., a FIFO Memory) with a width of W and a depth of H is directly used to store data at a clock frequency of F. When the highest supported clock frequency of the RAM does not meet the data transmission requirements, a RAM with a width of 2*W and a depth of H / 2 can be used as in this embodiment to store data at a clock frequency of F / 2, so that the operating frequency of the FIFO Memory is reduced by half.

[0083] Figure 3 This is a timing diagram of data splicing in reducing RAM frequency in FIFO according to the first embodiment of the present invention. Figure 3 , this embodiment implements data writing through the following process:

[0084] 1. Register reg0[99:0] and register reg1[99:0] are inserted before FIFO Memory. The wdata data from the upstream module is cached to register reg0[99:0] and register reg1[99:0] in the 1Ghz clock domain through ping-pong operation, and the data is first stored in register reg0[99:0] and then in register reg1[99:0].

[0085] 2. After the data is stored in register reg1[99:0], register reg0[99:0] and register reg1[99:0] are spliced ​​into 200-bit spliced ​​data. Register reg0[99:0] is placed in the lower 100 bits, and register reg1[99:0] is placed in the upper 100 bits. At a clock frequency of 500M_clk, the spliced ​​data is written to reg_slow_in[199:0]. After that, register reg0[99:0] and register reg1[99:0] can both re-cache data in the 1G_clk domain. The data is also first stored in register reg0[99:0] and then in register reg1[99:0].

[0086] 3. Then write the data of register reg_slow_in[199:0] into FIFO Memory in the 500M clock domain.

[0087] Figure 4 This is a timing diagram of data readout in a method of reducing RAM frequency in FIFO according to the first embodiment of the present invention. Figure 4 , this embodiment realizes data reading through the following process:

[0088] 1. Insert register reg_slow_out[199:0] after FIFO Memory and read the data in FIFO Memory into register reg_slow_out[199:0] at 500M_clk clock frequency.

[0089] 2. Divide the 200-bit data of register reg_slow_out[199:0] into two 100-bit high and low parts, and write them into register reg2[99:0] and register reg3[99:0] in a ping-pong manner at a clock frequency of 1G_clk. The low 100 bits are stored in register reg2[99:0] and the high 100 bits are stored in register reg3[99:0]. After the data in register reg_slow_out[199:0] is written into register reg2[99:0] and register reg3[99:0], register reg_slow_out[199:0] can continue to read new data in FIFO Memory at a clock frequency of 500M_clk. Among them, register reg2[99:0] and register reg3[99:0] are both 100-bit registers.

[0090] 3. The mux (data selector) logic ping-pongs the data from register reg2[99:0] and register reg3[99:0] as the final data_out. Similarly, register reg2[99:0] is output first, and then register reg3[99:0].

[0091] 4. When the FIFO Memory is empty, if there is data in the entry register reg0[99:0], the register reg0[99:0] that stores the data first can be directly output through data_out, so that the FIFO Memory can be completely emptied. By adopting the above process, the actual data cache requirements can be better met and the data transmission stability can be improved.

[0092] This embodiment adopts the above processing process. When data is written, since 500M_clk and 1G_clk are the same source clocks, the registers in the high and low frequency clock domains can sample each other. Therefore, the register reg_slow_in is used to complete the conversion from high frequency to low frequency when data is written, and the register reg_slow_out is used to complete the conversion from low frequency to high frequency when data is output.

[0093] The method for reducing the RAM frequency in the FIFO described in this embodiment obtains the wdata data from the upstream module, the bit width and clock frequency of the wdata data, and obtains the highest supported clock frequency of the RAM, and then compares the clock frequency of the wdata data with the highest supported clock frequency of the RAM to obtain a comparison result. Afterwards, according to the comparison result, the wdata data is cached in registers reg0 and reg1 in a preset order using a ping-pong operation; wherein the bit widths of registers reg0 and reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in registers reg0 and reg1 are the same as the clock frequencies corresponding to the wdata data. Then, the cached data in registers reg0 and reg1 are spliced ​​at the rising edge of the slow clock frequency to obtain spliced ​​data with a data bit width twice that of the wdata data, and the spliced ​​data is stored in register reg_slow_in; wherein the slow clock frequency is the clock frequency corresponding to the wdata data obtained by clock division, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock. Then, at the slow clock frequency, the spliced ​​data in the register reg_slow_in is stored in the FIFO Memory. Finally, when the spliced ​​data in the FIFO Memory is read by the subsequent module, the spliced ​​data in the FIFO Memory is first stored in the register reg_slow_out at the slow clock frequency, and then the ping-pong operation is used to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFO Memory is read empty, the cached data in the register reg0 or the register reg1 is output as data_out according to the preset order, so that the external interface timing meets the standard FIFO logic.

[0094] Compared with the prior art, the method for reducing the RAM frequency in the FIFO described in this embodiment can perform ping-pong buffering in a fast clock domain, and perform data splicing and storage in the FIFO in a slow clock domain, which cleverly solves the problem of mismatch between the FIFO design rate and the RAM rate, and reduces the FIFO Memory frequency while keeping the total amount of data received per unit time unchanged, taking into account performance. At the same time, by using registers to complete ping-pong buffering and realize data splicing and splitting, the design is relatively simple and the cost is low. In addition, when the subsequent module reads that the FIFO Memory is empty, data pass-through can also be used to reduce system cavitation and achieve high utilization rate.

[0095] Embodiment 2

[0096] Figure 5FIG. 1 is a schematic diagram of a structure of a device for reducing RAM frequency in a FIFO according to a second embodiment of the present invention. Figure 5 As shown, the device comprises:

[0097] The comparison module 201 is used to obtain wdata data from the upstream module, as well as the bit width and clock frequency of the wdata data, and after obtaining the highest supported clock frequency of the RAM, compare the wdata data clock frequency with the highest supported clock frequency of the RAM to obtain a comparison result.

[0098] The operation module 202 is used to cache the wdata data in register reg0 and register reg1 in a preset order by using a ping-pong operation according to the comparison result; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

[0099] The splicing module 203 is used to complete the splicing of the cached data in the register reg0 and the register reg1 at the rising edge of the slow clock frequency to obtain spliced ​​data with a data bit width twice that of the wdata data, and store the spliced ​​data in the register reg_slow_in; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock.

[0100] The storage module 204 is used to store the spliced ​​data in the register reg_slow_in into the FIFO Memory at the slow clock frequency.

[0101] The splitting module 205 is used to store the spliced ​​data in the FIFO Memory into the register reg_slow_out at the slow clock frequency when using the subsequent module to read the spliced ​​data in the FIFO Memory, and then use the ping-pong operation to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFOMemory is read empty, the cached data in the register reg0 or the register reg1 is output as data_out according to the preset order, so that the external interface timing meets the standard FIFO logic.

[0102] Preferably, the comparison module 201 includes:

[0103] An acquisition unit, used to acquire wdata data from an upstream module, as well as the bit width and clock frequency of the wdata data, and to acquire the highest supported clock frequency of the RAM;

[0104] A comparison unit is used to compare the wdata data clock frequency with the highest supported clock frequency of the RAM to obtain a comparison result; wherein the comparison result includes two results, one result is that the wdata data clock frequency is not greater than the highest supported clock frequency of the RAM, and the other result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM.

[0105] Preferably, the operation module 202 includes:

[0106] A direct storage unit, used for directly storing the wdata data into the FIFO Memory when the comparison result shows that the clock frequency of the wdata data is not greater than the highest supported clock frequency of the RAM, so as to be directly read by subsequent modules;

[0107] A ping-pong unit is used to use a ping-pong operation to first store the wdata data into register reg0 and then into register reg1 when the comparison result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

[0108] An apparatus for reducing RAM frequency in a FIFO provided by an embodiment of the present invention can execute a method for reducing RAM frequency in a FIFO provided by any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method.

[0109] Embodiment 3

[0110] Figure 6 A schematic diagram of the structure of a computing terminal provided in Embodiment 3 of the present invention; Figure 6 A block diagram of an exemplary terminal suitable for implementing embodiments of the present invention is shown. Figure 6 The terminal shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0111] like Figure 6 As shown, the terminal 12 is in the form of a general purpose computing device. The components of the terminal 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0112] Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. By way of example, these architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MAC) bus, an Enhanced ISA bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0113] Terminal 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by terminal 12, including volatile and non-volatile media, removable and non-removable media.

[0114] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Terminal 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Figure 6 not shown, usually called a "hard drive"). Although Figure 6 Not shown in the figure, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present invention.

[0115] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0116] The terminal 12 may also communicate with one or more external devices 14 (e.g., keyboards, pointing devices, displays 24, etc.), may communicate with one or more devices that enable a user to interact with the terminal 12, and / or may communicate with any device that enables the terminal 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may be performed via an input / output (I / O) interface 22. Furthermore, the terminal 12 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other modules of the terminal 12 via a bus 18. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the terminal 12, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0117] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the method for reducing the RAM frequency in the FIFO provided by the embodiment of the present invention.

[0118] Embodiment 4

[0119] Embodiment 4 of the present invention further provides a storage medium comprising computer executable instructions, wherein the computer executable instructions, when executed by a computer processor, are used to execute any of the methods for reducing the RAM frequency in the FIFO as provided in the above embodiments.

[0120] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0121] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0122] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0123] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0124] Embodiment 5

[0125] Embodiment 5 of the present invention further provides a computer product, including a computer program, which, when executed by a processor, implements the method for reducing the RAM frequency in the FIFO as described in the above embodiment.

[0126] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for reducing RAM frequency in FIFO, characterized in that, include: After obtaining wdata data from an upstream module, as well as the bit width and clock frequency of the wdata data, and obtaining the highest supported clock frequency of the RAM, the clock frequency of the wdata data is compared with the highest supported clock frequency of the RAM to obtain a comparison result; According to the comparison result, the wdata data is cached in register reg0 and register reg1 in a preset order by using a ping-pong operation; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data; The cached data in the register reg0 and the register reg1 are spliced ​​at the rising edge of the slow clock frequency to obtain spliced ​​data with a data width twice that of the wdata data, and the spliced ​​data is stored in the register reg_slow_in; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock; At the slow clock frequency, storing the spliced ​​data in the register reg_slow_in into the FIFO Memory; When the subsequent module is used to read the spliced ​​data in the FIFO Memory, the spliced ​​data in the FIFO Memory is first stored in the register reg_slow_out at the slow clock frequency, and then the ping-pong operation is used to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFO Memory is read empty, the cached data in the register reg0 or the register reg1 is output as data_out according to the preset order, so that the external interface timing meets the standard FIFO logic.

2. The method according to claim 1, characterized in that After obtaining the wdata data from the upstream module, the bit width and the clock frequency of the wdata data, and obtaining the highest supported clock frequency of the RAM, the wdata data clock frequency is compared with the highest supported clock frequency of the RAM to obtain a comparison result, including: Get the wdata data from the upstream module, as well as the bit width and clock frequency of the wdata data, and get the highest supported clock frequency of the RAM; The wdata data clock frequency is compared with the highest supported clock frequency of the RAM to obtain a comparison result; wherein the comparison result includes two results, one result is that the wdata data clock frequency is not greater than the highest supported clock frequency of the RAM, and the other result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM.

3. The method according to claim 2, characterized in that The method of caching the wdata data into register reg0 and register reg1 in a preset order by using a ping-pong operation according to the comparison result includes: When the comparison result is that the clock frequency of the wdata data is not greater than the highest supported clock frequency of the RAM, the wdata data is directly stored in the FIFO Memory for direct reading by subsequent modules; When the comparison result is that the clock frequency of the wdata data is greater than the highest supported clock frequency of the RAM, the wdata data is first stored in register reg0 and then in register reg1 using a ping-pong operation; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

4. The method according to claim 3, characterized in that The step of splicing the cached data in the register reg0 and the register reg1 at the rising edge of the slow clock frequency to obtain spliced ​​data having a data width twice that of the wdata data, and storing the spliced ​​data in the register reg_slow_in comprises: After the data is stored in the register reg1, the cached data in the register reg0 and the register reg1 are spliced ​​at the rising edge of the slow clock frequency, the cached data in the register reg0 is placed in the low position, and the cached data in the register reg1 is placed in the high position, so as to obtain spliced ​​data with a data width twice that of the wdata data; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock; At the slow clock frequency, the spliced ​​data is stored in the register reg_slow_in.

5. The method according to claim 4, characterized in that When the subsequent module is used to read the spliced ​​data in the FIFO Memory, the spliced ​​data in the FIFO Memory is first stored in the register reg_slow_out at the slow clock frequency, and then the ping-pong operation is used to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFO Memory is read empty, the cached data in the register reg0 or the register reg1 is used as data_out for data direct output according to the preset sequence, so that the external interface timing meets the standard FIFO logic, including: When the subsequent module reads that the FIFO Memory is empty, if there is cached data in the register reg0, the cached data in the register reg0 is directly output as data_out at a fast clock frequency, otherwise it is not output; wherein the fast clock frequency is the same as the clock frequency corresponding to the wdata data; When a subsequent module reads the spliced ​​data in the FIFO Memory, the spliced ​​data in the FIFO Memory is stored in a register reg_slow_out at the slow clock frequency; Splitting the data in the register reg_slow_out to obtain high-order data and low-order data; At the fast clock frequency, the low-order data is written into register reg2, and the high-order data is written into register reg3; Data is selected from the register reg2 and the register reg3 through the mux logic as data_out for output, and the low-order data in the register reg2 is output first, and then the high-order data in the register reg3 is output.

6. A device for reducing RAM frequency in FIFO, characterized in that include: A comparison module is used to obtain wdata data from an upstream module, as well as a bit width and a clock frequency of the wdata data, and after obtaining the highest supported clock frequency of the RAM, compare the clock frequency of the wdata data with the highest supported clock frequency of the RAM to obtain a comparison result; An operation module, configured to cache the wdata data in registers reg0 and reg1 in a preset order by using a ping-pong operation according to the comparison result; wherein the bit widths of registers reg0 and reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in registers reg0 and reg1 are the same as the clock frequencies corresponding to the wdata data; A splicing module, used for completing the splicing of the cached data in the register reg0 and the register reg1 at the rising edge of the slow clock frequency to obtain spliced ​​data with a data width twice that of the wdata data, and storing the spliced ​​data in the register reg_slow_in; wherein the slow clock frequency is obtained by clock division of the clock frequency corresponding to the wdata data, and the slow clock frequency and the clock frequency corresponding to the wdata data are the same source clock; A storage module, used for storing the spliced ​​data in the register reg_slow_in into the FIFO Memory at the slow clock frequency; The splitting module is used to store the spliced ​​data in the FIFO Memory into the register reg_slow_out at the slow clock frequency when the subsequent module reads the spliced ​​data in the FIFO Memory, and then use the ping-pong operation to realize the split reading of the spliced ​​data in the register reg_slow_out; wherein, when the FIFO Memory is read empty, the cached data in the register reg0 or the register reg1 is output as data_out according to the preset order, so that the external interface timing meets the standard FIFO logic.

7. The device according to claim 6, characterized in that The comparison module comprises: An acquisition unit, used to acquire wdata data from an upstream module, as well as the bit width and clock frequency of the wdata data, and to acquire the highest supported clock frequency of the RAM; A comparison unit is used to compare the wdata data clock frequency with the highest supported clock frequency of the RAM to obtain a comparison result; wherein the comparison result includes two results, one result is that the wdata data clock frequency is not greater than the highest supported clock frequency of the RAM, and the other result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM.

8. The device according to claim 6, characterized in that The operation module includes: A direct storage unit, used for directly storing the wdata data into the FIFO Memory when the comparison result shows that the clock frequency of the wdata data is not greater than the highest supported clock frequency of the RAM, so as to be directly read by subsequent modules; A ping-pong unit is used to use a ping-pong operation to first store the wdata data into register reg0 and then into register reg1 when the comparison result is that the wdata data clock frequency is greater than the highest supported clock frequency of the RAM; wherein the bit widths of register reg0 and register reg1 are both half of the RAM bit width, and the clock frequencies of the cached data in register reg0 and register reg1 are the same as the clock frequencies corresponding to the wdata data.

9. A computing terminal, characterized in that: include: one or more processors; A storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method for reducing the RAM frequency in the FIFO according to any one of claims 1 to 5.

10. A storage medium containing computer executable instructions, characterized in that: The computer executable instructions are used to perform the method of reducing RAM frequency in FIFO as claimed in any one of claims 1 to 5 when executed by a computer processor.

11. A computer product, comprising a computer program, characterized in that: When the computer program is executed by a processor, the method for reducing the RAM frequency in a FIFO according to any one of claims 1 to 5 is implemented.

Images