Semiconductor structure and forming method thereof, and method for measuring overlay error

Abstract

The invention discloses a semiconductor structure, a forming method thereof and a method for measuring overlay error, and the structure comprises a to-be-measured wafer which comprises a measurement area; the first measuring mark is located in the measuring area, the first measuring mark comprises a first strip-shaped structure extending in the first direction and directly facing the first strip-shaped structure and a second strip-shaped structure extending in the second direction and directly facing the second strip-shaped structure, and the first direction is perpendicular to the second direction; the shape defined by the first strip-shaped structures right facing the first strip-shaped structures and the second strip-shaped structures right facing the second strip-shaped structures is rectangular. The second measurement mark is located in the measurement area, the second measurement mark surrounds the first measurement mark, the shape defined by the second measurement mark is rectangular, and a height difference exists between the top of the second measurement mark and the top of the first measurement mark. The accuracy of overlay error monitoring of the first-layer pattern of the wafer is improved, and the product yield of the wafer is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same, and a method for measuring overlay error. Background Art

[0002] Overlay is a key parameter in the working process of the lithography machine. It describes the relative position deviation between the current layer (photoresist pattern) and the reference layer (pattern in the substrate) in the multi-layer lithography process. Ideally, the two layers of patterns should completely overlap, but in fact, due to the existence of systematic errors and accidental errors, the positions of the two layers of patterns deviate, resulting in overlay error. In integrated circuit manufacturing, overlay error is a key indicator for monitoring the quality of the lithography process, which affects the reliable connection of the circuit.

[0003] In order to ensure the accuracy of overlay between process layers, signal alignment is performed first during the photolithography process. However, the first layer of the wafer has no reference coordinates, so signal alignment cannot be performed and positioning can only be performed through the wafer notch. The accuracy of this process is completely dependent on the performance of the exposure machine itself, and there is a risk of offset. If the first layer is offset, it will affect the overlay accuracy of subsequent layers, increase the difficulty of process processing, and in severe cases, cause the product to be scrapped.

[0004] At present, the accuracy of overlay error monitoring of the first layer of wafer still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, and a method for measuring overlay error, which are beneficial to improving the accuracy of overlay error monitoring of the first layer pattern of the wafer and improving the product yield of the wafer.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer, comprising: a wafer to be measured, the wafer to be measured comprising a measurement area; a first measurement mark located in the measurement area, the first measurement mark comprising a first strip structure extending along a first direction and opposite to each other and a second strip structure extending along a second direction and opposite to each other, the first direction is perpendicular to the second direction, and the shape formed by the first strip structures opposite to each other and the second strip structures opposite to each other is rectangular; a second measurement mark located in the measurement area, the second measurement mark surrounds the first measurement mark, the shape formed by the second measurement mark is rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark.

[0007] Optionally, the first measurement mark includes an opening.

[0008] Optionally, the end of the first strip-shaped structure is in contact with the end of the second strip-shaped structure; or, the end of the first strip-shaped structure is separated from the end of the second strip-shaped structure.

[0009] Optionally, the second measurement mark includes a third strip structure extending along the first direction and facing each other, and a fourth strip structure extending along the second direction and facing each other, and an end of the third strip structure is in contact with an end of the fourth strip structure.

[0010] Optionally, the distance between the outer boundary of the third strip structure and the first strip structure is between 4 microns and 10 microns; the distance between the outer boundary of the fourth strip structure and the second strip structure is between 4 microns and 10 microns.

[0011] Optionally, the semiconductor structure also includes: a first filling layer, located in the area enclosed by the first strip structure and the second strip structure opposite to each other, the top of the first filling layer is flush with the top of the second measurement mark, and the first filling layer and the second measurement mark are an integrated structure.

[0012] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, which is suitable for measuring the overlay error of the first layer pattern of a wafer, comprising: providing a wafer to be measured, the wafer to be measured comprising a measurement area; forming a first measurement mark in the measurement area, the first measurement mark comprising a first strip structure extending along a first direction and opposite to each other, and a second strip structure extending along a second direction and opposite to each other, the first direction is perpendicular to the second direction, and the shape formed by the first strip structures opposite to each other and the second strip structures opposite to each other is rectangular; forming a second measurement mark surrounding the first measurement mark in the measurement area, the shape formed by the second measurement mark is rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark.

[0013] Optionally, the first measurement mark and the second measurement mark are formed in the same step.

[0014] Optionally, the step of forming the first measurement mark and the second measurement mark includes: forming a measurement mark material layer in the measurement area of ​​the first layer of the wafer; performing graphing on the measurement mark material layer to form a first opening extending along a first direction and opposite to each other, and a second opening extending along a second direction and opposite to each other in the measurement mark material layer, the first direction is perpendicular to the second direction, the shape formed by the first openings opposite to each other and the second openings opposite to each other is a rectangle, and the first opening and the second opening are used as the first measurement mark, and the remaining measurement mark material layer surrounding the first measurement mark is used as the second measurement mark.

[0015] Optionally, in the step of forming the first measurement mark and the second measurement mark, the remaining measurement mark material layer located in the area enclosed by the first opening and the second opening opposite to each other is used as a first filling layer, the top of the first filling layer is flush with the top of the second measurement mark, and the first filling layer and the second measurement mark are an integrated structure.

[0016] Optionally, a distance between an outer boundary of the second measurement mark and the first strip structure in the first direction is between 4 microns and 10 microns; a distance between an outer boundary of the second measurement mark and the second strip structure in the second direction is between 4 microns and 10 microns.

[0017] Correspondingly, an embodiment of the present invention also provides a method for measuring overlay error, comprising: providing a semiconductor structure provided by an embodiment of the present invention; obtaining a signal wave center point of the second measurement mark and a signal wave center point of the first measurement mark based on a height difference between the top of the second measurement mark and the top of the first measurement mark; and obtaining an overlay error between the second measurement mark and the first measurement mark based on the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark.

[0018] Optionally, the step of obtaining the center point of the signal wave of the second measurement mark and the center point of the signal wave of the first measurement mark includes: scanning the first measurement mark and the second measurement mark by an electron beam emitted by a scanning electron microscope; obtaining images of the first measurement mark and the second measurement mark after the electron beam scanning; based on the images of the first measurement mark and the second measurement mark, obtaining the center point of the signal wave of the second measurement mark and the center point of the signal wave of the first measurement mark.

[0019] Optionally, the step of obtaining the overlay error between the second measurement mark and the first measurement mark based on the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark includes: establishing an XY coordinate system; determining the coordinates of the signal wave center point of the second measurement mark in the XY coordinate system and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system; obtaining the overlay error between the second measurement mark and the first measurement mark based on the coordinates of the signal wave center point of the second measurement mark in the XY coordinate system and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0021] An embodiment of the present invention provides a semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer, wherein the wafer to be measured includes a measurement area, a first measurement mark is located in the measurement area, the first measurement mark includes a first strip structure extending along a first direction and opposite to each other, and a second strip structure extending along a second direction and opposite to each other, the first direction is perpendicular to the second direction, and the shape formed by the first strip structures opposite to each other and the second strip structures opposite to each other is rectangular, the second measurement mark is located in the measurement area, the second measurement mark surrounds the first measurement mark, the shape formed by the second measurement mark is rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark, compared with the existing method of judging the first layer pattern of the wafer by manual visual inspection, In order to determine whether an overlay error occurs in the pattern of the first layer of the wafer, an embodiment of the present invention enables a height difference between the top of the second measurement mark and the top of the first measurement mark. In the subsequent process of measuring the overlay error, when the signal wave passes through the second measurement mark and the first measurement mark, a phase difference is generated due to the difference in path lengths caused by the height difference. The center position of the signal wave of the second measurement mark and the center position of the signal wave of the first measurement mark can be distinguished through the phase difference. Therefore, the overlay error between the second measurement mark and the first measurement mark can be obtained according to the center position of the signal wave of the second measurement mark and the center position of the signal wave of the first measurement mark, so as to determine whether an overlay error occurs in the pattern of the first layer of the wafer, thereby improving the accuracy of monitoring the overlay error of the first layer of the wafer and improving the product yield of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 to Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0023] Figures 3 to 5 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0024] Figure 6 It is a flowchart of steps corresponding to an embodiment of a method for measuring overlay error of the present invention. DETAILED DESCRIPTION

[0025] As can be seen from the background technology, currently, the accuracy of monitoring the overlay error of the first layer of a wafer still needs to be improved.

[0026] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer, including: a wafer to be measured, the wafer to be measured including a measurement area; a first measurement mark, located in the measurement area, the first measurement mark including a first strip structure extending along a first direction and opposite to each other and a second strip structure extending along a second direction and opposite to each other, the first direction is perpendicular to the second direction, and the shape formed by the first strip structures opposite to each other and the second strip structures opposite to each other is rectangular; a second measurement mark, located in the measurement area, the second measurement mark surrounds the first measurement mark, the shape formed by the second measurement mark is rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark.

[0027] In the semiconductor structure provided by the embodiment of the present invention, there is a height difference between the top of the second measurement mark and the top of the first measurement mark. Compared with the existing method of judging whether the first layer pattern of the wafer has an overlay error by manual visual inspection, the embodiment of the present invention makes the top of the second measurement mark have a height difference with the top of the first measurement mark. In the subsequent process of measuring the overlay error, when the signal wave passes through the second measurement mark and the first measurement mark, a phase difference will be generated due to the difference in path lengths generated by the height difference. The center position of the signal wave of the second measurement mark and the center position of the signal wave of the first measurement mark can be distinguished through the phase difference, so that the overlay error between the second measurement mark and the first measurement mark can be obtained according to the center position of the signal wave of the second measurement mark and the center position of the signal wave of the first measurement mark, and then whether the first layer pattern of the wafer has an overlay error can be judged, thereby improving the accuracy of overlay error monitoring of the first layer pattern of the wafer and improving the product yield of the wafer.

[0028] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figure 1 to Figure 2 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1 It is a top view of the wafer to be tested; Figure 2 yes Figure 1 Enlarged view of reference numeral 201.

[0030] The semiconductor structure includes: a wafer to be tested 100, the wafer to be tested 100 includes a measurement area 101; a first measurement mark 130, located in the measurement area 101, the first measurement mark 130 includes a first direction (such as Figure 2 The first strip structure 121 extending in the X direction and facing each other and along the second direction (as shown in the X direction) Figure 2 The first direction is perpendicular to the second direction, and the shape formed by the first strip structures 121 and the second strip structures 120 facing each other is rectangular; the second measurement marks 150 are located in the measurement area 101, and the second measurement marks 150 surround the first measurement marks 130. The shape formed by the second measurement marks 150 is rectangular, and there is a height difference between the top of the second measurement marks 150 and the top of the first measurement marks 130.

[0031] Specifically, there is a height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130. In the subsequent process of measuring the overlay error, when the signal wave passes through the second measurement mark 150 and the first measurement mark 130, a phase difference will be generated due to the difference in path length caused by the height difference. The center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130 can be distinguished through the phase difference. Therefore, the overlay error between the second measurement mark 150 and the first measurement mark 130 can be obtained according to the center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130, and then it can be determined whether the overlay error occurs in the first layer pattern of the wafer, thereby improving the accuracy of overlay error monitoring of the first layer pattern of the wafer and improving the product yield of the wafer.

[0032] It should be noted that in the process of forming semiconductor structures, multi-layer stacked patterns will be formed on the wafer. The overlay error of the first layer pattern will affect the overlay accuracy of subsequent stacked layers and affect the product yield of the wafer. Therefore, it is extremely important to measure the overlay error of the first layer pattern.

[0033] Specifically, the wafer 100 to be tested is used as a wafer for subsequent overlay error measurement.

[0034] In this embodiment, the wafer 100 to be tested includes a measurement area 101 .

[0035] Specifically, the measurement area 101 is an area where the first measurement mark 130 and the second measurement mark 150 are arranged.

[0036] As an example, the measurement area 101 is usually disposed in a scribe line of the wafer 100 to be tested. In other embodiments, the measurement area 101 is also disposed in an effective chip area of ​​the wafer 100 to be tested.

[0037] It should be noted that, by providing the first measurement mark 130 , it is convenient to subsequently obtain the center point of the signal wave of the first measurement mark 130 .

[0038] In this embodiment, the first measurement mark 130 includes a first strip structure 121 extending along a first direction and opposite to each other, and a second strip structure 120 extending along a second direction and opposite to each other. The first direction is perpendicular to the second direction, and the shape formed by the first strip structures 121 and the second strip structures 120 opposite to each other is rectangular.

[0039] Specifically, by providing the first strip structures 121 and the second strip structures 120 that are opposite to each other, the influence of system errors and environmental interference can be effectively eliminated in the process of obtaining the center point of the signal wave, thereby improving the accuracy of the measurement result.

[0040] It should be noted that the first strip structure 121 extends along the first direction, and the second strip structure 120 extends along the second direction, and the first direction is perpendicular to the second direction. In the subsequent process of measuring the overlay error, the offset of the first measurement mark 130 and the second measurement mark 150 in the first direction and the offset of the first measurement mark 130 and the second measurement mark 150 in the second direction can be obtained.

[0041] In this embodiment, the first measurement mark 130 includes an opening.

[0042] It should be noted that the top of the physical film layer is exposed at the bottom of the opening. Since the second measurement mark 150 surrounds the first measurement mark 130, there is a height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130. In other words, there is a height difference between the top of the second measurement mark 150 and the top of the physical film layer exposed at the bottom of the opening. When the signal wave passes through the second measurement mark 150 and the first measurement mark 130, a phase difference is generated due to the difference in path lengths caused by the height difference. The phase difference can be used to distinguish the center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130.

[0043] In this embodiment, the end of the first strip structure 121 is separated from the end of the second strip structure 120 .

[0044] Specifically, the end of the first strip structure 121 is separated from the end of the second strip structure 120. In the process of forming the first strip structure 121 and the second strip structure 120, the process difficulty of forming the first strip structure 121 and the second strip structure 120 is reduced, and the risk of over-etching the end of the first strip structure 121 and the end of the second strip structure 120 in their extension direction is avoided, thereby reducing the impact on the waveform accuracy of the signal wave.

[0045] In other embodiments, an end of the first strip-shaped structure 121 contacts an end of the second strip-shaped structure 120 .

[0046] It should be noted that, by setting the second measurement mark 150, it is convenient to subsequently obtain the center point of the signal wave of the second measurement mark 150, and by utilizing the height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130, in the subsequent process of measuring the overlay error, when the signal wave passes through the second measurement mark 150 and the first measurement mark 130, a phase difference will be generated due to the difference in path lengths generated by the height difference. The center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130 can be distinguished through the phase difference, so that the overlay error between the second measurement mark 150 and the first measurement mark 130 can be obtained according to the center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130.

[0047] In this embodiment, the second measurement mark 150 includes a third strip structure 151 extending along the first direction and facing each other, and a fourth strip structure 152 extending along the second direction and facing each other, and an end of the third strip structure 151 contacts an end of the fourth strip structure 152 .

[0048] It should be noted that the third strip structure 151 extends along the first direction and the fourth strip structure 152 extends along the second direction, and the first direction is perpendicular to the second direction. In the subsequent process of measuring the overlay error, the offset of the third measurement mark and the fourth measurement mark in the first direction and the offset of the third measurement mark and the fourth measurement mark in the second direction can be obtained.

[0049] It should also be noted that the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 should not be too large or too small. If the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 is too large, when the area of ​​the wafer 100 to be measured is certain, it is easy to cause the area of ​​the periphery of the measurement area 101 to become smaller, which also causes the area of ​​the formation area of ​​the effective chip to become smaller, thereby affecting the formation quality of the wafer; if the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 is too small, in the subsequent process of obtaining the center point position of the signal wave of the first measurement mark 130 and the center position of the signal wave of the second measurement mark 150, the probability of mutual interference between the signal wave passing through the first measurement mark 130 and the signal wave passing through the second measurement mark 150 is increased, thereby reducing the accuracy of obtaining the center point of the signal wave of the first measurement mark 130 and the center of the signal wave of the second measurement mark 150, thereby affecting the product yield of the wafer. Therefore, in this embodiment, the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 is between 4 micrometers and 10 micrometers.

[0050] Specifically, the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 should not be too large or too small. If the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 is too large, when the area of ​​the wafer 100 to be measured is certain, it is easy to cause the area of ​​the periphery of the measurement area 101 to become smaller, which also causes the area of ​​the formation area of ​​the effective chip to become smaller, thereby affecting the formation quality of the wafer; if the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 is too small, in the subsequent process of obtaining the center point position of the signal wave of the first measurement mark 130 and the center position of the signal wave of the second measurement mark 150, the probability of mutual interference between the signal wave passing through the first measurement mark 130 and the signal wave passing through the second measurement mark 150 is increased, thereby reducing the accuracy of obtaining the center point of the signal wave of the first measurement mark 130 and the center of the signal wave of the second measurement mark 150, thereby affecting the product yield of the wafer. Therefore, in this embodiment, the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 is between 4 micrometers and 10 micrometers.

[0051] In this embodiment, the semiconductor structure also includes: a first filling layer 199, which is located in the area enclosed by the first strip structure 121 and the second strip structure 120 that are opposite to each other, the top of the first filling layer 199 is flush with the top of the second measurement mark 150, and the first filling layer 199 and the second measurement mark 150 are an integrated structure.

[0052] Specifically, the top of the first filling layer 199 is flush with the top of the second measurement mark 150, and the first filling layer 199 and the second measurement mark 150 are an integrated structure, so that the first filling layer 199 fills the area enclosed by the first strip structure 121 and the second strip structure 120 opposite to it, so that the waveform of the signal wave passing through the first filling layer 199 is close to the waveform passing through the top surface of the second measurement mark 150, and can be distinguished from the waveform passing through the first measurement mark 130, so that the center point of the signal wave of the first measurement mark 130 can be accurately obtained.

[0053] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure. Figures 3 to 5 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0054] refer to Figure 3 , a wafer 200 to be tested is provided, wherein the wafer 200 to be tested includes a measurement area 201.

[0055] It should be noted that in the process of forming semiconductor structures, multi-layer stacked patterns will be formed on the wafer. The overlay error of the first layer pattern will affect the overlay accuracy of subsequent stacked layers and affect the product yield of the wafer. Therefore, it is extremely important to measure the overlay error of the first layer pattern.

[0056] Specifically, the wafer to be tested 200 is used as a wafer for subsequent overlay error measurement.

[0057] In this embodiment, the wafer 200 to be tested includes a measurement area 201 .

[0058] Specifically, the measurement area 201 is an area where a first measurement mark and a second measurement mark are subsequently formed.

[0059] As an example, the measurement area 201 is usually disposed in a scribe line of the wafer 200 to be tested. In other embodiments, the measurement area 201 is also disposed in an effective chip area of ​​the wafer 200 to be tested.

[0060] refer to Figures 4 to 5 ,in, Figure 4 Tie Figure 3 An enlarged top view of the reference numeral 201, Figure 5 Tie Figure 4 A cross-sectional view along the AA direction. A first measurement mark 230 is formed in the measurement area 201. The first measurement mark 230 includes a first measurement mark 230 along a first direction (eg Figure 4 The first strip structure 297 extending in the X direction and facing each other and along the second direction (as shown in the X direction) Figure 4A second strip structure 296 extending and opposite to the first measurement mark 230 (shown in the Y direction), the first direction is perpendicular to the second direction, and the shape formed by the first strip structures 297 and the second strip structures 296 opposite to each other is rectangular; a second measurement mark 250 is formed in the measurement area 201 to surround the first measurement mark 230, the shape formed by the second measurement mark 250 is rectangular, and there is a height difference between the top of the second measurement mark 250 and the top of the first measurement mark 230.

[0061] It should be noted that there is a height difference between the top of the second measurement mark 250 and the top of the first measurement mark 230. Compared with the existing method of judging whether the first layer pattern of the wafer has an overlay error by manual visual inspection, the embodiment of the present invention makes the top of the second measurement mark 250 and the top of the first measurement mark 230 have a height difference. In the subsequent process of measuring the overlay error, when the signal wave passes through the second measurement mark 250 and the first measurement mark 230, a phase difference will be generated due to the difference in path length caused by the height difference. The center position of the signal wave of the second measurement mark 250 and the center position of the signal wave of the first measurement mark 230 can be distinguished through the phase difference, so that the overlay error between the second measurement mark 250 and the first measurement mark 230 can be obtained according to the center position of the signal wave of the second measurement mark 250 and the center position of the signal wave of the first measurement mark 230, and then whether the first layer pattern of the wafer has an overlay error can be judged, thereby improving the accuracy of overlay error monitoring of the first layer pattern of the wafer and improving the product yield of the wafer.

[0062] In this embodiment, the first measurement mark 230 and the second measurement mark 250 are formed in the same step.

[0063] Specifically, the first measurement mark 230 and the second measurement mark 250 are formed in the same step, which reduces the process steps and reduces the process cost.

[0064] In this embodiment, the steps of forming the first measurement mark 230 and the second measurement mark 250 include: forming a measurement mark material layer 298 in the measurement area 201 of the first layer of the wafer; performing a graphic processing on the measurement mark material layer 298 to form a first opening 221 extending along a first direction and opposite to each other, and a second opening 220 extending along a second direction and opposite to each other in the measurement mark material layer 298, the first direction is perpendicular to the second direction, and the shape formed by the first opening 221 and the second opening 220 opposite to each other is rectangular, and the first opening 221 and the second opening 220 are used as the first measurement mark 230, and the remaining measurement mark material layer 298 surrounding the first measurement mark 230 is used as the second measurement mark 250.

[0065] Specifically, by providing the first opening 221 and the second opening 220 that are opposite to each other, the influence of system errors and environmental interference can be effectively eliminated in the process of obtaining the center point of the signal wave, thereby improving the accuracy of the measurement result.

[0066] It should be noted that the first opening 221 extends along the first direction, and the second opening 220 extends along the second direction, and the first direction is perpendicular to the second direction. In the subsequent process of measuring the overlay error, the offset of the first measurement mark 230 and the second measurement mark 250 in the first direction and the offset of the first measurement mark 230 and the second measurement mark 250 in the second direction can be obtained.

[0067] In this embodiment, the first opening 221 and the second opening 220 serve as the first measurement mark 230 .

[0068] It should be noted that the top of the physical film layer (i.e., the measurement mark material layer 298) is exposed at the bottom of the first opening 221 and the second opening 220. Since the second measurement mark 250 surrounds the first measurement mark 230, there is a height difference between the top of the second measurement mark 250 and the top of the first measurement mark 230. In other words, there is a height difference between the top of the second measurement mark 250 and the top of the physical film layer exposed at the bottom of the first opening 221 and the second opening 220. When the signal wave passes through the second measurement mark 250 and the first measurement mark 230, a phase difference will be generated due to the difference in path lengths generated by the height difference. The center position of the signal wave of the second measurement mark 250 and the center position of the signal wave of the first measurement mark 230 can be distinguished through the phase difference.

[0069] In this embodiment, in the step of forming the first measurement mark 230 and the second measurement mark 250, the remaining measurement mark material layer 298 located in the area enclosed by the first opening 221 and the second opening 220 opposite to each other is used as the first filling layer 299, the top of the first filling layer 299 is flush with the top of the second measurement mark 250, and the first filling layer 299 and the second measurement mark 250 are an integrated structure.

[0070] Specifically, the top of the first filling layer 299 is flush with the top of the second measurement mark 250, and the first filling layer 299 and the second measurement mark 250 are an integrated structure, so that the first filling layer 299 fills the area enclosed by the first strip structure 297 and the second strip structure 296 opposite to it, so that the waveform of the signal wave passing through the first filling layer 299 is close to the waveform passing through the top surface of the second measurement mark 250, and can be distinguished from the waveform passing through the first measurement mark 230, so that the center point of the signal wave of the first measurement mark 230 can be accurately obtained.

[0071] It should be noted that the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction should not be too large or too small. If the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction is too large, when the area of ​​the wafer 200 to be measured is certain, it is easy to cause the area of ​​the periphery of the measurement area 201 to become smaller, which also causes the area of ​​the formation area of ​​the effective chip to become smaller, thereby affecting the formation quality of the wafer; if the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction is too small, in the subsequent process of obtaining the center point position of the signal wave of the first measurement mark 230 and the center position of the signal wave of the second measurement mark 250, the probability of mutual interference between the signal wave passing through the first measurement mark 230 and the signal wave passing through the second measurement mark 250 is increased, thereby reducing the accuracy of obtaining the center point of the signal wave of the first measurement mark 230 and the center of the signal wave of the second measurement mark 250, thereby affecting the product yield of the wafer. To this end, in this embodiment, the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction is between 4 micrometers and 10 micrometers.

[0072] It should also be noted that the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction should not be too large or too small. If the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction is too large, when the area of ​​the wafer 200 to be measured is certain, it is easy to cause the area of ​​the periphery of the measurement area 201 to become smaller, which also causes the area of ​​the formation area of ​​the effective chip to become smaller, thereby affecting the formation quality of the wafer; if the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction is too small, in the subsequent process of obtaining the center point position of the signal wave of the first measurement mark 230 and the center position of the signal wave of the second measurement mark 250, the probability of mutual interference between the signal wave passing through the first measurement mark 230 and the signal wave passing through the second measurement mark 250 is increased, thereby reducing the accuracy of obtaining the center point of the signal wave of the first measurement mark 230 and the center of the signal wave of the second measurement mark 250, thereby affecting the product yield of the wafer. Therefore, in this embodiment, the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction is between 4 micrometers and 10 micrometers.

[0073] Accordingly, an embodiment of the present invention also provides a method for measuring overlay error. Figure 6 The present invention is a flowchart of a method for measuring overlay error according to an embodiment of the present invention.

[0074] Combined with reference Figure 1 to Figure 2 , execute step S1: provide a semiconductor structure provided by an embodiment of the present invention.

[0075] Specifically, the detailed description of the semiconductor structure is not repeated here, and please refer to the aforementioned embodiments.

[0076] Combined with reference Figure 1 to Figure 2 , execute step S2: based on the height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130, obtain the center point of the signal wave of the second measurement mark 150 and the center point of the signal wave of the first measurement mark 130.

[0077] Specifically, there is a height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130. In the process of obtaining the center point of the signal wave of the second measurement mark 150 and the center point of the signal wave of the first measurement mark 130, when the signal wave passes through the second measurement mark 150 and the first measurement mark 130, a phase difference will be generated due to the difference in path length caused by the height difference. The center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130 can be distinguished through the phase difference, so that the overlay error between the second measurement mark 150 and the first measurement mark 130 can be obtained according to the center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130, and then it is determined whether the overlay error occurs in the first layer pattern of the wafer, thereby improving the accuracy of overlay error monitoring of the first layer pattern of the wafer and improving the product yield of the wafer.

[0078] In this embodiment, the steps of obtaining the center point of the signal wave of the second measurement mark 150 and the center point of the signal wave of the first measurement mark 130 include: scanning the first measurement mark 130 and the second measurement mark 150 by an electron beam emitted by a scanning electron microscope; obtaining images of the first measurement mark 130 and the second measurement mark 150 after the electron beam scanning; and obtaining the center point of the signal wave of the second measurement mark 150 and the center point of the signal wave of the first measurement mark 130 based on the images of the first measurement mark 130 and the second measurement mark 150.

[0079] It should be noted that, based on the images of the first measurement mark 130 and the second measurement mark 150 , obtaining the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 can improve measurement accuracy and enhance signal recognition capability.

[0080] Combined with reference Figure 1 to Figure 2 , execute step S3: based on the center point of the signal wave of the second measurement mark 150 and the center point of the signal wave of the first measurement mark 130, obtain the overlay error between the second measurement mark 150 and the first measurement mark 130.

[0081] Specifically, by obtaining the overlay error between the second measurement mark 150 and the first measurement mark 130 , the offset of the first layer pattern of the wafer 100 to be tested can be determined, providing a process basis for subsequently forming a multi-layer stacked film layer above the first layer pattern of the wafer 100 to be tested.

[0082] In this embodiment, based on the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130, the step of obtaining the overlay error between the second measurement mark 150 and the first measurement mark 130 includes: establishing an XY coordinate system; determining the coordinates of the signal wave center point of the second measurement mark 150 in the XY coordinate system and the coordinates of the signal wave center point of the first measurement mark 130 in the XY coordinate system; based on the coordinates of the signal wave center point of the second measurement mark 150 in the XY coordinate system and the coordinates of the signal wave center point of the first measurement mark 130 in the XY coordinate system, obtaining the overlay error between the second measurement mark 150 and the first measurement mark 130.

[0083] It should be noted that in the step of determining the coordinates of the center point of the signal wave of the second measurement mark 150 in the XY coordinate system and the coordinates of the center point of the signal wave of the first measurement mark 130 in the XY coordinate system, the coordinates of the center point of the signal wave of the first measurement mark 130 in the XY coordinate system are set to (X1, Y1), and the coordinates of the center point of the signal wave of the second measurement mark 150 in the XY coordinate system are set to (X2, Y2).

[0084] In this embodiment, obtaining the overlay error between the second measurement mark 150 and the first measurement mark 130 includes: obtaining the overlay error between the second measurement mark 150 and the first measurement mark 130 in the first direction (i.e., the X-axis); obtaining the overlay error between the second measurement mark 150 and the first measurement mark 130 in the second direction (i.e., the Y-axis).

[0085] As an example, the overlay error a=X2-X1 between the second measurement mark 150 and the first measurement mark 130 in the first direction (ie, the X-axis) is obtained; the overlay error b=Y2-Y1 between the second measurement mark 150 and the first measurement mark 130 in the second direction (ie, the Y-axis) is obtained.

[0086] Specifically, when a and b are both 0, it means that the second measurement mark 150 and the first measurement mark 130 are not offset in the first direction, and the second measurement mark 150 and the first measurement mark 130 are not offset in the second direction, which means that the first layer pattern of the wafer 100 to be tested has no overlay error. Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention, so the scope of protection of the present invention shall be based on the scope defined by the claims.

Claims

1. A semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer, characterized in that: include: A wafer to be tested, wherein the wafer to be tested comprises a measurement area; A first measurement mark, located in the measurement area, the first measurement mark includes a first strip structure extending along a first direction and facing each other, and a second strip structure extending along a second direction and facing each other, the first direction is perpendicular to the second direction, and the shape formed by the first strip structure facing each other and the second strip structure facing each other is a rectangle; The second measurement mark is located in the measurement area. The second measurement mark surrounds the first measurement mark. The shape formed by the second measurement mark is rectangular. There is a height difference between the top of the second measurement mark and the top of the first measurement mark.

2. The semiconductor structure according to claim 1, wherein: The first measurement mark includes an opening.

3. The semiconductor structure according to claim 1, wherein: An end of the first strip-shaped structure contacts an end of the second strip-shaped structure; Alternatively, the end of the first strip-shaped structure is separated from the end of the second strip-shaped structure.

4. The semiconductor structure according to claim 1, wherein: The second measurement mark includes a third strip structure extending along the first direction and facing each other, and a fourth strip structure extending along the second direction and facing each other, and an end of the third strip structure contacts an end of the fourth strip structure.

5. The semiconductor structure according to claim 4, characterized in that The distance between the outer boundary of the third strip structure and the first strip structure is between 4 micrometers and 10 micrometers; The distance between the outer boundary of the fourth strip structure and the second strip structure is between 4 micrometers and 10 micrometers.

6. The semiconductor structure according to claim 1, wherein: The semiconductor structure also includes: a first filling layer, located in an area enclosed by the first strip structure and the second strip structure facing each other, the top of the first filling layer is flush with the top of the second measurement mark, and the first filling layer and the second measurement mark are an integrated structure.

7. A method for forming a semiconductor structure, suitable for measuring the overlay error of the first layer pattern of a wafer, characterized in that: include: Providing a wafer to be tested, wherein the wafer to be tested includes a measurement area; A first measurement mark is formed in the measurement area, the first measurement mark includes a first strip structure extending in a first direction and facing each other, and a second strip structure extending in a second direction and facing each other, the first direction is perpendicular to the second direction, and the shape formed by the first strip structure facing each other and the second strip structure facing each other is a rectangle; A second measurement mark is formed in the measurement area to surround the first measurement mark. The shape formed by the second measurement mark is rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The first metrology mark and the second metrology mark are formed in the same step.

9. The method for forming a semiconductor structure according to claim 7, characterized in that: The steps of forming the first measurement mark and the second measurement mark include: forming a measurement mark material layer in the measurement area of ​​the first layer of the wafer; performing graphic processing on the measurement mark material layer, forming a first opening extending along a first direction and opposite to each other, and a second opening extending along a second direction and opposite to each other in the measurement mark material layer, the first direction is perpendicular to the second direction, the shape formed by the first opening opposite to each other and the second opening opposite to each other is rectangular, and the first opening and the second opening are used as the first measurement mark, and the remaining measurement mark material layer surrounding the first measurement mark is used as the second measurement mark.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: In the step of forming the first measurement mark and the second measurement mark, the remaining measurement mark material layer located in the area enclosed by the first opening and the second opening opposite to each other is used as a first filling layer, the top of the first filling layer is flush with the top of the second measurement mark, and the first filling layer and the second measurement mark are an integrated structure.

11. The method for forming a semiconductor structure according to claim 7, characterized in that: The distance between the outer boundary of the second measurement mark and the first strip structure in the first direction is between 4 micrometers and 10 micrometers; A distance between an outer boundary of the second measurement mark and the second strip structure in the second direction is between 4 micrometers and 10 micrometers.

12. A method for measuring overlay error, characterized in that: include: Providing a semiconductor structure according to any one of claims 1 to 6; Based on a height difference between a top of the second measurement mark and a top of the first measurement mark, obtaining a center point of a signal wave of the second measurement mark and a center point of a signal wave of the first measurement mark; An overlay error between the second measurement mark and the first measurement mark is obtained based on a center point of a signal wave of the second measurement mark and a center point of a signal wave of the first measurement mark.

13. The method for measuring overlay error according to claim 12, wherein: The steps of obtaining the center point of the signal wave of the second measurement mark and the center point of the signal wave of the first measurement mark include: scanning the first measurement mark and the second measurement mark by an electron beam emitted by a scanning electron microscope; obtaining images of the first measurement mark and the second measurement mark after the electron beam scanning; and obtaining the center point of the signal wave of the second measurement mark and the center point of the signal wave of the first measurement mark based on the images of the first measurement mark and the second measurement mark.

14. The method for measuring overlay error according to claim 12, wherein: The step of obtaining the overlay error between the second measurement mark and the first measurement mark based on the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark includes: establishing an XY coordinate system; determining the coordinates of the signal wave center point of the second measurement mark in the XY coordinate system and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system; obtaining the overlay error between the second measurement mark and the first measurement mark based on the coordinates of the signal wave center point of the second measurement mark in the XY coordinate system and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system.

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