Communication method and device of processor, electronic equipment and storage medium

Abstract

The invention provides a communication method and device of a processor, electronic equipment and a storage medium, and relates to the technical field of communication. The communication method of the processor comprises the following steps: acquiring data of a plurality of first services; determining a plurality of target sending GPIO pins without conflicts in the plurality of sending GPIO pins; and sending the data of the plurality of first services to the input ends of the plurality of bus transceivers by adopting the plurality of target sending GPIO pins, so that the plurality of bus transceivers respectively send the data of the plurality of first services to the plurality of external devices. A plurality of target sending GPIO pins in a processor are adopted to communicate with a plurality of bus transceivers, data of a plurality of first services can be simultaneously sent to a plurality of external devices through a plurality of target sending GPIO pins without conflicts and a plurality of bus transceivers, and the sending GPIO pins in the processor are adopted to carry out data transmission in the whole process. And the cost of communication between the processor and the peripheral through a plurality of buses is saved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication method, device, electronic device and storage medium of a processor. Background Art

[0002] In embedded systems, a large number of buses are used to interconnect devices. The general composition of buses includes "physical layer, link layer, and transport layer". In industrial control scenarios, buses are used in large quantities, and bus protocols are diverse. This brings challenges to the controller design of industrial control scenarios. It is difficult to find a processor that is suitable for multiple industrial embedded scenarios.

[0003] In the related technology, many peripherals communicate with the processor through multiple buses. For example, 5 buses are needed. The common method of flexibly implementing the bus is usually implemented by a module with parallel processing capabilities, such as an FPGA (Field-Programmable Gate Array) chip. The hardware of each bus is independent and does not affect each other.

[0004] However, in the related art, when a processor communicates with peripherals through multiple buses, additional chips need to be added, resulting in increased costs. Summary of the invention

[0005] The purpose of this application is to provide a communication method, device, electronic device and storage medium for a processor in order to solve the above-mentioned technical problems existing in the related technology in view of the deficiencies in the above-mentioned prior art.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a communication method of a processor, wherein the processor includes: a plurality of transmit input and output GPIO pins; the plurality of transmit GPIO pins are respectively communicatively connected to input ends of a plurality of bus transceivers, and the method includes:

[0008] Obtaining data of multiple first services;

[0009] Determine, among the plurality of transmitting GPIO pins, a plurality of target transmitting GPIO pins that do not conflict;

[0010] A plurality of the target sending GPIO pins are used to send a plurality of the data of the first services to the input ends of a plurality of the bus transceivers, so that the plurality of the bus transceivers send the plurality of the data of the first services to a plurality of external devices respectively.

[0011] Optionally, the processor further includes: a plurality of receiving GPIO pins, the plurality of receiving GPIO pins are respectively communicatively connected to receiving ends of the plurality of bus transceivers, and the method further includes:

[0012] The plurality of receiving GPIO pins are used to receive the data of the plurality of second services sent from the output ends of the plurality of bus transceivers.

[0013] Optionally, the using a plurality of the receiving GPIO pins to receive a plurality of second service data sent by output ends of a plurality of the bus transceivers comprises:

[0014] Using the plurality of receiving GPIO pins, data of the plurality of second services sent from the output ends of the plurality of bus transceivers are received according to the operating frequencies, delays and service priorities corresponding to the types of the plurality of second services.

[0015] Optionally, the using a plurality of the target sending GPIO pins to send a plurality of data of the first services to input ends of a plurality of the bus transceivers includes:

[0016] Using a plurality of the target sending GPIO pins, data of a plurality of the first services are sent to input ends of a plurality of the bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of the plurality of the first services.

[0017] Optionally, the service type includes: hard real-time service type, high real-time service type, and ordinary real-time service type;

[0018] The service priority of the hard real-time service type is higher than the service priority of the high real-time service type; and the service priority of the high real-time service type is higher than the service priority of the common real-time service type.

[0019] Optionally, the using a plurality of the receiving GPIO pins to receive a plurality of second service data sent by output ends of a plurality of the bus transceivers comprises:

[0020] According to the data of the multiple first services transmitted by the multiple sending GPIO pins and the data of the multiple second services transmitted by the multiple receiving GPIO pins, conflict detection is performed on the multiple sending GPIO pins to obtain a conflict detection result;

[0021] If the conflict detection result indicates that some of the sending GPIO pins among the multiple sending GPIO pins have conflicts, conflict indication information is sent to the bit switches corresponding to the some of the sending GPIO pins, so as to close the bit switches corresponding to the some of the sending GPIO pins based on the conflict indication information.

[0022] Optionally, determining, among the plurality of transmitting GPIO pins, a plurality of target transmitting GPIO pins without conflict comprises:

[0023] Determine whether multiple bit switches corresponding to the multiple sending GPIO pins are turned on;

[0024] If there is an unopened bit switch among the multiple bit switches corresponding to the multiple sending GPIO pins, turning off the sending GPIO pin corresponding to the unopened bit switch and the sending function corresponding to the target bus transceiver connected to the communication;

[0025] Among the transmission GPIO pins corresponding to the remaining turned-on bit switches, a plurality of target transmission GPIO pins are determined.

[0026] Optionally, after using the plurality of receiving GPIO pins to receive the data of the plurality of second services sent by the output ends of the plurality of bus transceivers, the method further comprises:

[0027] respectively determining whether the data of the plurality of second services are complete;

[0028] If complete, a confirmation signal is sent to a plurality of confirmation switches corresponding to the plurality of sending GPIO pins.

[0029] Optionally, the using a plurality of the target sending GPIO pins to send a plurality of data of the first services to input ends of a plurality of the bus transceivers includes:

[0030] If the bit switches corresponding to the multiple target sending GPIO pins are all turned on, and the multiple confirmation switches corresponding to the multiple target sending GPIO pins have received the confirmation signal, then the multiple target sending GPIO pins are used to send the data of the multiple first services to the input ends of the multiple bus transceivers.

[0031] In a second aspect, an embodiment of the present application further provides a communication device of a processor, wherein the processor includes: a plurality of transmit input and output GPIO pins; the plurality of transmit GPIO pins are respectively communicatively connected to input ends of a plurality of bus transceivers, and the device includes:

[0032] An acquisition module, used for acquiring data of multiple first services;

[0033] A determination module, used for determining, among the plurality of the transmitting GPIO pins, a plurality of target transmitting GPIO pins without conflict;

[0034] The sending module is used to use the multiple target sending GPIO pins to send the data of the multiple first services to the input ends of the multiple bus transceivers, so that the multiple bus transceivers send the data of the multiple first services to multiple external devices respectively.

[0035] Optionally, the processor further includes: a plurality of receiving GPIO pins, wherein the plurality of receiving GPIO pins are respectively communicatively connected to receiving ends of the plurality of bus transceivers, and the device further includes:

[0036] The receiving module is used to use the plurality of receiving GPIO pins to receive the data of the plurality of second services sent from the output ends of the plurality of bus transceivers.

[0037] Optionally, the receiving module is specifically used to use multiple receiving GPIO pins to receive data of multiple second services sent from the output ends of multiple bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of multiple second services.

[0038] Optionally, the sending module is specifically used to use multiple target sending GPIO pins to send data of multiple first services to input ends of multiple bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of multiple first services.

[0039] Optionally, the service type includes: hard real-time service type, high real-time service type, and ordinary real-time service type;

[0040] The service priority of the hard real-time service type is higher than the service priority of the high real-time service type; and the service priority of the high real-time service type is higher than the service priority of the common real-time service type.

[0041] Optionally, the receiving module is specifically used to perform conflict detection on the multiple sending GPIO pins according to the data of the multiple first services transmitted by the multiple sending GPIO pins and the data of the multiple second services transmitted by the multiple receiving GPIO pins to obtain a conflict detection result; if the conflict detection result indicates that there is a conflict among some of the multiple sending GPIO pins, conflict indication information is sent to the bit switches corresponding to the some of the sending GPIO pins, so as to close the bit switches corresponding to the some of the sending GPIO pins based on the conflict indication information.

[0042] Optionally, the determination module is specifically used to determine whether multiple bit switches corresponding to the multiple sending GPIO pins are turned on; if there are bit switches that are not turned on among the multiple bit switches corresponding to the multiple sending GPIO pins, then the sending GPIO pins corresponding to the unturned bit switches and the sending function corresponding to the target bus transceiver connected to the communication are turned off; and among the sending GPIO pins corresponding to the remaining turned-on bit switches, the multiple target sending GPIO pins are determined.

[0043] Optionally, the device further comprises:

[0044] A judging module, used to judge whether the data of the plurality of second services are complete;

[0045] The sending module is further configured to send a confirmation signal to a plurality of confirmation switches corresponding to the plurality of sending GPIO pins if the confirmation signal is complete.

[0046] Optionally, the sending module is specifically used to use multiple target sending GPIO pins to send data of multiple first services to the input ends of multiple bus transceivers if the bit switches corresponding to multiple target sending GPIO pins are all turned on and multiple confirmation switches corresponding to multiple target sending GPIO pins have received the confirmation signal.

[0047] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a memory and a processor, wherein the memory stores a computer program executable by the processor, and when the processor executes the computer program, the processor implements the communication method described in any one of the first aspects above.

[0048] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is read and executed, the communication method of the processor described in any one of the above-mentioned first aspects is implemented.

[0049] The beneficial effects of the present application are as follows: an embodiment of the present application provides a communication method for a processor, the processor comprising: a plurality of transmit input and output GPIO pins; the plurality of transmit GPIO pins are respectively connected to the input ends of a plurality of bus transceivers for communication, the method comprising: obtaining data of a plurality of first services; among the plurality of transmit GPIO pins, determining a plurality of target transmit GPIO pins without conflicts; using a plurality of target transmit GPIO pins to transmit data of a plurality of first services to the input ends of a plurality of bus transceivers, so that a plurality of bus transceivers respectively send the data of a plurality of first services to a plurality of external devices. By using a plurality of target transmit GPIO pins in the processor to communicate with a plurality of bus transceivers, the data of a plurality of first services can be simultaneously sent to a plurality of external devices through a plurality of target transmit GPIO pins without conflicts and a plurality of bus transceivers, without adding an additional chip, and the entire process uses the transmit GPIO pins in the processor for data transmission, saving the cost of the processor communicating with peripherals through a plurality of buses. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 1 ;

[0052] Figure 2 A schematic diagram of a system architecture based on a communication method of a processor provided in an embodiment of the present application;

[0053] Figure 3 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 2 ;

[0054] Figure 4 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 3 ;

[0055] Figure 5 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 4 ;

[0056] Figure 6 A schematic diagram of the structure of a communication device of a processor provided in an embodiment of the present application;

[0057] Figure 7A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0059] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0060] In the description of the present application, it should be noted that if the terms "upper", "lower", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the application is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0061] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0063] An embodiment of the present application provides a communication method of a processor, which is applied to a processor in an electronic device, wherein the processor includes: a plurality of transmitting GPIO (General Purpose Input Output) pins; the plurality of transmitting GPIO pins are respectively communicatively connected to input ends of a plurality of bus transceivers.

[0064] There is a one-to-one correspondence between the sending GPIO pin and the input end of the bus transceiver, that is, one sending GPIO pin is communicatively connected to one input end of the bus transceiver.

[0065] In some embodiments, there is a first group of GPIO pins in the processor, and the group of GPIO pins includes multiple GPIO pins. The first group of GPIO pins is configured as output, and then multiple GPIO pins in the first group of GPIO pins are configured as multiple transmitting GPIO pins, and each transmitting GPIO pin is connected to the input end of each bus transceiver.

[0066] The following is an explanation of a communication method of a processor provided in an embodiment of the present application.

[0067] Figure 1 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the method may include:

[0068] S101. Acquire data of multiple first services.

[0069] In some embodiments, data of multiple first services are read from a sending buffer, and the unit of measurement of the data of the multiple first services is byte; the data of the multiple first services are converted to obtain converted data of the multiple first services; the unit of the converted data of the multiple first services is bit.

[0070] It should be noted that the converted data of one first service is transmitted serially through the same target sending GPIO pin, and the converted data of different first services are transmitted serially through different target sending GPIO pins.

[0071] S102: Determine, among a plurality of transmitting GPIO pins, a plurality of target transmitting GPIO pins without conflict.

[0072] Wherein, a plurality of transmission GPIO pins are connected to a plurality of bus transceivers via a plurality of buses.

[0073] Optionally, the multiple buses may include a low-speed bus and / or a high-speed bus. For example, the low-speed bus may include at least one of the following: UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), IIC (IIC (Inter-Integrated Circuit) is actually the abbreviation of IICBus, so it should be called integrated circuit bus in Chinese). The high-speed bus may include at least one of the following: ETH (Ethernet is a computer network technology used to connect devices in a local area network and transmit data via cables or wirelessly), PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard).

[0074] In the embodiment of the present application, the conflicting transmission GPIO pins among the multiple transmission GPIO pins mean that the bus corresponding to the transmission GPIO pin is in an occupied state, and the bus corresponding to the transmission GPIO pin cannot be used to send data and transmit data. Therefore, it is necessary to determine the multiple target transmission GPIO pins among the multiple transmission GPIO pins that do not conflict, and the buses corresponding to these multiple target transmission GPIO pins are not in an occupied state, and data transmission can be performed.

[0075] S103, using multiple target sending GPIO pins to send multiple first service data to input ends of multiple bus transceivers, so that the multiple bus transceivers send the multiple first service data to multiple external devices respectively.

[0076] The multiple target sending GPIO pins may be all or part of the multiple sending GPIO pins.

[0077] In some implementations, when the number of multiple target transmission GPIO pins is greater than the number of multiple first services, target transmission GPIO pins equal to the number of multiple first services are determined from the multiple target transmission GPIO pins to transmit data of the multiple first services. When the number of multiple target transmission GPIO pins is less than the number of multiple first services, the multiple target transmission GPIO pins are used to transmit data of the multiple first services in batches according to the priorities of the multiple first services.

[0078] In actual applications, the data of the same first service is serially sent to the corresponding bus through the same target sending GPIO pin, and then transmitted through the bus to the input end of the bus transceiver that is communicatively connected to the target sending GPIO pin. The bus transceiver transmits the data of the first service to the bus controller, and the bus controller is used to send the data of the first service to the external device.

[0079] In summary, an embodiment of the present application provides a communication method for a processor, the processor comprising: a plurality of transmitting input and output GPIO pins; the plurality of transmitting GPIO pins are respectively connected to the input ends of a plurality of bus transceivers for communication, the method comprising: obtaining data of a plurality of first services; among the plurality of transmitting GPIO pins, determining a plurality of target transmitting GPIO pins without conflicts; using a plurality of target transmitting GPIO pins to transmit the data of a plurality of first services to the input ends of a plurality of bus transceivers, so that a plurality of bus transceivers respectively send the data of a plurality of first services to a plurality of external devices. By using a plurality of target transmitting GPIO pins in a processor to communicate with a plurality of bus transceivers, the data of a plurality of first services can be simultaneously sent to a plurality of external devices through a plurality of target transmitting GPIO pins without conflicts and a plurality of bus transceivers, without adding an additional chip, and the entire process uses the transmitting GPIO pins in the processor for data transmission, saving the cost of the processor communicating with peripherals through a plurality of buses.

[0080] Optionally, Figure 2 A schematic diagram of a system architecture based on a communication method of a processor provided in an embodiment of the present application, such as Figure 2 As shown, the processor may include: multiple sending GPIO pins such as GPIOA0 pin, GPIOA1 pin, GPIOA2 pin, GPIOA3 pin, GPIOA4 pin, etc. The multiple bus transceivers include: Can0, Can1, Can2, Can3, Can4. Among them, GPIOA0 pin, GPIOA1 pin, GPIOA2 pin, GPIOA3 pin, GPIOA4 pin are the first group of GPIO pins, which can be called GPIOA pins.

[0081] Among them, the GPIOA0 pin is connected to Can0T (T refers to the input end), the GPIOA1 pin is connected to Can1T, the GPIOA2 pin is connected to Can2T, the GPIOA3 pin is connected to Can3T, and the GPIOA4 pin is connected to Can4T.

[0082] certainly, Figure 2 This is only an example. In the embodiment of the present application, there is no specific limitation on the number of multiple transmitting GPIO pins and the number of multiple bus transceivers.

[0083] Optionally, the processor further includes: a plurality of receiving GPIO pins, the plurality of receiving GPIO pins are respectively communicatively connected to receiving ends of the plurality of bus transceivers, and the method further includes:

[0084] A plurality of receiving GPIO pins are used to receive a plurality of second service data sent from output ends of a plurality of bus transceivers.

[0085] In some implementations, the output ends of the multiple bus transceivers send the data of the multiple second services to the multiple receiving GPIO pins via the multiple buses, wherein the data of one second service is transmitted serially via the same bus transceiver and the same receiving GPIO pin.

[0086] In an embodiment of the present application, there is a second group of GPIO pins in the processor, and the second group of GPIO pins includes multiple GPIO pins. The second group of GPIO pins are configured as input, and then the multiple GPIO pins in the second group of GPIO pins are configured as multiple receiving GPIO pins, and each receiving GPIO pin is connected to the output end of each bus transceiver.

[0087] It should be noted that all transmit GPIO pins are mapped to the first group of GPIO pins, and all receive GPIO pins are mapped to the second group of GPIO pins. In this way, multiple transmit GPIO pins can be controlled to output bus waveforms at the same time, or multiple receive GPIO pins can be used to sample multiple buses at the same time.

[0088] like Figure 2 The processor may include: multiple transmission GPIO pins such as GPIOB0 pin, GPIOB1 pin, GPIOB2 pin, GPIOB3 pin, GPIOB4 pin, etc. Multiple bus transceivers include: Can0, Can1, Can2, Can3, Can4. Among them, GPIOB0 pin, GPIOB1 pin, GPIOB2 pin, GPIOB3 pin, GPIOB4 pin are the second group of GPIO pins, which can be called GPIOB pins.

[0089] Among them, the GPIOB0 pin is connected to Can0R (R refers to the input end), the GPIOB1 pin is connected to Can1R, the GPIOB2 pin is connected to Can2R, the GPIOB3 pin is connected to Can3R, and the GPIOB4 pin is connected to Can4R.

[0090] certainly, Figure 2 This is only an example. In the embodiment of the present application, there is no specific limitation on the number of multiple receiving GPIO pins and the number of multiple bus transceivers.

[0091] Optionally, the process of using multiple receiving GPIO pins to receive data of multiple second services sent by output ends of multiple bus transceivers may include:

[0092] A plurality of receiving GPIO pins are used to receive data of a plurality of second services sent from output ends of a plurality of bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of the plurality of second services.

[0093] In some implementations, the task of receiving data of multiple second services is a first hard real-time service, and its scheduling period is 1 / 5 of the minimum baud period of the external bus, that is, the scheduling period is 200ns (nanoseconds), and multiple receiving GPIO pins are uniformly controlled by the first hard real-time service. Figure 2 As shown, the first hard real-time service operates at the highest sampling rate through multiple receiving GPIO pins and parallel port input.

[0094] In addition, after receiving the data of the multiple second services, the data of the multiple second services may be filtered to obtain the filtered data of the multiple second services, wherein the filtering process may eliminate the interference of signal noise.

[0095] In an embodiment of the present application, unit conversion is performed on data of multiple second services received using multiple receiving GPIO pins, the unit of measurement of the data of the multiple second services is bit, the unit of measurement of the converted data of the multiple second services is byte, and the converted data of the multiple second services is output to a receiving buffer, and each receiving GPIO pin corresponds to a bit in the receiving buffer.

[0096] like Figure 2 As shown, the unit is converted from bit to byte, the number of the multiple second services may be 5, and the converted data of the obtained multiple service data include: B1byte (byte), B2byte, B3byte, B4byte, and B5byte.

[0097] Optionally, the process of using multiple target sending GPIO pins in the above S103 to send multiple first service data to the input ends of multiple bus transceivers may include:

[0098] Using multiple target sending GPIO pins, data of multiple first services are sent to input ends of multiple bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of multiple first services.

[0099] Among them, different business types correspond to different working frequencies, delays, and business priorities.

[0100] In the embodiment of the present application, the task of sending data of multiple first services is the second hard real-time task, the scheduling period is the minimum baud period of the external bus 1us (microseconds), and multiple target sending GPIO pins are uniformly controlled by the second hard real-time service. Figure 2 As shown, the second hard real-time service sends GPIO pins and outputs through multiple targets, working at the highest baud rate.

[0101] In an embodiment of the present application, the converted data units of the multiple first services are bits, each bit in the converted data of the multiple first services corresponds to a sending GPIO pin, and the data of the multiple first services in the sending buffer are output to multiple target sending GPIO pins.

[0102] like Figure 2 As shown, data of multiple first services are obtained from ordinary real-time services, high-level protocol frames, application layer tasks, etc. The unit of the data of multiple first services is byte. For example, the number of multiple first tasks is 5, including: B1byte, B2byte, B3byte, B4byte, B5byte. After the unit is converted from byte to bit, it is sent using multiple sending GPIO pins.

[0103] It should be noted that in the scenario where multiple buses exist at the same time, the key indicator of latency is usually affected by hardware resources and software resources. Among them, the impact of hardware resources mainly includes: processor processing speed, pin flip speed, etc. The impact of software resources mainly includes: OS (Operating System), scheduling algorithm, etc.

[0104] Therefore, whether it is a scenario in which multiple receiving GPIO pins receive data of multiple second services, or a scenario in which multiple target sending GPIO pins send data of multiple first services, the services are classified in the embodiments of the present application, and different operating frequencies, delays, and service priorities are used to transmit service data according to different service types, ensuring that different types of service data can be transmitted reliably and meet actual needs.

[0105] Optionally, the service type includes: a hard real-time service type, a high real-time service type, and a common real-time service type.

[0106] Among them, the service priority of hard real-time service type is higher than that of high real-time service type; the service priority of high real-time service type is higher than that of ordinary real-time service type. Hard real-time service is guaranteed by hardware real-time device, high real-time service runs without occupying processor in hardware implementation, and ordinary real-time service runs without occupying processor in hard real-time service and high real-time service.

[0107] In the embodiment of the present application, the services of the hard real-time service type include: data output, data collection and other services; the services of the high real-time service type include: conflict detection, ACK (Acknowledge character, confirmation character), error checking and integrity detection and other services; the services of the ordinary real-time service type include: message framing, message filtering, and retransmission control services.

[0108] In some implementations, the operating frequency of the hard real-time service is higher than the operating frequency of the high real-time service, and the maximum delay of the hard real-time service is lower than the maximum delay of the high real-time service. The ordinary real-time service is triggered by the high real-time service, and the operating frequency is flexible in terms of service packets. The operating frequency of the ordinary real-time service is lower than the operating frequency of the high real-time service. Figure 2 As shown, for high real-time services, the baud rate is used as the minimum working cycle.

[0109] For example, the operating frequency of hard real-time services can be 25 MHz (megahertz), and the maximum delay of hard real-time services can be 40 ns; the operating frequency of high real-time services can be 1 MHz, and the maximum delay of high real-time services can be 1 us; the operating frequency of ordinary real-time services is less than 1 MHz.

[0110] It should be noted that hard real-time services must be guaranteed first. This type of service mainly involves hardware operations and has a relatively simple function. In the embodiment of the present application, the highest priority of hard real-time services is guaranteed by hardware clock interrupts. Every time the clock arrives, the hard real-time service must be executed first.

[0111] Optionally, Figure 3 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 2 ,like Figure 3 As shown, multiple receiving GPIO pins are used to receive data of multiple second services sent by output ends of multiple bus transceivers, including:

[0112] S201. Perform conflict detection on multiple sending GPIO pins according to multiple first service data transmitted by multiple sending GPIO pins and multiple second service data transmitted by multiple receiving GPIO pins to obtain a conflict detection result.

[0113] The conflict detection result is used to indicate whether there is a conflicting transmission GPIO pin among the multiple transmission GPIO pins.

[0114] In some implementations, data of multiple first services output by multiple sending GPIO pins and data of multiple second services read by multiple receiving GPIO pins are compared to determine whether the two are equal, thereby obtaining conflict detection results for multiple sending GPIO pins.

[0115] S202: If the conflict detection result indicates that some of the transmitting GPIO pins among the multiple transmitting GPIO pins have conflicts, conflict indication information is sent to bit switches corresponding to some of the transmitting GPIO pins, so as to close the bit switches corresponding to some of the transmitting GPIO pins based on the conflict indication information.

[0116] Among them, part of the transmission GPIO pins can be: at least one transmission GPIO pin among multiple transmission GPIO pins. Figure 2 As shown, after multiple sending GPIO pins receive data of multiple first services, conflict detection is performed, and conflict indication information is sent to bit switches corresponding to some of the sending GPIO pins.

[0117] In the embodiment of the present application, each transmission GPIO pin has a corresponding bit switch. For the transmission GPIO pins with conflicts among the multiple transmission GPIO pins, a conflict indication can be sent to the transmission GPIO pins with conflicts, so that the bit switches corresponding to the transmission GPIO pins with conflicts can be turned off, and the transmission GPIO pins with conflicts will stop transmitting data. In this way, the transmission GPIO pins with conflicts can be prevented from participating in data transmission, making the method of transmitting data to multiple bus transceivers through multiple transmission GPIO pins more reliable.

[0118] Optionally, Figure 4 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 3 ,like Figure 4 As shown, the process of determining multiple target transmitting GPIO pins without conflicts among multiple transmitting GPIO pins in the above S102 may include:

[0119] S301, determining whether multiple bit switches corresponding to multiple sending GPIO pins are turned on.

[0120] It should be noted that, among the multiple transmission GPIO pins, the transmission GPIO pins that have conflicts have their bit switches turned off, and among the multiple transmission GPIO pins that have no conflicts, their bit switches are turned on. The bit switches are turned off based on the conflict indication.

[0121] S302: If there is an unopened bit switch among the multiple bit switches corresponding to the multiple transmitting GPIO pins, turn off the transmitting GPIO pin corresponding to the unopened bit switch and the transmitting function corresponding to the target bus transceiver connected to the communication.

[0122] In the embodiment of the present application, the transmission GPIO pin corresponding to the bit switch that is not turned on is the transmission GPIO pin in conflict. That is to say, the bus between the transmission GPIO pin in conflict and the target bus transceiver is in an occupied state. Turning off the transmission GPIO pin in conflict and the corresponding transmission function of the target bus transceiver can avoid the problem of unreliable data transmission caused by using the bus for data transmission when the bus corresponding to the target bus transceiver is occupied.

[0123] S303: Determine a plurality of target transmitting GPIO pins among the transmitting GPIO pins corresponding to the remaining turned-on bit switches.

[0124] It is worth noting that if the number of sending GPIO pins corresponding to the remaining turned-on bit switches is less than or equal to the number of multiple first services, the sending GPIO pins corresponding to the remaining turned-on bit switches are directly used as multiple target sending GPIO pins.

[0125] In addition, if the number of transmitting GPIO pins corresponding to the remaining turned-on bit switches is greater than the number of multiple first services, pins equal to the number of multiple first services are selected from the transmitting GPIO pins corresponding to the remaining turned-on bit switches as multiple target transmitting GPIO pins.

[0126] Optionally, Figure 5 A flow chart of a communication method of a processor provided in an embodiment of the present application Figure 4 ,like Figure 5 As shown, after the above process of using multiple receiving GPIO pins to receive data of multiple second services sent by output ends of multiple bus transceivers, the method may further include:

[0127] S401: Determine respectively whether data of multiple second services are complete.

[0128] The process of determining whether the data of multiple second services are complete belongs to the high real-time service type. For high real-time services, information within a single bit is processed, and a lightweight RTOS (Real Time Operate System) or bare core hardware can be used for triggering.

[0129] In some implementations, multiple receiving GPIO pins are used to read multiple bus transceivers through multiple buses to send multiple second service data; the data of multiple second services are in bits, and the data of multiple second services are simultaneously divided into multiple arrays to form receiving information corresponding to multiple buses, and the receiving information refers to the data of multiple second services in bytes. Wherein, the integrity check of the data is immediately performed after a byte is filled.

[0130] like Figure 2 As shown, after integrity check is performed on multiple second service data in bytes: B1byte, B2byte, B3byte, B4byte, B5byte, the process of ordinary real-time service, high-level protocol frame, application layer task and the like is entered.

[0131] It should be noted that the integrity of the data of multiple second services may be determined sequentially or simultaneously, or in other orders, and the embodiments of the present application do not impose any specific restrictions on this.

[0132] S402: If complete, send confirmation signals to multiple confirmation switches corresponding to multiple sending GPIO pins.

[0133] Each sending GPIO pin has a corresponding confirmation switch.

[0134] In the embodiment of the present application, there is a one-to-one correspondence between multiple transmitting GPIO pins and multiple receiving GPIO pins, and a transmitting GPIO pin and a GPIO pin with a corresponding relationship are respectively connected to the input end and the receiving end of the same bus transceiver.

[0135] It is worth noting that if the data of a second service received by a receiving GPIO pin is complete, a confirmation signal is sent to a confirmation switch corresponding to a sending GPIO pin having a corresponding relationship with the receiving GPIO pin. Conversely, if the data of a second service received by a receiving GPIO pin is incomplete, an error signal is sent to a confirmation switch corresponding to a sending GPIO pin having a corresponding relationship with the receiving GPIO pin.

[0136] Optionally, the process of using multiple target sending GPIO pins in the above S103 to send multiple first service data to the input ends of multiple bus transceivers may include:

[0137] If the bit switches corresponding to multiple target sending GPIO pins are all turned on, and the multiple confirmation switches corresponding to the multiple target sending GPIO pins all receive confirmation signals, the multiple target sending GPIO pins are used to send data of multiple first services to the input ends of multiple bus transceivers.

[0138] In an embodiment of the present application, when the bit switch corresponding to the target sending GPIO pin is turned on, it means that there is no conflict with the target sending GPIO pin, and the bus corresponding to the target sending GPIO pin is in an unoccupied state. When the confirmation switch corresponding to the target sending GPIO pin receives a confirmation signal, it means that the receiving GPIO pin that has a corresponding relationship with the target sending GPIO pin can accurately and completely receive the data transmitted by the bus transceiver through the bus. By sampling such multiple target sending GPIO pins and sending multiple first business data to the input end of multiple bus transceivers through multiple buses, efficient, accurate and reliable parallel transmission of multiple first business data can be achieved.

[0139] In summary, in the embodiment of the present application, the same functions of multiple buses are designed into the same module, and multiple GPIO pins of the processor are used as the sending hardware of multiple buses, so that the sending or receiving of multiple bus signals can be realized at the same time. In addition, multiple parameters can be operated at the same time using the simd instruction (Single Instruction Multiple Data, a parallel instruction). For example, when multiple receiving GPIO pins receive multiple complete bytes of data of the second task, these data can be added to each array at the same time.

[0140] Moreover, according to the different real-time requirements of the bus protocol, the functional modules are split into hard real-time services (data output, data sampling), high real-time services (conflict detection, response ACK, error checking), and ordinary real-time tasks (message framing, message filtering, and resending control). The task scheduling scheme is designed to ensure the real-time requirements of tasks of various priorities. At the same time, the processor's GPIO group contains multiple pins, and the SIMD instruction simultaneously operates multiple operands. The characteristics of the operation of multiple data lines at the same time are used to realize the real-time requirements of multiple buses and maximize the processor's capabilities.

[0141] The following describes a communication device, electronic device, and storage medium of a processor used to execute the communication method of the processor provided in this application. The specific implementation process and technical effects thereof refer to the relevant contents of the communication method of the above-mentioned processor, which will not be repeated below.

[0142] Figure 6 A schematic diagram of a communication device of a processor provided in an embodiment of the present application, wherein the processor comprises: a plurality of transmit input and output GPIO pins; the plurality of transmit GPIO pins are respectively connected to the input ends of a plurality of bus transceivers for communication, such as Figure 6 As shown, the device comprises:

[0143] The device comprises:

[0144] An acquisition module 101 is used to acquire data of a plurality of first services;

[0145] A determination module 102 is used to determine, among the plurality of transmission GPIO pins, a plurality of target transmission GPIO pins that do not conflict;

[0146] The sending module 103 is used to use the multiple target sending GPIO pins to send the data of the multiple first services to the input ends of the multiple bus transceivers, so that the multiple bus transceivers send the data of the multiple first services to multiple external devices respectively.

[0147] Optionally, the processor further includes: a plurality of receiving GPIO pins, wherein the plurality of receiving GPIO pins are respectively communicatively connected to receiving ends of the plurality of bus transceivers, and the device further includes:

[0148] The receiving module is used to use the plurality of receiving GPIO pins to receive the data of the plurality of second services sent from the output ends of the plurality of bus transceivers.

[0149] Optionally, the receiving module is specifically used to use multiple receiving GPIO pins to receive data of multiple second services sent from the output ends of multiple bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of multiple second services.

[0150] Optionally, the sending module 103 is specifically used to use multiple target sending GPIO pins to send data of multiple first services to input ends of multiple bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of multiple first services.

[0151] Optionally, the service type includes: hard real-time service type, high real-time service type, and ordinary real-time service type;

[0152] The service priority of the hard real-time service type is higher than the service priority of the high real-time service type; and the service priority of the high real-time service type is higher than the service priority of the common real-time service type.

[0153] Optionally, the receiving module is specifically used to perform conflict detection on the multiple sending GPIO pins according to the data of the multiple first services transmitted by the multiple sending GPIO pins and the data of the multiple second services transmitted by the multiple receiving GPIO pins to obtain a conflict detection result; if the conflict detection result indicates that there is a conflict among some of the multiple sending GPIO pins, conflict indication information is sent to the bit switches corresponding to the some of the sending GPIO pins, so as to close the bit switches corresponding to the some of the sending GPIO pins based on the conflict indication information.

[0154] Optionally, the determination module 102 is specifically used to determine whether multiple bit switches corresponding to the multiple sending GPIO pins are turned on; if there are unturned bit switches among the multiple bit switches corresponding to the multiple sending GPIO pins, then the sending GPIO pins corresponding to the unturned bit switches and the sending function corresponding to the target bus transceiver connected to the communication are turned off; and among the sending GPIO pins corresponding to the remaining turned-on bit switches, the multiple target sending GPIO pins are determined.

[0155] Optionally, the device further comprises:

[0156] A judging module, used to judge whether the data of the plurality of second services are complete;

[0157] The sending module 103 is further configured to send a confirmation signal to a plurality of confirmation switches corresponding to the plurality of sending GPIO pins if the confirmation signal is complete.

[0158] Optionally, the sending module 103 is specifically used to use multiple target sending GPIO pins to send multiple data of the first services to the input ends of multiple bus transceivers if the bit switches corresponding to multiple target sending GPIO pins are all turned on and multiple confirmation switches corresponding to multiple target sending GPIO pins have received the confirmation signal.

[0159] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0160] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital singnal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0161] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the electronic device may include: a processor 201 and a memory 202 .

[0162] The memory 202 is used to store programs, and the processor 201 calls the programs stored in the memory 202 to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0163] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute the above method embodiment when executed by a processor.

[0164] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0165] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0166] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0167] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: Random Access Memory, abbreviated: RAM), disk or optical disk and other media that can store program codes.

[0168] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A communication method for a processor, characterized in that: The processor includes: a plurality of transmission input and output GPIO pins; the plurality of transmission GPIO pins are respectively connected to the input ends of a plurality of bus transceivers for communication, and the method includes: Obtaining data of multiple first services; Determine, among the plurality of transmitting GPIO pins, a plurality of target transmitting GPIO pins that do not conflict; A plurality of the target sending GPIO pins are used to send a plurality of the data of the first services to the input ends of a plurality of the bus transceivers, so that the plurality of the bus transceivers send the plurality of the data of the first services to a plurality of external devices respectively.

2. The method according to claim 1, characterized in that The processor further includes: a plurality of receiving GPIO pins, wherein the plurality of receiving GPIO pins are respectively communicatively connected to the receiving ends of the plurality of bus transceivers, and the method further includes: The plurality of receiving GPIO pins are used to receive the data of the plurality of second services sent from the output ends of the plurality of bus transceivers.

3. The method according to claim 2, characterized in that The step of using the plurality of receiving GPIO pins to receive the data of the plurality of second services sent by the output ends of the plurality of bus transceivers comprises: Using the plurality of receiving GPIO pins, data of the plurality of second services sent from the output ends of the plurality of bus transceivers are received according to the operating frequencies, delays and service priorities corresponding to the types of the plurality of second services.

4. The method according to claim 1, characterized in that: The step of using the plurality of target sending GPIO pins to send the plurality of data of the first services to the input ends of the plurality of bus transceivers comprises: Using a plurality of the target sending GPIO pins, data of a plurality of the first services are sent to input ends of a plurality of the bus transceivers according to the operating frequencies, delays and service priorities corresponding to the types of the plurality of the first services.

5. The method according to claim 3 or 4, characterized in that: The service types include: hard real-time service type, high real-time service type, and ordinary real-time service type; The service priority of the hard real-time service type is higher than the service priority of the high real-time service type; and the service priority of the high real-time service type is higher than the service priority of the common real-time service type.

6. The method according to claim 2, characterized in that The step of using the plurality of receiving GPIO pins to receive the data of the plurality of second services sent by the output ends of the plurality of bus transceivers comprises: According to the data of the multiple first services transmitted by the multiple sending GPIO pins and the data of the multiple second services transmitted by the multiple receiving GPIO pins, conflict detection is performed on the multiple sending GPIO pins to obtain a conflict detection result; If the conflict detection result indicates that some of the sending GPIO pins among the multiple sending GPIO pins have conflicts, conflict indication information is sent to the bit switches corresponding to the some of the sending GPIO pins, so as to close the bit switches corresponding to the some of the sending GPIO pins based on the conflict indication information.

7. The method according to claim 6, characterized in that The step of determining, among the plurality of transmitting GPIO pins, a plurality of target transmitting GPIO pins without conflict comprises: Determine whether multiple bit switches corresponding to the multiple sending GPIO pins are turned on; If there is an unopened bit switch among the multiple bit switches corresponding to the multiple sending GPIO pins, turning off the sending GPIO pin corresponding to the unopened bit switch and the sending function corresponding to the target bus transceiver connected to the communication; Among the transmission GPIO pins corresponding to the remaining turned-on bit switches, a plurality of target transmission GPIO pins are determined.

8. The method according to claim 7, characterized in that After using the plurality of receiving GPIO pins to receive the data of the plurality of second services sent by the output ends of the plurality of bus transceivers, the method further comprises: respectively determining whether the data of the plurality of second services are complete; If complete, a confirmation signal is sent to a plurality of confirmation switches corresponding to the plurality of sending GPIO pins.

9. The method according to claim 8, characterized in that The step of using the plurality of target sending GPIO pins to send the plurality of data of the first services to the input ends of the plurality of bus transceivers comprises: If the bit switches corresponding to the multiple target sending GPIO pins are all turned on, and the multiple confirmation switches corresponding to the multiple target sending GPIO pins have received the confirmation signal, then the multiple target sending GPIO pins are used to send the data of the multiple first services to the input ends of the multiple bus transceivers.

10. A communication device for a processor, characterized in that: The processor includes: a plurality of transmission input and output GPIO pins; the plurality of transmission GPIO pins are respectively connected to the input ends of a plurality of bus transceivers for communication, and the device includes: An acquisition module, used for acquiring data of multiple first services; A determination module, used for determining, among the plurality of the transmitting GPIO pins, a plurality of target transmitting GPIO pins without conflict; The sending module is used to use the multiple target sending GPIO pins to send the data of the multiple first services to the input ends of the multiple bus transceivers, so that the multiple bus transceivers send the data of the multiple first services to multiple external devices respectively.

11. An electronic device, characterized in that: include: A memory and a processor, wherein the memory stores a computer program executable by the processor, and when the processor executes the computer program, the communication method of the processor described in any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is read and executed, the communication method of the processor described in any one of claims 1 to 9 is implemented.

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