Verification system and method for end-to-end access ECC protection in system-on-chip

Abstract

The invention relates to an end-to-end access ECC protection verification system and method in a system-on-chip, a UVM simulation test platform special for ECC protection verification is created based on a UVM verification methodology, and an AHB host agent component not only takes over a main device to realize output of a control signal, but also takes over an auxiliary device to realize ECC protection verification. And meanwhile, an input signal received by the main equipment is monitored to realize the purpose of flexibly controlling the main equipment to send excitation. A developed port connection and driving function can be flexibly switched and connected with different hosts through the same AHB host agent component, complex configuration processes of different main devices are omitted, and the purpose of efficiently, extendibly and flexibly controlling multiple types and a large number of main devices to send excitation is achieved. The ECC protection of the end-to-end access in the system chip can be fully verified, and the purposes of greatly reducing the workload in the verification process and shortening the verification period are achieved, so that the high-performance end-to-end ECC verification in the system chip is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip verification, and relates to a verification system and method for end-to-end access ECC protection in a system chip. Background Art

[0002] The master devices (such as processor cores, DMA controllers, etc.) and slave devices (such as memory, peripherals, etc.) in the system on chip (SOC) realize the access interaction of data, instructions and addresses between the master and slave devices through the bus matrix (OCN, On-Chip Network). As the complexity of SOC continues to increase, the interaction between master and slave devices is becoming more and more complex. Integrating the Error Correcting Code (ECC) module on the master and slave devices can effectively protect the integrity of the data during the transmission process from the access initiator to the access responder. Initiate multi-scenario end-to-end access in the SOC and inject errors in the access path. Check whether the ECC modules at the access initiator and access responder can correct or detect the received erroneous data (1bit or 2bit), and verify whether the ECC module's signal connection and protection functions are correct.

[0003] The processor core needs to write a corresponding C program to initiate an access request, and the DMA controller of the master device needs the processor core to configure its parameters and wait for the triggering of the peripheral transfer request before generating end-to-end multiple data transfers between the DMA controller and the two slave devices. The configuration for initiating transmission in the above end-to-end access is specific and difficult to reuse, and the simulation takes a long time. Therefore, a high-performance verification ECC technology for initiating end-to-end access that is efficient, scalable, and flexibly controllable is needed. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a verification system for end-to-end access to ECC protection in a system chip and a verification method for end-to-end access to ECC protection in a system chip, which can realize high-performance end-to-end ECC verification in a system chip.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a verification system for end-to-end access ECC protection in a system chip is provided, including a top-level file based on UVM verification methodology, the top-level file is used to initialize the verification system and start the test case; The top-level file includes test cases based on the test case base class extension, port connection and driver functions developed based on Verilog language and AHB protocol, 32-bit AHB host agent components, 64-bit AHB host agent components, and system chip components instantiated based on the design code of the system chip under test. The system chip components include processor cores, DMA controllers, bus matrices, and slave devices. The parameters of the port connection and driver functions include the name of the master device, the register address of the slave device, read and write instructions, preset data, and data bit width. Each processor core and each DMA controller connects to each slave device through a bus matrix, and each processor core and each DMA controller are master devices. The port connection and driver function is used to select the interface of the AHB host agent component corresponding to the data bit width according to the name of the master device, and after forcibly connecting it with the master device bus port through the force function, the read and write access requests in the test case are sent to the output port of the master device currently being accessed through the interface of the AHB host agent component according to the timing requirements of the bus protocol, so that the master device initiates the access request and monitors the bus response signal received by the master device during the transmission, and checks whether the ECC module of the master and slave devices in the current access can correctly correct the 1-bit error and detect the 2-bit error of the received data, thereby completing the functional verification of the ECC module of the master and slave devices in the current access; After the current access is completed, the port connection and driver function is also used to release the interface connection between the master device bus port and the AHB host agent component through the release function, establish the connection between the interface of the AHB host agent component for the next access and the master device bus port through the force function, and switch to the functional verification of the ECC modules corresponding to the next group of master and slave devices until the functional verification of the ECC modules corresponding to all master and slave devices is completed.

[0006] On the other hand, a verification method for end-to-end access to ECC protection in a system chip is also provided, which is applied to a verification system for end-to-end access to ECC protection in a system chip, wherein the verification system includes a top-level file based on UVM verification methodology, and the top-level file is used to initialize the verification system and start test cases; the top-level file includes a test case based on a test case base class extension, a port connection and driver function developed based on Verilog language and AHB protocol, a 32-bit AHB host agent component, a 64-bit AHB host agent component, and a system chip component instantiated based on the design code of the system chip under test, and the system chip component includes each processor core, each DMA controller, a bus matrix, and each slave device; the parameters of the port connection and driver function include the name of the master device, the register address of the slave device, the read and write instructions, the preset data, and the data bit width, each processor core and each DMA controller are connected to each slave device through the bus matrix, and each processor core and each DMA controller are each master device; The method for verifying end-to-end access ECC protection in a system chip comprises the steps of: Through the port connection and driver function, the interface of the AHB host agent component corresponding to the data bit width is selected according to the name of the master device and the master device bus port is forcibly connected through the force function; Send the read and write access requests in the test case to the output port of the currently accessed master device through the interface of the AHB host agent component according to the timing requirements of the bus protocol and monitor the bus response signal received by the master device during the transmission; Check whether the ECC modules of the master and slave devices in the current access can correctly correct 1-bit errors and detect 2-bit errors in the received data; After the current access is completed, the interface connection between the master device bus port and the AHB host agent component is released through the port connection and driver function through the release function; The connection between the interface of the AHB host agent component to be accessed next time and the bus port of the master device is established through the force function, and the function verification of the ECC modules corresponding to the next group of master and slave devices is switched to until the function verification of the ECC modules corresponding to all master and slave devices is completed.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The verification system and method for end-to-end access ECC protection in the above-mentioned system chip creates a UVM simulation test platform dedicated to ECC protection verification based on UVM verification methodology, wherein the AHB host agent component not only takes over the main device to realize the output of the control signal, but also monitors the input signal received by the main device to realize the purpose of flexibly controlling the main device to send excitation. The developed port connection and driver function can flexibly switch to connect different hosts through the same set of AHB host agent components, eliminating the complex configuration process of different main devices, and realizing the purpose of efficiently, scalably and flexibly controlling multiple types and a large number of main devices to send excitations, which can fully verify the ECC protection of end-to-end access in the system chip, and achieve the purpose of greatly reducing the workload of the verification process and shortening the verification cycle, thereby realizing high-performance end-to-end ECC verification in the system chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1A structural block diagram of a verification system for end-to-end access to ECC protection in a system chip in one embodiment; Figure 2 A block diagram of a verification workflow of a verification system for end-to-end access to ECC protection in a system chip in one embodiment; Figure 3 FIG. 1 is a flow chart of a method for verifying end-to-end access ECC protection in a system chip in one embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] In one embodiment, Figure 1As shown, a verification system for end-to-end access ECC protection in a system chip is provided, including a top-level file based on UVM verification methodology, and the top-level file is used to initialize the verification system and start the test case. The top-level file includes a test case based on the test case base class extension, a port connection and driver function developed based on the Verilog language and the AHB protocol, a 32-bit AHB host agent component, a 64-bit AHB host agent component, and a system chip component instantiated based on the design code of the system chip under test. The system chip component includes each processor core, each DMA controller, a bus matrix, and each slave device. The parameters of the port connection and driver function include the name of the master device, the register address of the slave device, the read and write instructions, the preset data, and the data bit width. Each processor core and each DMA controller are connected to each slave device through a bus matrix, and each processor core and each DMA controller are each master device.

[0014] The port connection and driver function is used to select the interface of the AHB host agent component corresponding to the data bit width according to the name of the master device, and after forcing the connection with the master device bus port through the force function, the read and write access requests in the test case are sent to the output port of the master device currently being accessed through the interface of the AHB host agent component according to the timing requirements of the bus protocol, so that the master device initiates the access request and monitors the bus response signal received by the master device during the transmission, and checks whether the ECC module of the master and slave devices in the current access can correctly correct the 1-bit error and detect the 2-bit error of the received data, thereby completing the functional verification of the ECC module of the master and slave devices in the current access.

[0015] After the current access is completed, the port connection and driver function is also used to release the interface connection between the master device bus port and the AHB host agent component through the release function, establish the connection between the interface of the AHB host agent component for the next access and the master device bus port through the force function, and switch to the functional verification of the ECC modules corresponding to the next group of master and slave devices until the functional verification of the ECC modules corresponding to all master and slave devices is completed.

[0016] It can be understood that the design of each component in the verification system for end-to-end access to ECC protection in the above-mentioned system chip follows the existing UVM verification methodology. According to the detailed verification needs of the ECC protection function, the verification system is built based on the UVM verification platform to configure the components of the corresponding functions, and complete the connection between the components, connectivity testing and other basic operations to ensure normal data flow between the components during the verification process.

[0017] It can be understood that this embodiment creates Figure 1The UVM simulation test platform shown includes a top-level (simulation) file based on the UVM verification methodology. The top-level file is used to initialize the verification system and start the test case. The top-level file includes test cases based on the test case base class extension, port connection and driver functions developed based on the Verilog language and AHB protocol, 32-bit AHB host agent components, 64-bit AHB host agent components, and system chip components instantiated based on the design code of the SOC under test. The system chip components include each processor core (such as core 0 and core 1), each DMA controller (such as DMAC0 to DMACn, n is an integer not less than 2), a bus matrix and each slave device (such as peripheral 0 and peripheral 1, etc., and storage 0 and storage 1, etc.), and each processor core and each DMA controller are master devices. Among them, the test case can communicate with the system chip component through the 32-bit AHB host agent component and the 64-bit AHB host agent component respectively. In the simulation verification, the UVM simulation test platform can synchronously capture and annotate the transmission data signal inside the system chip component.

[0018] The parameters of the port connection and driver function include the name of the master device, the register address of the slave device, read and write instructions, preset data, data bit width and other parameters. The port connection and driver function will select the interface of the AHB host agent component (such as the 32-bit AHB host agent component or the 64-bit AHB host agent component) corresponding to the data bit width according to the name of the master device, and force the connection with the bus port of the master device through the force function (a built-in function in Verilog), so as to send the access request in the test case to the output port of the master device through the interface of the AHB host agent component according to the timing requirements of the bus protocol, so as to realize the master device initiating the read and write access request, and monitor the bus response signal received by the master device in the transmission, and randomly invert the 1bit or 2bit of the transmitted data in the access path to check whether the ECC module can correctly correct the 1bit error and detect the 2bit error of the write / read data, and complete the functional verification of the ECC module at the data receiving end in the scenario of the current test case. After the current access is completed, the release function (a built-in function in Verilog) is used to release the connection between the master device bus port and the AHB host agent component interface, and the connection between the interface of the AHB host agent component for the next access and the master device bus port is established referring to the above process to switch to the functional verification of the ECC modules corresponding to the next group of master and slave devices until the functional verification of the ECC modules corresponding to all master and slave devices is completed.

[0019] The verification system for end-to-end access to ECC protection in the above-mentioned system chip creates a UVM simulation test platform dedicated to ECC protection verification based on UVM verification methodology, wherein the AHB host agent component not only takes over the master device to realize the output of the control signal, but also monitors the input signal received by the master device to realize the purpose of flexibly controlling the master device to send excitation. The developed port connection and driver function can flexibly switch to connect different hosts through the same set of AHB host agent components, eliminating the complex configuration process of different master devices, and realizing the purpose of efficiently, scalably and flexibly controlling multiple types and a large number of master devices to send excitations, which can fully verify the ECC protection of end-to-end access in the system chip, and achieve the purpose of greatly reducing the workload of the verification process and shortening the verification cycle, thereby realizing high-performance end-to-end ECC verification in the system chip.

[0020] In one embodiment, the 32-bit AHB host agent component and the 64-bit AHB host agent component both include a driver, a monitor and an interface. The driver is used to send an end-to-end access request to the output port of the master device through the interface according to the timing requirements of the bus protocol under the drive of the port connection and driver function. The monitor is used to monitor the bus response signal received by the master device during transmission, and check whether the ECC module of the master and slave devices in the current access can correctly correct the 1-bit error and detect the 2-bit error of the received data.

[0021] It can be understood that both the 32-bit AHB host agent component and the 64-bit AHB host agent component are composed of a driver, a monitor and an interface, which are respectively used to work with the port connection and the driver function to drive the takeover and monitoring of the connected host device. The 32-bit AHB host agent component corresponds to the driver's access to each processor core and ECC verification, and correspondingly, the 64-bit AHB host agent component corresponds to the driver's access to each DMA controller and ECC verification. The number of each DMA controller can be set according to the number of DMA controllers actually carried by the SOC under test.

[0022] like Figure 2 As shown, the overall verification workflow of the verification system for end-to-end access to ECC protection in the above-mentioned system chip may include the following steps: Complete the creation of the UVM simulation test platform and the design code instantiation of the SOC under test.

[0023] Based on the bus architecture information of the SOC under test, build test cases for all end-to-end path data transmission.

[0024] According to the test case scenario, the interface between the master device bus port and the AHB host agent component is forced to be connected through port connection and driver functions.

[0025] According to the scenario of the test case, the interface of the AHB host agent component is driven by the port connection and the driver function to send end-to-end access requests according to the timing requirements of the bus protocol.

[0026] During the transmission process, a 1-bit or 2-bit flip is randomly triggered on the data signal in the access path.

[0027] The connection between the master device bus port and the interface of the AHB host agent component is released to disconnect the AHB host agent component from taking over the master device bus port.

[0028] For write data transmission, check the error injection at the data initiator (access initiator) and whether the ECC module at the data access receiver (access responder) can correctly correct 1-bit errors and detect 2-bit errors of the write data; for read data transmission, check the error injection at the data initiator (access responder) and whether the ECC module at the data access receiver (access initiator) can correctly correct 1-bit errors and detect 2-bit errors of the read data.

[0029] According to the verification scenario, the connection between the bus port of different master devices and the interface of the AHB host agent component is switched to establish the next set of error detection connections, from initiating a new driver access to ending the simulation after the stimulus driver ends.

[0030] Each component in the end-to-end access ECC protection verification system in the above system chip can be fully or partially implemented by software, hardware and their combination. The above components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the above device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. The above device can be but not limited to various types of chip verification computers available in the art.

[0031] In one embodiment, a verification method for end-to-end access to ECC protection in a system chip is provided, which is applied to the verification system for end-to-end access to ECC protection in the above-mentioned system chip, and is applied to a verification system for end-to-end access to ECC protection in a system chip, the verification system includes a top-level file based on UVM verification methodology, and the top-level file is used to initialize the verification system and start the test case. The top-level file includes a test case based on the test case base class extension, a port connection and driver function developed based on the Verilog language and the AHB protocol, a 32-bit AHB host agent component, a 64-bit AHB host agent component, and a system chip component instantiated based on the design code of the system chip under test, and the system chip component includes each processor core, each DMA controller, a bus matrix, and each slave device. The parameters of the port connection and driver function include the name of the master device, the register address of the slave device, the read and write instructions, the preset data, and the data bit width. Each processor core and each DMA controller are connected to each slave device through a bus matrix, and each processor core and each DMA controller are each master device.

[0032] like Figure 3 As shown, the verification method for end-to-end access ECC protection in the above system chip may include the following steps S10 to S18: S10, selecting the interface of the AHB host agent component corresponding to the data bit width according to the name of the master device through the port connection and driver function and forcibly connecting it with the master device bus port through the force function; S12, sending the read and write access requests in the test case to the output port of the master device currently being accessed through the interface of the AHB host agent component according to the timing requirements of the bus protocol and monitoring the bus response signal received by the master device during the transmission; S14, checking whether the ECC modules of the master and slave devices in the current access can correctly correct 1-bit errors and detect 2-bit errors of the received data; S16, after the current access is completed, the interface connection between the master device bus port and the AHB host agent component is released through the port connection and the driver function through the release function; S18, establish the connection between the interface of the AHB host agent component to be accessed next time and the bus port of the master device through the force function, and switch to the functional verification of the ECC modules corresponding to the next group of master and slave devices until the functional verification of the ECC modules corresponding to all master and slave devices is completed.

[0033] The verification method for end-to-end access ECC protection in the above-mentioned system chip creates a UVM simulation test platform dedicated to ECC protection verification based on UVM verification methodology, wherein the AHB host agent component not only takes over the master device to realize the output of the control signal, but also monitors the input signal received by the master device to realize the purpose of flexibly controlling the master device to send excitation. The developed port connection and driver function can flexibly switch to connect different hosts through the same set of AHB host agent components, eliminating the complex configuration process of different master devices, and realizing the purpose of efficiently, scalably and flexibly controlling multiple types and a large number of master devices to send excitations, which can fully verify the ECC protection of end-to-end access in the system chip, and achieve the purpose of greatly reducing the workload of the verification process and shortening the verification cycle, thereby realizing high-performance end-to-end ECC verification in the system chip.

[0034] In one embodiment, after the above step S12, the verification method for end-to-end access ECC protection in the above system chip may further include the following processing steps: Check the injection error of the data initiator in the current access, and whether the ECC module of the data access receiving end can correctly correct the 1-bit error of the transmitted data and detect the 2-bit error.

[0035] In one embodiment, the 32-bit AHB host agent component and the 64-bit AHB host agent component both include a driver, a monitor and an interface. The driver is used to send an end-to-end access request to the output port of the master device through the interface according to the timing requirements of the bus protocol under the drive of the port connection and driver function. The monitor is used to monitor the bus response signal received by the master device during transmission, and check whether the ECC module of the master and slave devices in the current access can correctly correct the 1-bit error and detect the 2-bit error of the received data.

[0036] For specific limitations on the verification method for end-to-end access to ECC protection in a system chip, please refer to the corresponding limitations on the verification system for end-to-end access to ECC protection in a system chip above, which will not be repeated here.

[0037] It should be understood that although Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 3At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0038] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0039] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A verification system for end-to-end access to ECC protection in a system chip, characterized in that: Including a top-level file based on UVM verification methodology, the top-level file is used to initialize the verification system and start the test case; The top-level file includes test cases based on the test case base class extension, port connection and driver functions developed based on Verilog language and AHB protocol, 32-bit AHB host agent components, 64-bit AHB host agent components and system chip components instantiated based on the design code of the system chip under test, the system chip components include processor cores, DMA controllers, bus matrices and slave devices; the parameters of the port connection and driver functions include the name of the master device, the register address of the slave device, read and write instructions, preset data and data bit width, the processor cores and DMA controllers are connected to the slave devices through the bus matrix, and the processor cores and DMA controllers are master devices; The port connection and driving function is used to select the interface of the AHB host agent component corresponding to the data bit width according to the name of the master device and forcibly connect it with the master device bus port through the force function, and then send the read and write access request in the test case to the output port of the master device currently being accessed through the interface of the AHB host agent component according to the timing requirements of the bus protocol, so that the master device initiates the access request and monitors the bus response signal received by the master device during the transmission, and checks whether the ECC module of the master and slave devices currently being accessed can correctly correct the 1-bit error and detect the 2-bit error of the received data, so as to complete the functional verification of the ECC module of the master and slave devices currently being accessed; After the current access is completed, the port connection and driver function is also used to release the interface connection between the master device bus port and the AHB host agent component through the release function, establish the connection between the interface of the AHB host agent component for the next access and the master device bus port through the force function, and switch to the functional verification of the ECC modules corresponding to the next group of master and slave devices until the functional verification of the ECC modules corresponding to all master and slave devices is completed.

2. The system for verifying end-to-end access to ECC protection in a system chip according to claim 1, characterized in that: The 32-bit AHB host agent component and the 64-bit AHB host agent component both include a driver, a monitor and an interface. The driver is used to send an end-to-end access request to the output port of the master device through the interface according to the timing requirements of the bus protocol under the drive of the port connection and driver function. The monitor is used to monitor the bus response signal received by the master device during transmission, and check whether the ECC modules of the master and slave devices in the current access can correctly correct 1-bit errors and detect 2-bit errors of the received data.

3. A method for verifying end-to-end access ECC protection in a system chip, characterized in that: The invention is applied to a verification system for end-to-end access ECC protection in a system chip. The verification system comprises a top-level file based on UVM verification methodology, and the top-level file is used to initialize the verification system and start test cases. The top-level file comprises a test case based on a test case base class extension, a port connection and driver function developed based on Verilog language and AHB protocol, a 32-bit AHB host agent component, a 64-bit AHB host agent component, and a system chip component instantiated based on the design code of the system chip under test. The system chip component comprises processor cores, DMA controllers, a bus matrix, and slave devices. The parameters of the port connection and driver function comprise the name of the master device, the register address of the slave device, read and write instructions, preset data, and data bit width. The processor cores and DMA controllers are connected to the slave devices through the bus matrix, and the processor cores and DMA controllers are master devices. The method for verifying end-to-end access ECC protection in the system chip comprises the steps of: The port connection and driver function selects the interface of the AHB host agent component corresponding to the data bit width according to the name of the master device and forces the connection with the master device bus port through the force function; Sending the read and write access requests in the test case to the output port of the master device currently being accessed through the interface of the AHB host agent component according to the timing requirements of the bus protocol and monitoring the bus response signal received by the master device during the transmission; Check whether the ECC modules of the master and slave devices in the current access can correctly correct 1-bit errors and detect 2-bit errors in the received data; After the current access is finished, the interface connection between the master device bus port and the AHB host agent component is released through the port connection and the driver function through the release function; The force function is used to establish a connection between the interface of the AHB host agent component to be accessed next time and the bus port of the master device, and switch to the functional verification of the ECC modules corresponding to the next group of master and slave devices until the functional verification of the ECC modules corresponding to all master and slave devices is completed.

4. The method for verifying end-to-end access ECC protection in a system chip according to claim 3, characterized in that: After the step of sending the read and write access request in the test case to the output port of the master device currently being accessed through the interface of the AHB host agent component according to the timing requirements of the bus protocol and monitoring the bus response signal received by the master device during the transmission, the step further includes: Check the injection error of the data initiator in the current access and whether the ECC module of the data receiver can correctly correct the 1-bit error and detect the 2-bit error of the transmitted data.

5. The method for verifying end-to-end access ECC protection in a system chip according to claim 3 or 4, characterized in that: The 32-bit AHB host agent component and the 64-bit AHB host agent component both include a driver, a monitor and an interface. The driver is used to send an end-to-end access request to the output port of the master device through the interface according to the timing requirements of the bus protocol under the drive of the port connection and driver function. The monitor is used to monitor the bus response signal received by the master device during transmission, and check whether the ECC modules of the master and slave devices in the current access can correctly correct 1-bit errors and detect 2-bit errors of the received data.

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