IO multiplexing circuit with anti-backflow function

Abstract

The invention discloses an IO multiplexing circuit with an anti-backflow function, when a port P is used as an output end, an enable signal EN is a high level, and the IO multiplexing circuit can realize a data transmission function; when a port P is used as an input end, an enable signal EN is in a low level, a pull-up branch and a pull-down branch in the anti-backflow circuit are controlled to be turned off, the port P of the IO multiplexing circuit is used as the input end, and if the port P inputs the low level, the internal power supply voltage of the IO multiplexing circuit is not lower than the voltage of the port P, and backflow current does not exist; and if the high level is input into the port P and the voltage of the port P is higher than the voltage of the internal power supply of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reversely biased, so that the current is prevented from flowing backwards into the internal power supply of the IO multiplexing circuit from the port P. The current backward flowing risk during IO port multiplexing is solved, the circuit has the advantages of being simple in structure and low in power consumption, and the chip design cost is effectively reduced.

Description

Technical Field

[0001] The present invention relates to an IO multiplexing circuit, and in particular to an IO multiplexing circuit with an anti-backflow function. Background Art

[0002] IO (Input / Output) port is an important part of the chip, and is the interactive window for data transmission between the chip core and the external circuit. Since the IO port has the characteristics of bidirectional transmission, in order to save chip area and cost, the IO port can be reused. For example, through the control signal, when the chip is in normal working mode, the IO port is used as the input end of the external signal, and in the test mode, the IO port can be used as the output end to detect the voltage and current signals of the key nodes inside the chip.

[0003] In actual applications, when the IO port works in input port mode, the internal power supply of the chip is in the power-off process, and the IO port is connected to an external input signal of high level, there is a risk of current backflow. Since the pull-up PMOS body diode in the IO circuit is turned on, there is a current path from the IO port through the PMOS body diode to the internal power supply of the chip, charging the internal power supply, causing the chip to be in an abnormal working state.

[0004] In the prior art, the anti-backflow function processing for IO multiplexing circuits is often implemented by adding large resistors, capacitors or diodes. The use of large resistors and capacitors will occupy a large chip area, while the use of diodes has high process requirements and increases the design cost of the chip. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides an IO multiplexing circuit with an anti-backflow function, which solves the risk of current backflow when IO ports are multiplexed, and has the advantages of simple structure and low power consumption, effectively reducing the chip design cost.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solutions: an IO multiplexing circuit with anti-backflow function, which is composed of a logic control circuit and an anti-backflow circuit;

[0007] When the logic control circuit uses port P as an output end, when the enable signal EN and the digital logic signal D are both at a high level, the pull-up branch in the anti-backflow circuit is controlled to be turned on and the pull-down branch is turned off, and the port P of the IO multiplexing circuit outputs a high level as an output end to realize the data transmission function; when the enable signal EN is at a high level and the digital logic signal D is at a low level, the pull-up branch in the anti-backflow circuit is controlled to be turned off and the pull-down branch is turned on, and the port P of the IO multiplexing circuit outputs a low level as an output end to realize the data transmission function;

[0008] When the logic control circuit uses port P as an input terminal, the enable signal EN is at a low level, and the pull-up branch and the pull-down branch in the anti-backflow circuit are controlled to be turned off. The port P of the IO multiplexing circuit is used as the input terminal. If the port P inputs a low level, the internal power supply voltage of the IO multiplexing circuit is not lower than the port P voltage, and there will be no backflow current; if the port P inputs a high level, and the port P voltage is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased to prevent the current from flowing back from the port P into the internal power supply of the IO multiplexing circuit.

[0009] Further, the logic control circuit includes: a first inverter, a first logic level conversion circuit, a second logic level conversion circuit, a second inverter, a third inverter, a fourth inverter, a NAND gate and a NOR gate, the input end of the first inverter serves as the input end of the enable signal EN, the output end of the first inverter is connected to the input end of the first logic level conversion circuit, the Q output end of the first logic level conversion circuit is respectively connected to the input end of the second inverter and the first input port of the NOR gate, the output end of the second inverter is connected to the first input end of the NAND gate, and the output end of the NAND gate is connected to the input end of the third inverter; the input end of the second logic level conversion circuit serves as the input end of the digital logic signal D, the Q output end of the second logic level conversion circuit is respectively connected to the second input end of the NAND gate and the second input end of the NOR gate, and the output end of the NOR gate is connected to the input end of the fourth inverter; The output end, the output end of the third inverter and the output end of the fourth inverter are all connected to the anti-backflow circuit.

[0010] Further, the first logic level conversion circuit and the second logic level conversion circuit both include: a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, an eighth NMOS tube M13, a ninth NMOS tube M14, a sixth PMOS tube M15 and a seventh PMOS tube M16, the output end of the fifth inverter is respectively connected to the input end of the sixth inverter and the gate of the ninth NMOS tube M14, the output end of the sixth inverter is connected to the gate of the eighth NMOS tube M13, the drain of the eighth NMOS tube M13 is respectively connected to the drain of the sixth PMOS tube M15 and the gate of the seventh PMOS tube M16, the gate of the sixth PMOS tube M15, the drain of the seventh PMOS tube M16 and the drain of the ninth NMOS tube M14 are all connected to the input end of the seventh inverter, and the output end of the seventh inverter is used as The output end of the seventh inverter is connected to the input end of the eighth inverter, and the output end of the eighth inverter serves as the Q output end; the source of the sixth PMOS tube M15 and the source of the seventh PMOS tube M16 are both connected to the power supply voltage, and the source of the eighth NMOS tube M13 and the source of the ninth NMOS tube M14 are both grounded.

[0011] Furthermore, in the first logic level conversion circuit, the input end of the fifth inverter is connected to the output end of the first inverter; in the second logic level conversion circuit, the input end of the fifth inverter serves as the input end of the digital logic signal D.

[0012] Furthermore, the anti-backflow circuit includes: a first NMOS tube M1, a first PMOS tube M2, a second NMOS tube M3, a third NMOS tube M4, a pull-up branch composed of a second PMOS tube M5 and a third PMOS tube M6, a fourth PMOS tube M7, a fourth NMOS tube M8, a fifth NMOS tube M9, a sixth NMOS tube M10 as a pull-down branch, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, the gate of the first NMOS tube M1 is connected to the logic control circuit, the source of the first NMOS tube M1 is grounded, and the The drain of the first NMOS tube M1 is connected to one end of the first resistor R1 and the gate of the third PMOS tube M6 respectively, the other end of the first resistor R1 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is used as the port P of the IO multiplexing circuit; the gate of the first PMOS tube M2 and the gate of the second NMOS tube M3 are both connected to the logic control circuit, the source of the first PMOS tube M2 is connected to the power supply voltage, and the drain of the first PMOS tube M2 is connected to one end of the second resistor R2, the gate of the third NMOS tube M4, and the gate of the second PMOS tube M5 respectively. The other end of the second resistor R2 is connected to the drain of the second NMOS tube M3, the source of the second NMOS tube M3 is grounded, the substrate and source of the second PMOS tube M5 are both connected to the power supply voltage, the drain of the second PMOS tube M5 is connected to the source of the third PMOS tube M6, the substrate of the third PMOS tube M6, the drain of the third PMOS tube M6, the source of the third NMOS tube M4, and the drain of the third NMOS tube M4 are all connected to one end of the fourth resistor R4; the gate of the fourth PMOS tube M7 and the gate of the fourth NMOS tube M8 are both connected to the logic In the control circuit, the source of the fourth PMOS tube M7 is connected to the power supply voltage, the drain of the fourth PMOS tube M7 is respectively connected to one end of the third resistor R3, the source of the fifth NMOS tube M9, the drain of the fifth NMOS tube M9, and the gate of the sixth NMOS tube M10, the gate of the fifth NMOS tube M9 and the drain of the sixth NMOS tube M10 are both connected to one end of the fourth resistor R4, the source of the sixth NMOS tube M10 is grounded, the other end of the third resistor R3 is connected to the drain of the fourth NMOS tube M8, and the source of the fourth NMOS tube M8 is grounded.

[0013] Furthermore, the gate of the first NMOS tube M1 is connected to the gate of the first logic level conversion circuit. Output connection.

[0014] Furthermore, the gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the output end of the third inverter.

[0015] Furthermore, the gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the output end of the fourth inverter.

[0016] Further, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are all composed of a fifth PMOS tube M11 and a seventh NMOS tube M12, the gate of the fifth PMOS tube M11 and the gate of the seventh NMOS tube M12 serve as input ends of the inverters, the drain of the fifth PMOS tube M11 and the drain of the seventh NMOS tube M12 serve as output ends of the inverters, the source of the fifth PMOS tube M11 is connected to the power supply voltage, and the source of the seventh NMOS tube M12 is grounded.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] (1) The IO multiplexing circuit with anti-backflow function of the present invention controls the IO multiplexing circuit to work in the input or output state through an enable signal, thereby realizing the bi-phase transmission of signals from the IO port, reducing the number of IOs and reducing the chip cost;

[0019] (2) The pull-up branch of the anti-backflow circuit in the IO multiplexing circuit with anti-backflow function of the present invention has two control paths: when the port P is used as an output terminal, the state of the pull-up branch is controlled by the first NMOS tube M1 in the anti-backflow circuit to realize the data transmission function; when the port P is used as an input terminal, the state of the pull-up branch is controlled by the voltage of the port P of the IO multiplexing circuit. When the voltage of the port P is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased to prevent the current from flowing back from the port P into the internal power supply of the IO multiplexing circuit, thereby realizing the anti-backflow function and having the advantages of simple circuit structure and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a logic control circuit of an IO multiplexing circuit with an anti-backflow function of the present invention;

[0021] Figure 2 It is a schematic diagram of an anti-backflow circuit of an IO multiplexing circuit with an anti-backflow function of the present invention;

[0022] Figure 3 is a schematic diagram of an inverter circuit involved in the present invention;

[0023] Figure 4 It is a schematic diagram of the logic level conversion circuit in the present invention. DETAILED DESCRIPTION

[0024] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0025] The present invention provides an IO multiplexing circuit with an anti-backflow function, which is composed of a logic control circuit and an anti-backflow circuit; when the logic control circuit uses a port P as an output end, when an enable signal EN and a digital logic signal D are both at a high level, the pull-up branch in the anti-backflow circuit is controlled to be turned on and the pull-down branch is turned off, and the port P of the IO multiplexing circuit outputs a high level as an output end to realize a data transmission function; when the enable signal EN is at a high level and the digital logic signal D is at a low level, the pull-up branch in the anti-backflow circuit is controlled to be turned off and the pull-down branch is turned on, and the port P of the IO multiplexing circuit outputs a low level as an output end to realize a data transmission function. Input function; when the logic control circuit uses port P as the input end, the enable signal EN is low level, and the pull-up branch and the pull-down branch in the anti-backflow circuit are controlled to be turned off. The port P of the IO multiplexing circuit is used as the input end. If the port P inputs a low level, the internal power supply voltage of the IO multiplexing circuit is not lower than the port P voltage, and the pull-up branch is turned off, and there will be no backflow current; if the port P inputs a high level, and the port P terminal voltage is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased, which can prevent the current from flowing back from port P into the internal power supply of the chip, thereby realizing the anti-backflow function when the external input signal is too high.

[0026] like Figure 1 The logic control circuit of the present invention comprises: a first inverter, a first logic level conversion circuit, a second logic level conversion circuit, a second inverter, a third inverter, a fourth inverter, a NAND gate and a NOR gate, the input end of the first inverter is used as the input end of the enable signal EN, the output end of the first inverter is connected to the input end of the first logic level conversion circuit, the Q output end of the first logic level conversion circuit is respectively connected to the input end of the second inverter and the first input port of the NOR gate, the output end of the second inverter is connected to the first input end of the NAND gate, and the output end of the NAND gate is connected to the input end of the third inverter; the input end of the second logic level conversion circuit is used as the input end of the digital logic signal D, the Q output end of the second logic level conversion circuit is respectively connected to the second input end of the NAND gate and the second input end of the NOR gate, and the output end of the NOR gate is connected to the input end of the fourth inverter; the The output end, the output end of the third inverter and the output end of the fourth inverter are all connected to the anti-backflow circuit. The logic control circuit of the present invention realizes the logic operation of the enable signal EN and the digital logic signal D through the inverter, the logic level conversion circuit, the NAND gate and the NOR gate, and converts it into an output signal as the control signal of the subsequent anti-backflow circuit.

[0027] like Figure 4In the present invention, the first logic level conversion circuit and the second logic level conversion circuit both include: a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, an eighth NMOS tube M13, a ninth NMOS tube M14, a sixth PMOS tube M15 and a seventh PMOS tube M16, the output end of the fifth inverter is respectively connected to the input end of the sixth inverter and the gate of the ninth NMOS tube M14, the output end of the sixth inverter is connected to the gate of the eighth NMOS tube M13, the drain of the eighth NMOS tube M13 is respectively connected to the drain of the sixth PMOS tube M15 and the gate of the seventh PMOS tube M16, the gate of the sixth PMOS tube M15, the drain of the seventh PMOS tube M16 and the drain of the ninth NMOS tube M14 are all connected to the input end of the seventh inverter, and the output end of the seventh inverter is used as The output end of the seventh inverter is connected to the input end of the eighth inverter, and the output end of the eighth inverter is used as the Q output end; the source of the sixth PMOS tube M15 and the source of the seventh PMOS tube M16 are both connected to the power supply voltage, and the source of the eighth NMOS tube M13 and the source of the ninth NMOS tube M14 are both grounded. The present invention completes the conversion from the digital domain power supply to the analog domain power supply through the first logic level conversion circuit and the second logic level conversion circuit.

[0028] In the first logic level conversion circuit, the input end of the fifth inverter is connected to the output end of the first inverter; in the second logic level conversion circuit, the input end of the fifth inverter serves as the input end of the digital logic signal D.

[0029] like Figure 2 The anti-backflow circuit of the present invention includes: a first NMOS tube M1, a first PMOS tube M2, a second NMOS tube M3, a third NMOS tube M4, a pull-up branch composed of a second PMOS tube M5 and a third PMOS tube M6, a fourth PMOS tube M7, a fourth NMOS tube M8, a fifth NMOS tube M9, a sixth NMOS tube M10 as a pull-down branch, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The gate of the first NMOS tube M1 is connected to the logic control circuit. Specifically, the gate of the first NMOS tube M1 is connected to the first logic level conversion circuit. The output end is connected and the control signal F1 is input; the source of the first NMOS tube M1 is grounded, the drain of the first NMOS tube M1 is respectively connected to one end of the first resistor R1 and the gate of the third PMOS tube M6, the other end of the first resistor R1 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is used as the port P of the IO multiplexing circuit; the gate of the first PMOS tube M2 and the gate of the second NMOS tube M3 are both connected to the access logic control circuit, specifically, the gate of the first PMOS tube M2 and the gate of the second NMOS tube M3 are both connected to the output end of the third inverter, and the control signal F2 is input; the source of the first PMOS tube M2 is connected to the power supply voltage, the drain of the first PMOS tube M2 is respectively connected to one end of the second resistor R2, the gate of the third NMOS tube M4, and the gate of the second PMOS tube M5, the other end of the second resistor R2 is connected to the drain of the second NMOS tube M3, the source of the second NMOS tube M3 is grounded, the substrate and source of the second PMOS tube M5 are both connected to the power supply voltage, and the drain of the second PMOS tube M5 The source of the third PMOS tube M6 is connected to the substrate of the third PMOS tube M6, the drain of the third PMOS tube M6, the source of the third NMOS tube M4, and the drain of the third NMOS tube M4 are all connected to one end of the fourth resistor R4; the gate of the fourth PMOS tube M7 and the gate of the fourth NMOS tube M8 are all connected to the logic control circuit. Specifically, the gate of the fourth PMOS tube M7 and the gate of the fourth NMOS tube M8 are all connected to the output end of the fourth inverter, and the control signal F3 is input; the fourth PMOS tube The source of M7 is connected to the power supply voltage, the drain of the fourth PMOS tube M7 is respectively connected to one end of the third resistor R3, the source of the fifth NMOS tube M9, the drain of the fifth NMOS tube M9, and the gate of the sixth NMOS tube M10, the gate of the fifth NMOS tube M9 and the drain of the sixth NMOS tube M10 are both connected to one end of the fourth resistor R4, the source of the sixth NMOS tube M10 is grounded, the other end of the third resistor R3 is connected to the drain of the fourth NMOS tube M8, and the source of the fourth NMOS tube M8 is grounded.

[0030] When the port P is used as an output terminal, that is, the enable signal EN=1, when the digital logic signal D=1, at this time, the logic control circuit outputs signals F1=1, F2=D=1, and F3=D=1. After the control signals F1, F2, and F3 are transmitted to the anti-backflow circuit, the control signal F1 is 1, the first NMOS tube M1 is turned on, so that the third PMOS tube M6 is turned on; the control signal F2 is 1, so that the second NMOS tube M3 is turned on, the first PMOS tube M2 is turned off, the gate of the second PMOS tube M5 is pulled to the ground potential, and the second PMOS tube M5 is turned on; the control signal F3 is 1, so that the fourth NMOS tube M8 is turned on, the fourth PMOS tube M7 is turned off, the gate of the sixth NMOS tube M10 is pulled to the ground potential, and the sixth NMOS tube M10 is turned off. Since the pull-up branch is turned on and the pull-down branch is turned off, the port P outputs a high level. When the enable signal EN=1 and the digital logic signal D=0, the logic control circuit outputs signals F1=1, F2=D=0, and F3=D=0. After the control signals F1, F2, and F3 are transmitted to the anti-backflow circuit, the control signal F1 is 1 to turn on the first NMOS tube M1, and then the third PMOS tube M6 is turned on; the control signal F2 is 0 to turn on the first PMOS tube M2, and the second NMOS tube M3 is turned off, and the gate of the second PMOS tube M5 is pulled to the power supply potential to turn off the second PMOS tube M5; the control signal F3 is 0 to turn on the fourth PMOS tube M7, and the fourth NMOS tube M8 is turned off, and the gate of the sixth NMOS tube M10 is pulled to the power supply potential to turn on the sixth NMOS tube M10. At this time, the pull-up branch is turned off, the pull-down branch is turned on, and the port P outputs a low level. In summary, when the IO multiplexing circuit is used as an output terminal, the output voltage of port P changes with the digital logic signal D. When D is high, port P outputs a high level; when D is low, port P outputs a low level, thus realizing the data transmission function. Among them, 1 represents a high level and 0 represents a low level.

[0031] When the port P is used as an input terminal and the enable signal EN=0, no matter the digital logic signal D is 1 or 0, the output of the logic control circuit is always F1=0, F2=0, F3=1. After the control signals F1, F2, and F3 are transmitted to the anti-backflow circuit, F1=0 turns off the first NMOS tube M1, and the state of the third PMOS tube M6 is controlled by the voltage of the port P; F2=0 turns on the first PMOS tube M2, turns off the second NMOS tube M3, and pulls the gate of the second PMOS tube M5 to a high level to turn off the second PMOS tube M5; F3=1 turns on the fourth NMOS tube M8, turns off the fourth PMOS tube M7, and pulls the gate of the sixth NMOS tube M10 to a low potential to turn on the sixth NMOS tube M11. The MOS tube M10 is turned off. At this time, both the pull-up branch and the pull-down branch are turned off. The circuit no longer has the signal transmission function, but needs to prevent the current from flowing back from the port P to the power supply voltage through the pull-up branch. The specific implementation logic is discussed in two cases: when the port P is at a low level, the internal power supply voltage of the chip is not lower than the port P voltage, and there is no possibility of current flowing back from the port P into the internal power supply of the IO multiplexing circuit; the gate and drain voltages of the third PMOS tube M6 are both low levels, the third PMOS tube M6 is turned on, and the source voltage of the third PMOS tube M6 drops to a low potential, but because the second PMOS tube M5 is in the off state, no current will flow from the internal power supply voltage of the IO multiplexing circuit to the port P. When the port P is at a high level, the gate voltage and drain voltage of the third PMOS tube M6 are both at a high level. Since the substrate of the third PMOS tube M6 is connected to the drain, the body diode of the third PMOS tube M6 is in a reverse bias state at this time. Even if the power supply inside the chip is in a power-off process or the chip voltage is lower than the IO voltage, there is no conduction branch from the IO to the power supply inside the chip, and there is no backflow current of the IO. At the same time, since the parasitic body diode of the third PMOS tube M6 is used to realize the anti-backflow function, compared with adding additional diodes and other devices, it does not occupy additional voltage margin, the circuit structure is simpler, the dependence on the process is reduced, and the chip area and cost are saved. Therefore, the present invention realizes an IO multiplexing circuit with anti-backflow protection.

[0032] like Figure 3 In the present invention, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are all composed of a fifth PMOS tube M11 and a seventh NMOS tube M12, the gate of the fifth PMOS tube M11 and the gate of the seventh NMOS tube M12 serve as input ends of the inverters, the drain of the fifth PMOS tube M11 and the drain of the seventh NMOS tube M12 serve as output ends of the inverters, the source of the fifth PMOS tube M11 is connected to the power supply voltage, and the source of the seventh NMOS tube M12 is grounded.

[0033] The IO multiplexing circuit with anti-backflow function solves the risk of current backflow when IO ports are multiplexed, and has the advantages of simple structure and low power consumption, thereby effectively reducing chip design costs.

[0034] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. An IO multiplexing circuit with anti-backflow function, characterized in that: It is composed of logic control circuit and anti-backflow circuit; When the logic control circuit uses port P as an output end, when the enable signal EN and the digital logic signal D are both at a high level, the pull-up branch in the anti-backflow circuit is controlled to be turned on and the pull-down branch is turned off, and the port P of the IO multiplexing circuit outputs a high level as an output end to realize the data transmission function; when the enable signal EN is at a high level and the digital logic signal D is at a low level, the pull-up branch in the anti-backflow circuit is controlled to be turned off and the pull-down branch is turned on, and the port P of the IO multiplexing circuit outputs a low level as an output end to realize the data transmission function; When the logic control circuit uses port P as an input terminal, the enable signal EN is at a low level, and the pull-up branch and the pull-down branch in the anti-backflow circuit are controlled to be turned off. The port P of the IO multiplexing circuit is used as the input terminal. If the port P inputs a low level, the internal power supply voltage of the IO multiplexing circuit is not lower than the port P voltage, and there will be no backflow current; if the port P inputs a high level, and the port P voltage is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased to prevent the current from flowing back from the port P into the internal power supply of the IO multiplexing circuit.

2. The IO multiplexing circuit with anti-backflow function according to claim 1, characterized in that: The logic control circuit includes: a first inverter, a first logic level conversion circuit, a second logic level conversion circuit, a second inverter, a third inverter, a fourth inverter, a NAND gate and a NOR gate, the input end of the first inverter serves as the input end of an enable signal EN, the output end of the first inverter is connected to the input end of the first logic level conversion circuit, the Q output end of the first logic level conversion circuit is respectively connected to the input end of the second inverter and the first input port of the NOR gate, the output end of the second inverter is connected to the first input end of the NAND gate, and the output end of the NAND gate is connected to the input end of the third inverter; the input end of the second logic level conversion circuit serves as the input end of a digital logic signal D, the Q output end of the second logic level conversion circuit is respectively connected to the second input end of the NAND gate and the second input end of the NOR gate, and the output end of the NOR gate is connected to the input end of the fourth inverter; The output end, the output end of the third inverter and the output end of the fourth inverter are all connected to the anti-backflow circuit.

3. The IO multiplexing circuit with anti-backflow function according to claim 2, characterized in that: The first logic level conversion circuit and the second logic level conversion circuit both include: a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, an eighth NMOS tube M13, a ninth NMOS tube M14, a sixth PMOS tube M15 and a seventh PMOS tube M16, the output end of the fifth inverter is respectively connected to the input end of the sixth inverter and the gate of the ninth NMOS tube M14, the output end of the sixth inverter is connected to the gate of the eighth NMOS tube M13, the drain of the eighth NMOS tube M13 is respectively connected to the drain of the sixth PMOS tube M15 and the gate of the seventh PMOS tube M16, the gate of the sixth PMOS tube M15, the drain of the seventh PMOS tube M16 and the drain of the ninth NMOS tube M14 are all connected to the input end of the seventh inverter, and the output end of the seventh inverter is used as The output end of the seventh inverter is connected to the input end of the eighth inverter, and the output end of the eighth inverter serves as the Q output end; the source of the sixth PMOS tube M15 and the source of the seventh PMOS tube M16 are both connected to the power supply voltage, and the source of the eighth NMOS tube M13 and the source of the ninth NMOS tube M14 are both grounded.

4. The IO multiplexing circuit with anti-backflow function according to claim 3, characterized in that: In the first logic level conversion circuit, the input terminal of the fifth inverter is connected to the output terminal of the first inverter; In the second logic level conversion circuit, the input terminal of the fifth inverter serves as the input terminal of the digital logic signal D.

5. The IO multiplexing circuit with anti-backflow function according to claim 4, characterized in that: The anti-backflow circuit includes: a first NMOS tube M1, a first PMOS tube M2, a second NMOS tube M3, a third NMOS tube M4, a pull-up branch composed of a second PMOS tube M5 and a third PMOS tube M6, a fourth PMOS tube M7, a fourth NMOS tube M8, a fifth NMOS tube M9, a sixth NMOS tube M10 as a pull-down branch, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, wherein the gate of the first NMOS tube M1 is connected to the logic control circuit, the source of the first NMOS tube M1 is grounded, and the first NMOS tube M1 is connected to the logic control circuit. The drain of the OS transistor M1 is respectively connected to one end of the first resistor R1 and the gate of the third PMOS transistor M6, the other end of the first resistor R1 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is used as the port P of the IO multiplexing circuit; the gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the logic control circuit, the source of the first PMOS transistor M2 is connected to the power supply voltage, the drain of the first PMOS transistor M2 is respectively connected to one end of the second resistor R2, the gate of the third NMOS transistor M4, and the gate of the second PMOS transistor M5, The other end of the second resistor R2 is connected to the drain of the second NMOS tube M3, the source of the second NMOS tube M3 is grounded, the substrate and source of the second PMOS tube M5 are connected to the power supply voltage, the drain of the second PMOS tube M5 is connected to the source of the third PMOS tube M6, the substrate of the third PMOS tube M6, the drain of the third PMOS tube M6, the source of the third NMOS tube M4, and the drain of the third NMOS tube M4 are all connected to one end of the fourth resistor R4; the gate of the fourth PMOS tube M7 and the gate of the fourth NMOS tube M8 are both connected to the logic control In the control circuit, the source of the fourth PMOS tube M7 is connected to the power supply voltage, the drain of the fourth PMOS tube M7 is respectively connected to one end of the third resistor R3, the source of the fifth NMOS tube M9, the drain of the fifth NMOS tube M9, and the gate of the sixth NMOS tube M10, the gate of the fifth NMOS tube M9 and the drain of the sixth NMOS tube M10 are both connected to one end of the fourth resistor R4, the source of the sixth NMOS tube M10 is grounded, the other end of the third resistor R3 is connected to the drain of the fourth NMOS tube M8, and the source of the fourth NMOS tube M8 is grounded.

6. The IO multiplexing circuit with anti-backflow function according to claim 5, characterized in that: The gate of the first NMOS tube M1 is connected to the gate of the first logic level conversion circuit. Output connection.

7. The IO multiplexing circuit with anti-backflow function according to claim 5, characterized in that: The gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the output end of the third inverter.

8. The IO multiplexing circuit with anti-backflow function according to claim 5, characterized in that: The gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the output end of the fourth inverter.

9. The IO multiplexing circuit with anti-backflow function according to claim 5, characterized in that: The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are all composed of a fifth PMOS tube M11 and a seventh NMOS tube M12, the gate of the fifth PMOS tube M11 and the gate of the seventh NMOS tube M12 serve as input ends of the inverters, the drain of the fifth PMOS tube M11 and the drain of the seventh NMOS tube M12 serve as output ends of the inverters, the source of the fifth PMOS tube M11 is connected to the power supply voltage, and the source of the seventh NMOS tube M12 is grounded.

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