Semiconductor structure, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of first grooves arranged side by side along a first direction in the substrate; forming a supporting structure in the first groove, wherein the supporting structure at least partially covers the side wall of the first groove; filling the first groove with an isolation material to form an isolation material layer; wherein the isolation material layer covers the supporting structure; performing planarization processing on the isolation material layer to form an isolation layer located in the first groove; wherein the hardness of the supporting structure is greater than that of the isolating layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof, and a memory system. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses. DRAM is composed of multiple repeated memory cells, each of which usually includes a capacitor and a transistor. An isolation structure is provided between the multiple transistors in the multiple memory cells, and the isolation structure is used to reduce the electrical interference between two adjacent transistors and ensure the structural stability of the device. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, comprising:

[0004] providing a substrate;

[0005] forming a plurality of first grooves arranged side by side along a first direction in the substrate;

[0006] forming a support structure in the first trench, wherein the support structure at least partially covers a sidewall of the first trench;

[0007] Filling the first trench with an isolation material to form an isolation material layer; wherein the isolation material layer covers the support structure; performing a planarization process on the isolation material layer to form an isolation layer located in the first trench; wherein the hardness of the support structure is greater than the hardness of the isolation layer.

[0008] In some embodiments, the substrate includes semiconductor strips located between adjacent first trenches, and the planarizing process of the isolation material layer includes:

[0009] The isolation material layer is planarized by using a chemical mechanical polishing process; wherein the support structure is used to reduce deformation of the semiconductor strip caused by abrasive particles embedded in the first groove in the chemical mechanical polishing process.

[0010] In some embodiments, forming a support structure in the first groove includes:

[0011] A support structure is formed covering the sidewalls and the bottom of the first trench.

[0012] In some embodiments, the hardness of the support structure is greater than or equal to 1.7 GPa.

[0013] In some embodiments, the material of the support structure includes at least one of silicon oxide, silicon oxycarbide, and silicon oxynitride.

[0014] In some embodiments, the material of the isolation layer includes a spin-on carbon material.

[0015] In some embodiments, the substrate includes a semiconductor strip located between adjacent first trenches, the first trenches and the semiconductor strips both extend along a second direction, and the second direction intersects the first direction; the support structure and the isolation layer constitute a first isolation structure;

[0016] The manufacturing method further comprises:

[0017] forming a second trench extending along the first direction, the second trench passing through the semiconductor strip and the first isolation structure, so that the remaining semiconductor strips located on both sides of the second trench respectively form semiconductor columns; the semiconductor column comprises a first source and drain region, a channel region and a second source and drain region sequentially arranged along a vertical direction; wherein the vertical direction is perpendicular to the first direction;

[0018] forming a gate dielectric layer on the sidewalls of the second trench;

[0019] forming a gate layer located on the sidewall of the gate dielectric layer; wherein the gate layer is located on at least one side of the channel region;

[0020] A second isolation structure covering a surface of the gate layer is formed in the second trench.

[0021] According to a second aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0022] A plurality of semiconductor columns, wherein the plurality of semiconductor columns are arranged in an array along a first direction and a second direction intersecting each other;

[0023] The first isolation structure is located between the semiconductor pillars adjacent to each other along the first direction, and includes a support structure and an isolation layer, wherein the support structure at least partially covers the sidewalls of the semiconductor pillars, and the hardness of the support structure is greater than the hardness of the isolation layer.

[0024] In some embodiments, the support structure includes two support sidewalls disposed opposite to each other along the first direction, the support sidewalls cover a sidewall of the semiconductor column, and the isolation layer is located between the two support sidewalls.

[0025] In some embodiments, the support structure further includes a connecting portion, which is close to an end of the semiconductor column and connects two supporting spacers.

[0026] In some embodiments, the supporting spacer has a first width along the first direction, and the first width ranges from 4 nm to 8 nm;

[0027] The isolation layer has a second width along the first direction, and the second width has a size ranging from 10 nm to 14 nm.

[0028] In some embodiments, the material of the support structure includes at least one of silicon oxide, silicon oxycarbide, and silicon oxynitride.

[0029] In some embodiments, the material of the isolation layer includes a spin-on carbon material.

[0030] In some embodiments, the semiconductor column includes a first source and drain region, a channel region, and a second source and drain region sequentially arranged along a vertical direction, and the semiconductor structure further includes:

[0031] a gate layer extending along the first direction, wherein the gate layer is coupled to the channel regions of a plurality of the semiconductor pillars arranged side by side along the first direction;

[0032] The gate dielectric layer is located between the gate layer and the semiconductor column.

[0033] According to a third aspect of the present disclosure, there is provided a memory system, comprising:

[0034] One or more semiconductor structures as described in any one of the above;

[0035] The controller is coupled to the semiconductor structure and is configured to control the semiconductor structure.

[0036] In the manufacturing method of the semiconductor structure provided in the embodiment of the present disclosure, a support structure with relatively high hardness is formed in the first groove, and the support structure at least partially covers the sidewall of the first groove, and can play a supporting role for the substrate where the first groove is located, so that in the subsequent planarization process, if the abrasive exerts an extrusion force on the substrate, causing the substrate to have a tendency to bend and deform, the support structure can support the substrate to resist such deformation, that is, the support structure improves the bending resistance of the substrate, making it less likely for the substrate to bend and deform, reducing the probability of the substrate bending, and thereby improving the quality and yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1a to Figure 1b A schematic diagram of the structure of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0038] Figure 2 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0039] Figures 3a to 3kA schematic diagram of the structure of another semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure.

[0040] Figure 4 A schematic diagram of the structure of another semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0041] Figure 5 A schematic diagram of the structure of another semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.

[0043] Figure 7 A schematic diagram of the structure of a memory system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The technical solution of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments.

[0045] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The terminology used herein is intended only to describe specific embodiments and is not intended to be limiting of the present disclosure. The terms "consisting of" and / or "comprising", when used in this specification, identify the presence of features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0048] Figure 1a and Figure 1b The schematic diagram of the structure of an isolation structure provided in the embodiment of the present disclosure during the manufacturing process. Figure 1a As shown, a plurality of grooves 20 arranged in parallel along a first direction are formed in the substrate 10, and the grooves 20 extend along a second direction. The substrate 10 also includes semiconductor strips 30 located between adjacent grooves, and the extension direction of the semiconductor strips 30 is consistent with the grooves 20, that is, extending along the second direction.

[0049] Continue to see Figure 1a , a spin-on carbon material (SOC) is filled in the groove 20 until the SOC fills the groove and covers the top surface of the substrate 10 , thereby forming a SOC material layer 40 .

[0050] Then, if Figure 1b As shown, the spin-on carbon material layer 40 is planarized until the top surface of the substrate is exposed, and the remaining spin-on carbon material layer located in the trench 20 forms an isolation layer 60 .

[0051] However, if Figure 1a and Figure 1b As shown, in the actual process of planarizing the spin-coated carbon material layer 40, due to the low hardness of the spin-coated carbon material layer 40 (that is, the material is relatively soft), the abrasive 50 used in the planarization process is easily pressed into the spin-coated carbon material layer 40, thereby being embedded in the groove. In some cases, for example, the diameter of the abrasive 50 is greater than the width of the groove 20 along the first direction, and the abrasive may squeeze the semiconductor strip 30 after being embedded in the groove. In addition, since the size of the semiconductor strip 30 in the vertical direction is relatively large, the swing force arm after being squeezed by the abrasive 50 is relatively long, and the semiconductor strip 30 is easily bent and deformed by the squeezing force, thereby causing the entire substrate to bend and deform. This not only affects the subsequent process, but also causes defects, resulting in a decrease in the yield and reliability of the device.

[0052] In some embodiments, a spin-on dielectric material (Spin On Deposition, SOD) can be used to replace SOC. The SOD isolation layer is obtained by flattening the excess SOD after filling. Since the hardness of SOD is relatively large, the probability of abrasive embedding into the groove during the flattening process can be reduced, thereby improving the problem of abrasive-induced substrate bending during the flattening process. However, the corresponding matching process of the filling and removal process of SOD is complicated, the process window is small, which will cause the process cycle to be delayed, the process difficulty to increase and the cost to increase.

[0053] In another embodiment, the present disclosure provides a method for manufacturing a semiconductor structure, which is used to improve the problem of abrasive-induced substrate deformation during a planarization process. Figure 2 A schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the method for manufacturing the semiconductor structure includes:

[0054] S100: providing a substrate;

[0055] S200: forming a plurality of first grooves arranged side by side along a first direction in a substrate;

[0056] S300: forming a support structure in the first trench, wherein the support structure at least partially covers a sidewall of the first trench;

[0057] S400: filling an isolation material into the first trench to form an isolation material layer; wherein the isolation material layer covers the support structure;

[0058] S500: performing a planarization process on the isolation material layer to form an isolation layer located in the first trench; wherein the hardness of the support structure is greater than the hardness of the isolation layer.

[0059] Figures 3a to 3k A schematic diagram of a semiconductor structure in a manufacturing process provided by an embodiment of the present disclosure is shown below. Figure 2 , Figures 3a to 3k The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is introduced in detail.

[0060] See also Figure 3a , perform step S100 to provide a substrate 100.

[0061] In some embodiments, the base 100 includes a substrate 110 and a first mask layer located on the substrate 110 . The first mask layer can be used as a mask in subsequent etching steps and as a stop layer in a planarization process to protect the surface of the substrate 110 .

[0062] For example, the material of the substrate 110 may be silicon, germanium, silicon germanium semiconductor or silicon carbide, etc., or may be silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI), or may be other materials, such as III-V group compounds such as gallium arsenide. For example, the material of the first mask layer includes but is not limited to silicon nitride.

[0063] Figure 3b for Figure 3a The corresponding schematic top view of the semiconductor structure is shown in Figure 3a and Figure 3b , performing step S200, forming a plurality of first grooves 210 arranged side by side along a first direction in the substrate 100; wherein the portion of the substrate 100 located between two adjacent first grooves 210 constitutes a strip structure 101, and the first direction is parallel to the top surface of the substrate 100. Here, the first direction is, for example, the X direction.

[0064] In some embodiments, the first trench 210 extends from the top surface of the substrate 100 into the substrate 110 . The step of forming the first trench 210 in the substrate 100 may specifically include:

[0065] The first mask layer is patterned to obtain a patterned first mask layer 130; wherein the patterned first mask layer 130 has a plurality of openings for defining the shape of the first groove 210; using the patterned first mask layer 130 as a mask, the substrate 110 is etched to form a plurality of first grooves 210 arranged side by side along a first direction (X direction); wherein the depth of the first grooves 210 along the vertical direction (Z direction) is less than the thickness of the base 100, and the first grooves 210 do not penetrate the substrate 110.

[0066] A plurality of first grooves 210 are formed at the etched position of the substrate 100, and the first grooves 210 extend along the second direction, and the second direction is parallel to the top surface of the substrate. Here, the second direction is, for example, the Y direction. Two adjacent first grooves 210 define a strip structure 101 in the substrate 100, so the strip structure 101 also extends along the second direction (Y direction).

[0067] For example, the process of etching the substrate 100 may include a dry etching process and a wet etching process. The dry etching process may be, for example, plasma etching.

[0068] In some embodiments, the portion of the substrate 110 between two adjacent first trenches 210 forms a semiconductor strip 300, that is, the two adjacent first trenches 210 define a semiconductor strip 300 in the substrate, and the sidewalls of the semiconductor strip 300 are exposed by the first trenches 210. The strip structure 101 includes the semiconductor strip 300, and the semiconductor strip 300 extends along the second direction (Y direction).

[0069] In some other embodiments, the method for manufacturing the semiconductor structure further includes: using a thermal oxidation process to generate an oxide layer 120 on the exposed surface of the substrate. Specifically, the top surface and sidewall of the semiconductor strip 300 and the substrate 110 at the bottom of the first trench 210 are oxidized to form an oxide layer 120. After the oxide layer 120 is formed, the size of the semiconductor strip 300 is reduced. The strip structure 101 includes the semiconductor strip 300 and the oxide layer 120. The oxide layer 120 can be, for example, a silicon oxide layer.

[0070] See also Figure 3c , step S300 is performed to form a support structure 410 in the first trench 210 , wherein the support structure 410 at least partially covers the sidewall of the first trench, that is, the support structure 410 at least partially covers the sidewall of the strip structure 101 .

[0071] By way of example, the support structure 410 is in contact with the sidewall of the semiconductor strip 300 , or the support structure 410 is in contact with the oxide layer 120 on the sidewall of the semiconductor strip 300 .

[0072] In this embodiment, the hardness of the support structure 410 is greater than the hardness of the isolation layer subsequently filled in the remaining space of the first groove 210. The support structure 410 has a relatively large hardness and is in contact with the sidewall of the strip structure 101, and can support the semiconductor strip therein, so that in the subsequent planarization process, if the abrasive exerts an extrusion force on the semiconductor strip, causing the semiconductor strip to have a bending tendency, the support structure can support the semiconductor strip to resist such deformation, that is, the support structure improves the bending resistance of the semiconductor strip, making it less likely for the semiconductor strip to bend and deform, and also reduces the probability of substrate bending, thereby improving the quality and yield of the semiconductor structure.

[0073] In some embodiments, the hardness of the support structure 410 is greater than or equal to 1.7 GPa. For example, the hardness of the support structure 410 is 1.7 GPa, 1.8 GPa, 1.95 GPa, 2.3 GPa, 2.5 GPa, etc., so as to support the semiconductor strip 300 and increase the bending resistance of the semiconductor strip.

[0074] In some embodiments, Figure 3d As shown, the support structure 410 with greater hardness covers the entire side wall of the strip structure 101. Compared with a single strip structure, the strip structure and the support structure located on its side wall have a better bending resistance, so that the whole is not easy to bend and deform when subjected to the extrusion force of the abrasive, thereby reducing the probability of bending of the semiconductor strip and improving the deformation resistance of the substrate. It can also be understood that the support structure with greater hardness is set on the side wall of the first groove, which increases the proportion of hard materials in the substrate, thereby increasing the strength of the substrate and reducing the probability of bending of the substrate.

[0075] In some embodiments, forming a support structure 410 in the first trench 210 includes:

[0076] A support structure 410 covering the sidewalls and the bottom of the first trench 210 is formed.

[0077] In this embodiment, the support structure at the bottom of the first groove is connected to the support structure at the side wall of the first groove, and the support structure at the bottom of the first groove and the support structure at the side wall of the first groove are integrally formed, and the internal stress between the two can improve the ability of the support structure at the side wall of the first groove to resist bending deformation, improve the overall bending resistance of the semiconductor strip and the support structure, thereby reducing the probability of bending deformation of the substrate. It can also be understood that the support structure covers the bottom and side wall of the first groove, which can increase the proportion of hard materials in the substrate, improve the strength of the substrate, and thus reduce the probability of bending of the substrate.

[0078] In some embodiments, the support structure 410 also covers the top surface of the substrate (ie, the top surface of the strip structure 101 ), thereby protecting the top surface of the semiconductor strip and reducing damage to the top surface of the semiconductor strip caused by subsequent processes.

[0079] It should be understood that in some embodiments, Figure 3c As shown, when the substrate 100 also includes an oxide layer 120 and a patterned first mask layer 130, the support structure 410 covers the top surface of the substrate 100, that is, the support structure 410 covers the top surface of the patterned first mask layer 130; the support structure 410 covers the sidewalls of the first trench, that is, the support structure 410 covers the sidewalls of the oxide layer 120 and the sidewalls of the patterned first mask layer 130.

[0080] In some embodiments, a deposition process may be used to form the support structure 410. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), etc. The above process may form a film layer with high density and good step coverage, so that a relatively dense support structure can be formed on the sidewall and bottom of the first trench 210, thereby obtaining a support structure 410 with greater hardness.

[0081] In this embodiment, an atomic layer deposition process is used to form a support structure 410 with relatively high hardness. The atomic layer deposition process includes performing multiple atomic layer deposition cycles, and the deposition rate is slow. The film layer formed by the deposition has the characteristics of high density and good step coverage, so that a dense and relatively hard support structure 410 can be formed on the sidewall and bottom of the first trench 210.

[0082] In some embodiments, the material of the support structure 410 includes at least one of silicon oxide, silicon oxycarbide, silicon oxynitride, silicon nitride, and silicon carbide. These materials generally have the characteristic of high hardness, which can make the support structure 410 have greater hardness to improve the bending resistance of the semiconductor strip 300.

[0083] In this embodiment, the support structure is a silicon oxide layer formed by a deposition process, which has higher hardness than the spin-on carbon material SOC.

[0084] In some embodiments, the support structure 410 may include a plurality of sub-support layers. The plurality of sub-support layers are sequentially stacked on the sidewalls of the strip structure 101 along the first direction (X direction). It should be understood that the plurality of sub-support layers may also be sequentially stacked on the top surface of the substrate 100 (i.e., the top surface of the strip structure 101) and the bottom of the first groove 210.

[0085] For example, the materials of the multiple sub-support layers may be the same or different.

[0086] In some embodiments, the material selection of the multiple sub-support layers can take into account both hardness and isolation effect. By selecting different sub-support layers with different materials, the support structure can have both good hardness and good isolation effect. For example, some of the multiple sub-support layers have high hardness, while other sub-support layers have a smaller dielectric constant, so as to ensure that the support structure has a good isolation effect while having the required thickness and hardness.

[0087] See also Figure 3d , perform step S400 to fill the first trench with an isolation material to form an isolation material layer 421 ; wherein the isolation material layer 421 covers the support structure 410 .

[0088] Specifically, the isolation material is filled in the first trench until the isolation material fills up the first trench and covers the top surface of the substrate 100 (ie, the top surface of the strip structure), thereby forming an isolation material layer 421 .

[0089] The process of filling the isolation material in the first trench may include a deposition process and a spin coating process. The deposition process may include but is not limited to a chemical vapor deposition process and a physical vapor deposition process (PVD).

[0090] See also Figure 3e , performing step S500 to planarize the isolation material layer 421 to form an isolation layer 420 located in the first trench; wherein the hardness of the support structure 410 is greater than the hardness of the isolation layer 420. The support structure 410 and the isolation layer 420 together constitute the first isolation structure 400.

[0091] In some embodiments, the step of planarizing the filled isolation material includes:

[0092] like Figure 3e As shown, the isolation material layer 421 is processed by a planarization process until the support structure 410 located on the surface of the substrate 100 is exposed. At this time, the top surface of the remaining isolation material layer 421 is flush with the top surface of the support structure 410. The remaining isolation material layer 421 forms an isolation layer 420.

[0093] In some embodiments, the isolation material layer 421 may be planarized using a chemical mechanical polish (CMP) process, wherein the support structure 410 is used to reduce deformation of the semiconductor strip 300 caused by abrasive particles embedded in the first groove 210 during the chemical mechanical polishing process.

[0094] By way of example, the material of the isolation layer 420 includes, but is not limited to, a spin-on material, and the spin-on material may be, for example, a spin-on carbon material.

[0095] In this embodiment, due to the setting of the support structure 410, the bending resistance of the strip structure 101 (including the semiconductor strip) is improved, thereby reducing the probability of the semiconductor strip bending. Under this premise, when the isolation layer 420 uses a spin-coated carbon material, the spin-coated carbon material has the characteristics of good filling properties and low preparation difficulty. Good filling properties can reduce the generation of irregular voids, so that the isolation layers between different semiconductor strips are consistent, thereby ensuring the consistency of the performance of the storage unit, and the use of spin-coated carbon materials can shorten the process and reduce the process cost.

[0096] That is, in this embodiment, the support structure 410 and the isolation layer 420 are combined, which can reduce the probability of bending of the semiconductor strip, ensure the quality of the isolation layer, reduce the difficulty of the manufacturing process of the isolation layer, and reduce the process cost. In addition, in this embodiment, the process steps introduced by adding the support structure are relatively few, the cost is low, and the impact on the existing process is very small. The process window for preparing the support structure and the isolation layer is relatively large, which can ensure the yield of the semiconductor structure.

[0097] In this embodiment, the material of the isolation layer is a spin-coated carbon material. The filling process of the spin-coated carbon material is simple, and the filling effect is high, and no heat treatment is required, thereby shortening the process cycle and reducing costs.

[0098] In some embodiments, the support structure 410 located on the sidewall of the strip structure 101 has a first width W1 along the first direction (X direction), the isolation layer 420 has a second width W2 along the first direction, and the strip structure 101 has a third width W3 along the first direction.

[0099] Among them, the total width of the strip structure 101 and the support structure 410 located on its two side walls is W0=2W1+W3, and the second width W2 of the isolation layer and the total width W0 of the strip structure and the support structure located on its two side walls satisfy: W2 / W0 is greater than or equal to 1 / 3 and less than or equal to 1 / 2.

[0100] Here, it should be noted that the ratio should be neither too large nor too small. When the ratio is too large, it is easy to cause the total width W0 of the hard material composed of the strip structure 101 and the support structure 410 located on its two side walls to be too small, which will have little improvement on the bending resistance of the strip structure, and the probability of bending of the strip structure is still high. When the ratio is too small, the hard material composed of the strip structure 101 and the support structure 410 located on its two side walls has better bending resistance, which can prevent the strip structure from bending, but at the same time it will increase the difficulty of preparing the isolation layer 420, resulting in a smaller filling process window, which is not conducive to the filling of the isolation material, affecting the yield and isolation effect.

[0101] For example, a first width W1 of the support structure 410 located on the sidewall of the strip structure along the first direction (X direction) ranges from 4 nm to 8 nm.

[0102] The second width W2 of the isolation layer 420 along the first direction ranges from 10 nm to 14 nm.

[0103] The third width W3 of the strip structure 101 along the first direction has a size range of less than or equal to 25 nm.

[0104] A fourth width of the first trench 210 along the first direction may have a size ranging from 18 nm to 30 nm.

[0105] In this embodiment, the first width W1 of the support structure on the sidewall of the strip structure 101 is 5 nm to 6 nm, the second width W2 of the isolation layer 420 is 12 nm, and the fourth width of the first trench is 25 nm to 30 nm.

[0106] It should be understood that since the support structures 410 located on each surface are formed in the same process, the thickness of the support structure 410 located at the bottom of the first groove 210 along the vertical direction (Z direction) may also be 4nm to 8nm. Here, the vertical direction is perpendicular to the first direction, and the vertical direction may be, for example, the Z direction. Of course, in other embodiments, the deposition process may also be controlled so that the thickness of the support structure 410 located at the bottom of the first groove 210 is different from the first width of the support structure located on the sidewall of the first groove. For example, the thickness of the support structure 410 located at the bottom of the first groove 210 may be greater than the first width of the support structure located on the sidewall of the first groove, so as to increase the internal stress between the two and further reduce the probability of bending of the strip structure.

[0107] In other embodiments, appropriate support structure dimensions and isolation layer dimensions may be selected according to specific material types and process conditions of the support structure 410 and the isolation layer 420 , as well as the widths of the strip structure and the first groove.

[0108] The manufacturing method of the semiconductor structure provided by the present disclosure can support the strip structure by forming a support structure in contact with the side wall of the strip structure 101, so that in the subsequent planarization process, if the abrasive generates an extrusion force on the strip structure, causing the strip structure to have a bending tendency, the support structure can support the strip structure to resist such deformation, that is, the support structure improves the bending resistance of the strip structure, making the strip structure less likely to bend and deform, and also reduces the probability of substrate bending and base deformation, thereby improving the quality and yield of the semiconductor structure.

[0109] Figure 3f The top view of the semiconductor structure after the first isolation structure 400 and the second trench 220 are formed is shown in FIG. Figure 3e For along Figure 3f The cross-sectional diagram of line BB in FIG. Figure 3g For along Figure 3f Schematic diagram of the cross section of line AA in FIG. Figure 3f and Figure 3g As shown, after forming the first isolation structure, the method for manufacturing the semiconductor structure may further include:

[0110] A second trench 220 extending along the first direction (X direction) is formed, and a plurality of second trenches are arranged in parallel along the second direction (Y direction). The second trench 220 passes through the semiconductor strip and the first isolation structure 400, so that the remaining semiconductor strips located on both sides of the second trench 220 form semiconductor columns 310 respectively; the semiconductor column 310 includes a first source and drain region 311, a channel region 312, and a second source and drain region 313 arranged in sequence along the vertical direction. Here, the vertical direction is perpendicular to the first direction, that is, perpendicular to the top surface of the substrate, and the vertical direction is, for example, the Z direction.

[0111] In some embodiments, Figure 3e As shown, before forming the second trench 220, a planarization process may be further used to sequentially remove the support structure 410, the oxide layer 120, and the patterned first mask layer 130 located on the top surface of the semiconductor strip 300 until the semiconductor strip 300 is exposed. At this time, the top surfaces of the remaining isolation layer 420 and the remaining support structure 410 are flush with the top surface of the semiconductor strip, and the support structure 410 covers the sidewalls of the semiconductor strip 300 and the bottom of the first trench.

[0112] In some embodiments, Figure 3f and Figure 3g As shown, when forming the second trench 220, a second mask layer (not shown in the figure) covering the substrate and the first isolation structure can be formed first, and the second mask layer can be patterned. The substrate and the first isolation structure are etched based on the patterned second mask layer to form the second trench 220.

[0113] Such as 3f and Figure 3gAs shown, a plurality of first isolation structures 400 extending along the second direction (Y direction) and a plurality of second trenches 220 extending along the first direction (X direction) define a semiconductor column array in the substrate, and the semiconductor column array includes a plurality of semiconductor columns 310 arranged in an array in the first direction and the second direction. Each semiconductor column 310 includes a first source and drain region 311, a channel region 312, and a second source and drain region 313 sequentially arranged along the vertical direction (Z direction), the first source and drain region 311 being closer to the bottom of the first trench 210, and the second source and drain region 313 being closer to the opening of the first trench. One of the first source and drain region 311 and the second source and drain region 313 is a source region, and the other is a drain region.

[0114] For example, the first source and drain regions 311 and the second source and drain regions 313 are formed by injecting N-type doping ions or P-type doping ions into the semiconductor column 310. The doping ions injected into the first source and drain regions 311 and the second source and drain regions 313 are of the same type, that is, both are N-type doped or P-type doped. In some embodiments, the channel region 312 can be an intrinsic semiconductor or a doped semiconductor. For example, P-type doping ions or N-type doping ions can be injected into the channel region 312 of the semiconductor column 310 to form the channel region 312. The doping ion type of the channel region 312 is different from that of the first source and drain region 311. If the first source and drain region 311 is P-type doped, the channel region 312 is N-type doped. Conversely, if the first source and drain region 311 is N-type doped, the channel region 312 is P-type doped.

[0115] In some embodiments, before etching the substrate 110, doping ions may be injected into the substrate 110 to form a first source-drain layer, a channel layer, and a second source-drain layer arranged in sequence along a vertical direction; thereafter, the substrate 110 is etched to form a plurality of semiconductor pillars 310, each semiconductor pillar 310 including a first source-drain region 311 corresponding to the first source-drain layer, a channel region 312 corresponding to the channel layer, and a second source-drain region 313 corresponding to the second source-drain layer.

[0116] In some other embodiments, after forming the semiconductor pillars 310 , doping ions may be implanted into all the semiconductor pillars 310 , so that each semiconductor pillar 310 includes a first source and drain region 311 , a channel region 312 , and a second source and drain region 313 .

[0117] like Figure 3g and Figure 3hAs shown, a gate dielectric layer 510 is formed on the sidewall of the second trench 220, and then a gate layer 520 is formed on the sidewall of the gate dielectric layer 510; wherein the gate layer 520 is located on at least one side of the channel region 312 and is arranged opposite to the channel region 312. The gate layer 520 extends along the first direction (X direction) and is coupled with the channel regions of the plurality of semiconductor pillars 310 arranged side by side along the first direction, so as to control the opening and closing of the transistor. In this embodiment, the gate layer 520 is located on both sides of the channel region 312 along the second direction (Y direction).

[0118] For example, the gate dielectric layer may include silicon oxide, silicon oxynitride or a high dielectric constant (High-K) material. High dielectric constant materials include but are not limited to hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide zirconium oxide silicon, etc. The process of forming the gate dielectric material layer includes but is not limited to chemical vapor deposition, atomic layer deposition, thermal oxidation, etc.

[0119] The material of the gate layer may include metal, metal nitride and silicon, etc. Metals include but are not limited to tungsten, gold, silver, copper, aluminum, titanium, tantalum, etc. Metal nitrides include but are not limited to titanium nitride, tungsten nitride, tantalum nitride, etc. Silicon includes but is not limited to polysilicon and doped polysilicon.

[0120] Continue to see Figure 3h , a second isolation structure 600 covering the surface of the gate layer is formed in the second trench 220 .

[0121] In some embodiments, the second isolation structure 600 covers the gate dielectric layer 510 and the gate layer 520 , and fills up the remaining space of the second trench.

[0122] The material of the second isolation structure 600 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or other low dielectric constant (Low-K) materials.

[0123] In some embodiments, Figure 3h As shown, the manufacturing method of the semiconductor structure further includes: forming a spacing structure 700, the spacing structure 700 is located between the second isolation structures 600 and extends along the first direction (X direction). The bottom of the spacing structure 700 is at least lower than the bottom of the channel region 312, so as to divide the second source and drain region 313 into two parts and the channel region 312 into two parts, so that the semiconductor column 310 forms two transistors 301 arranged side by side along the second direction (Y direction), and each transistor 301 is controlled by a word line (that is, the gate layer 520). That is, in this embodiment, the gate layer is located on one side of the channel region.

[0124] The material of the spacer structure 700 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0125] In this embodiment, the spacing structure 700 includes a first silicon oxide layer and a first silicon nitride layer stacked in sequence along the vertical direction (Z direction), the first silicon nitride layer is closer to the top surface of the semiconductor column 310, and the spacing structure also includes a second silicon oxide layer surrounding the first silicon oxide layer and the first silicon nitride layer.

[0126] In some embodiments, the spacer structure 700 is formed first, and then the gate dielectric layer 510 , the gate layer 520 and the second isolation structure 600 are formed.

[0127] In some embodiments, Figure 3h to Figure 3k As shown ( Figure 3k The oxide layer 120 and the gate dielectric layer 510 are not shown in the figure, the substrate 110 includes a first surface and a second surface arranged opposite to each other in a vertical direction (Z direction), and the above processes are all performed on the first surface of the substrate 110. The method for manufacturing the semiconductor structure also includes: thinning the second surface of the substrate until the first isolation structure 400 and the second isolation structure 600 are exposed, and at this time, the plurality of semiconductor pillars 310 are isolated from each other.

[0128] In some embodiments, during the thinning of the second surface of the substrate, the support structure 410 in the first groove is completely retained, and the following is obtained: Figure 3i The support structure includes two support sidewalls 411 arranged opposite to each other along the first direction (X direction), and a connecting portion 412 connecting the support sidewalls, and the support sidewalls cover the sidewalls of the semiconductor column 310. In other embodiments, the support structure at the bottom of the isolation layer can also be removed to obtain the following: Figure 4 The structure shown. Figure 4 The supporting structure shown only includes two supporting side walls 411 , and the connecting portion 412 is removed.

[0129] After that, continue to see Figure 3i to Figure 3k , a plurality of bit lines 530 are formed on the second surface of the thinned substrate 110, the plurality of bit lines 530 are arranged side by side along the first direction (X direction), each bit line 530 extends along the second direction (Y direction), and is electrically connected to the first source and drain regions 311 of the plurality of semiconductor pillars 310 arranged at intervals along the second direction. In some embodiments, the bit line 530 may be directly contacted and connected to the first source and drain regions 311. In another embodiment, a bit line contact plug 531 may be further provided between the bit line 530 and the first source and drain regions 311, and the bit line 530 and the first source and drain regions 311 are electrically connected through the bit line contact plug 531.

[0130] In some embodiments, the manufacturing method of the semiconductor device also includes: forming a capacitor array on the first surface of the substrate, the capacitor array includes a plurality of capacitors arranged in an array, each capacitor is connected to the second source and drain region 313 of a semiconductor column 310, and each capacitor and the corresponding transistor constitute a storage unit.

[0131] The present disclosure also provides a gate structure and a second isolation structure, which are different from Figure 3g to Figure 3h The gate structure (including a gate layer and a gate dielectric layer) and the second isolation structure are shown. Figure 5 A cross-sectional view of another semiconductor structure provided according to an embodiment of the present disclosure.

[0132] In some embodiments, Figure 5 As shown, the specific steps of forming the gate dielectric layer 510, the gate layer 520 and the second isolation structure 600 may include:

[0133] A lower isolation structure 610 is formed at the bottom portion of the second trench 220. The lower isolation structure 610 includes a first silicon oxide layer 601, a second silicon nitride layer 602 covering the first silicon oxide layer, and a third silicon oxide layer 603, the top surfaces of which are flush and lower than the top surface of the semiconductor pillar 310. The top surface of the lower isolation structure 610 determines the position of the bottom of the gate layer to be formed subsequently;

[0134] forming a gate dielectric material layer in the second trench, the gate dielectric material layer covering the top surface of the lower isolation structure 610 and the sidewalls of the second trench; and forming a gate material layer covering the gate dielectric material layer;

[0135] At least part of the gate material layer and the gate dielectric material layer at the bottom of the second trench is removed until the lower isolation structure 610 is exposed. At this time, the remaining gate material layer is divided into two independent parts, and the gate dielectric material layer is divided into two independent parts.

[0136] An intermediate isolation structure 620 is formed in the second trench, wherein the top surface of the intermediate isolation structure is lower than the top surface of the semiconductor pillar 310, and the top surface of the intermediate isolation structure determines the position of the top of the gate layer to be formed subsequently;

[0137] Afterwards, the gate dielectric material layer and the gate material layer are etched until the top surfaces of the two are flush with the top surface of the middle isolation structure 620, wherein the remaining two portions of the gate material layer form two gate layers 520 isolated from each other, and the remaining two portions of the gate dielectric material layer form two gate dielectric layers 510 isolated from each other;

[0138] Finally, an upper isolation structure 630 is deposited in the remaining space of the second trench, and the lower isolation structure 610 , the middle isolation structure 620 and the upper isolation structure 630 together constitute a second isolation structure 600 .

[0139] In some embodiments, the gate layer 520 may include a metal nitride layer and a metal layer stacked along the second direction (Y direction), and the metal nitride layer is used to block the metal from diffusing into the gate dielectric layer 510 .

[0140] The present disclosure also provides a semiconductor structure, such as Figure 3i to Figure 3k As shown, the semiconductor structure includes:

[0141] A plurality of semiconductor pillars 310, wherein the plurality of semiconductor pillars 310 are arranged in an array along an intersecting first direction (X direction) and a second direction (Y direction);

[0142] The first isolation structure 400 is located between semiconductor pillars 310 adjacent to each other along a first direction (X direction). The first isolation structure 400 includes a support structure 410 and an isolation layer 420 , wherein the support structure 410 at least partially covers the sidewalls of the semiconductor pillars 310 , and the hardness of the support structure 410 is greater than the hardness of the isolation layer 420 .

[0143] The “covering” in this embodiment includes both direct contact and indirect covering. For example, the support structure 410 may be in direct contact with the sidewall of the semiconductor pillar 310. Alternatively, when the sidewall of the semiconductor pillar 310 is provided with an oxide layer 120, the support structure is in contact with the oxide layer and thus indirectly covers the sidewall of the semiconductor pillar 310.

[0144] In this embodiment, the support structure 410 at least partially covers the side wall of the semiconductor column 310. Since the hardness of the support structure 410 is greater than the hardness of the isolation layer 420, it can support the semiconductor column 310, improve the bending resistance of the semiconductor column 310, reduce the probability of damage to the semiconductor column 310 caused by the stress generated by the abrasive embedded in the first isolation structure during the planarization process, and improve the stability of the semiconductor structure.

[0145] In some embodiments, Figure 3i As shown, the support structure 410 includes two support spacers 411 disposed opposite to each other along a first direction (X direction), the support spacers 411 cover the sidewalls of a semiconductor column 310 , and the isolation layer 420 is located between the two support spacers 411 .

[0146] For the semiconductor pillar 310 , one sidewall of the semiconductor pillar 310 along the first direction (X direction) is covered by a support spacer 411 in a support structure, and the other sidewall is covered by a support spacer 411 in another support structure.

[0147] Continue to see Figure 3i The support structure 410 further includes a connecting portion 412, which is close to one end of the semiconductor column 310 and connects the two support sidewalls 411. The connecting portion 412 connects the two support sidewalls 411, and the cross section of the support structure perpendicular to the second direction (e.g., XZ plane) is "U"-shaped. At this time, the isolation layer 420 can be regarded as filling the "U"-shaped groove formed by the support structure 410.

[0148] In other embodiments, Figure 4 As shown, the connecting portion 412 may also be removed, and the supporting structure 410 only includes two supporting side walls.

[0149] In some embodiments, the supporting sidewall 411 has a first width along the first direction (X direction), and the first width has a size range of 4nm to 8nm. Since the connecting portion 412 and the supporting sidewall 411 can be prepared in the same process step, the thickness of the connecting portion 412 along the vertical direction (Z direction) can also be 4nm to 8nm.

[0150] The material of the support structure 410 includes at least one of silicon oxide, silicon oxycarbide, and silicon oxynitride.

[0151] The isolation layer 420 has a second width along the first direction (X direction), and the second width has a size ranging from 10 nm to 14 nm. The material of the isolation layer 420 includes a spin-on carbon material.

[0152] In some embodiments, Figure 3j As shown, the semiconductor column 310 includes a first source and drain region 311 , a channel region 312 , and a second source and drain region 313 sequentially arranged along a vertical direction (eg, Z direction), and the vertical direction is perpendicular to the first direction and the second direction.

[0153] In some embodiments, Figure 3j and 3k As shown, the semiconductor structure further includes:

[0154] A gate layer 520 extending along a first direction (X direction), the gate layer 520 being coupled to the channel regions 312 of a plurality of semiconductor pillars 310 arranged side by side along the first direction;

[0155] The gate dielectric layer 510 is located between the gate layer 520 and the semiconductor pillar 310 .

[0156] By way of example, the gate layer 520 may be located on one side or both sides of the semiconductor pillar 310 along the second direction (Y direction).

[0157] In some embodiments, Figure 3k As shown, the semiconductor structure also includes a second isolation structure 600, which is located between the semiconductor pillars 310 arranged side by side along the second direction (Y direction), and covers the gate layer 520 and the gate dielectric layer 510, thereby isolating the multiple gate layers 520 arranged side by side along the second direction (Y direction).

[0158] The semiconductor structure has been described in detail in the semiconductor structure manufacturing method, so it will not be described again. The semiconductor structure provided in this embodiment can be a memory, and the memory includes the structure described above.

[0159] Figure 6 A schematic diagram of a memory provided by an embodiment of the present disclosure, such as Figure 6 As shown, in some embodiments, the memory includes: a first wafer 810 and a second wafer 820 connected to each other.

[0160] The first wafer 810 includes a memory cell array, which includes a semiconductor column array (i.e., a transistor array) and a capacitor array 811 located on one side of the semiconductor column array. The lower electrode plate of each capacitor in the capacitor array 811 is electrically connected to the second source and drain region of a semiconductor column 310, and the upper electrode plates of the capacitors are connected to each other, and can also be considered to be connected to a common wire 812. The first wafer 810 also includes: a bit line 530 located on a side of the semiconductor column array away from the capacitor array 811, a conductive plug 813 leading out of the common wire, an interconnection layer 814 connecting the bit line 530, the gate layer and the conductive plug 813, and a first bonding layer 815 connecting the interconnection layer 814 and including a first pad exposed on the surface of the first wafer.

[0161] The second wafer 820 includes a peripheral circuit, which includes a MOS transistor 821. The MOS transistor 821 may include a PMOS transistor and an NMOS transistor. A plurality of MOS transistors 821 may form devices in peripheral circuits such as buffers and sense amplifiers. The second wafer 820 also includes a peripheral contact plug 822 for leading out the source, drain and gate of the MOS transistor, a peripheral interconnection layer 823 connected to the peripheral contact plug, and a second bonding layer connected to the peripheral interconnection layer and including a second pad exposed on the surface of the second wafer.

[0162] For example, the first pad of the first wafer 810 and the second pad of the second wafer 820 are bonded to bond the first wafer and the second wafer to achieve circuit connection, and the peripheral circuit of the second wafer can control the memory cell array in the first wafer to access data.

[0163] like Figure 7 As shown, the embodiment of the present disclosure further provides a memory system 1000, the memory system comprising:

[0164] One or more semiconductor structures as described above;

[0165] The controller is coupled to the semiconductor structure and is configured to control the semiconductor structure.

[0166] For example, the semiconductor structure may be Figure 6 Memory shown.

[0167] In summary, in the semiconductor structure provided by the embodiment of the present disclosure, a supporting structure is arranged on the side wall of the semiconductor column, and the supporting structure has a relatively high hardness, thereby improving the bending resistance of the semiconductor column. In the subsequent planarization process, even if the abrasive particles exert a squeezing force on the semiconductor column, the supporting structure improves the bending resistance of the semiconductor column, making it less likely for the semiconductor column to bend and deform, thereby reducing the probability of the substrate bending, and further improving the quality and yield of the semiconductor structure.

[0168] It should be noted that the manufacturing method of the semiconductor structure provided in the embodiment of the present disclosure can be applied to DRAM structure or other semiconductor devices, and no further limitation is made here. The embodiment of the semiconductor structure manufacturing method provided in the present disclosure and the embodiment of the semiconductor structure belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict.

[0169] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the claims of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of first grooves arranged side by side along a first direction in the substrate; forming a support structure in the first trench, wherein the support structure at least partially covers a sidewall of the first trench; Filling the first trench with an isolation material to form an isolation material layer; wherein the isolation material layer covers the support structure; The isolation material layer is planarized to form an isolation layer located in the first trench; wherein the hardness of the support structure is greater than the hardness of the isolation layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The substrate includes semiconductor strips located between adjacent first trenches, and the planarization process of the isolation material layer includes: The isolation material layer is planarized by using a chemical mechanical polishing process; wherein the support structure is used to reduce deformation of the semiconductor strip caused by abrasive particles embedded in the first groove in the chemical mechanical polishing process.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of a support structure in the first groove comprises: A support structure is formed covering the sidewalls and the bottom of the first trench.

4. The method for manufacturing a semiconductor structure according to claim 1 or 3, characterized in that: The hardness of the support structure is greater than or equal to 1.7 GPa.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The material of the support structure includes at least one of silicon oxide, silicon oxycarbide, and silicon oxynitride.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The material of the isolation layer includes a spin-on carbon material.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The substrate comprises semiconductor strips located between adjacent first trenches, the first trenches and the semiconductor strips both extend along a second direction, and the second direction intersects the first direction; The support structure and the isolation layer constitute a first isolation structure; The manufacturing method further comprises: forming a second trench extending along the first direction, the second trench passing through the semiconductor strip and the first isolation structure, so that the remaining semiconductor strips located on both sides of the second trench respectively form semiconductor columns; the semiconductor column comprises a first source and drain region, a channel region and a second source and drain region sequentially arranged along a vertical direction; wherein the vertical direction is perpendicular to the first direction; forming a gate dielectric layer on the sidewalls of the second trench; forming a gate layer located on the sidewall of the gate dielectric layer; wherein the gate layer is located on at least one side of the channel region; A second isolation structure covering a surface of the gate layer is formed in the second trench.

8. A semiconductor structure, characterized in that: include: A plurality of semiconductor columns, wherein the plurality of semiconductor columns are arranged in an array along a first direction and a second direction intersecting each other; The first isolation structure is located between the semiconductor pillars adjacent to each other along the first direction, and includes a support structure and an isolation layer, wherein the support structure at least partially covers the sidewalls of the semiconductor pillars, and the hardness of the support structure is greater than the hardness of the isolation layer.

9. The semiconductor structure according to claim 8, characterized in that: The support structure includes two support sidewalls arranged opposite to each other along the first direction, the support sidewalls cover a sidewall of the semiconductor column, and the isolation layer is located between the two support sidewalls.

10. The semiconductor structure according to claim 9, characterized in that: The supporting structure further includes a connecting portion, which is close to one end of the semiconductor column and connects two supporting sidewalls.

11. The semiconductor structure according to claim 9, characterized in that: The supporting spacer has a first width along the first direction, and the first width ranges from 4 nm to 8 nm; The isolation layer has a second width along the first direction, and the second width has a size ranging from 10 nm to 14 nm.

12. The semiconductor structure according to claim 8, characterized in that The material of the support structure includes at least one of silicon oxide, silicon oxycarbide, and silicon oxynitride.

13. The semiconductor structure according to claim 8, characterized in that The material of the isolation layer includes a spin-on carbon material.

14. The semiconductor structure according to claim 8, characterized in that The semiconductor column includes a first source-drain region, a channel region, and a second source-drain region sequentially arranged along a vertical direction, and the semiconductor structure further includes: a gate layer extending along the first direction, the gate layer being coupled to the channel regions of a plurality of the semiconductor pillars arranged side by side along the first direction; The gate dielectric layer is located between the gate layer and the semiconductor column.

15. A memory system, characterized in that: The memory system comprises: One or more semiconductor structures according to any one of claims 8 to 14; The controller is coupled to the semiconductor structure and is configured to control the semiconductor structure.

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