Memory data storage structure, management method, memory manager and memory device
By designing memory data storage structures in ReRAM, including main memory area, redundant repair area and index area, ReRAM reliability issues are solved, achieving higher reliability and cyclic persistence.
Patent Information
- Application Number
- CN202311208400.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-18
- Publication Date
- 2025-03-18
AI Technical Summary
Reliability issues of ReRAM, especially after multiple executions, some resistor units fail, resulting in the reliability not meeting the mass production standards.
A memory data storage structure is designed, including a main memory area, a redundant repair area and an index area. The failed data unit in the main memory area is repaired in units of data units through the redundant repair area, and the address mapping relationship of the repaired failed data unit is established through the index area.
It improves the reliability and cycle durability of ReRAM, avoids read and write failures, has higher redundant space utilization, and can randomly read and write without affecting speed.
Smart Images
Figure CN119645715A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of memory technology, and in particular, relates to a memory data storage structure, a management method, a memory manager, and a memory device. Background Art
[0002] Resistive Random Access Memory (ReRAM) is a next-generation memory technology that is currently under development. ReRAM is implemented by applying a voltage to a stack of materials, which causes a change in resistance that can record data (0 and 1) in memory. Compared with flash memory, ReRAM has strong random storage performance, with the advantages of lower read latency and faster write speed. Although ReRAM has these excellent properties, it has encountered many difficulties in the mass production process, especially the reliability has not yet reached the mass production standard. After multiple executions, some resistor cells will fail.
[0003] Therefore, the reliability of ReRAM has become an important issue in this field. The commonly used method is to use error correction code (ECC) to solve the reliability problem of ReRAM to extend the service life of ReRAM. Taking 32-bit data as an example, for every 32-bit data, 24-bit ECC code is required to correct 4-bit failed cell data. This technology can solve some reliability problems, but its effect is not very obvious and has some limitations. Summary of the invention
[0004] The purpose of the present application is to provide a memory data storage structure, management method, memory manager, and memory device to solve the reliability problem of ReRAM.
[0005] In a first aspect, the present application provides a memory data storage structure, including a main storage area, a redundant repair area and an index area, wherein the main storage area, the redundant repair area and the index area respectively include a number of data units; the main storage area is used to store data; the redundant repair area is used to repair failed data units in the main storage area in units of data units; the index area is used to establish an address mapping relationship for repairing the failed data units.
[0006] In an implementation of the first aspect, the data unit includes a data subunit and an error correction subunit; the data subunit is used to store data, and the error correction subunit is used to store an error correction code; the error correction code stored in the data unit is used to correct errors in the data stored in the data unit.
[0007] In an implementation of the first aspect, the index area includes a failed data unit position index table and a redundant unit mapping position index table; the failed data unit position index table is used to mark the physical state of each data unit in the main storage area; the physical state includes a valid state and a failed state; the redundant unit mapping position index table is used to establish an address of the data unit marked as a failed state in the main storage area mapped to the redundant repair area; the data unit in the failed state is the failed data unit; the data unit in the valid state is the valid data unit.
[0008] In an implementation manner of the first aspect, the failed data unit position index table and / or the redundant unit mapping position index table are stored after data compression.
[0009] In an implementation of the first aspect, the compressed data of the failed data unit position index table is stored in a top-down development manner, and the compressed data of the redundant unit mapping position index table is stored in a bottom-up development manner; or the compressed data of the failed data unit position index table is stored in a bottom-up development manner, and the compressed data of the redundant unit mapping position index table is stored in a top-down development manner.
[0010] In an implementation manner of the first aspect, the error correction code includes an error correction code.
[0011] In the second aspect, the present application provides a memory data management method, including: storing data using a memory data storage structure according to any one of the above items; reading data in an index area; obtaining a read / write instruction, and obtaining a read / write real address based on the read / write instruction address and the data in the index area; reading / writing data in a data unit corresponding to the read / write real address; issuing a failure warning based on an error correction code stored in the data unit corresponding to the read / write real address; and repairing the data unit with a failure warning.
[0012] In an implementation of the second aspect, a failure warning is performed based on the error correction code stored in the data unit corresponding to the read / write real address, including: determining whether the number of error bits of the error correction code stored in the data unit exceeds a preset value; if so, performing a failure warning for the data unit; if not, not performing a failure warning.
[0013] In an implementation of the second aspect, the data unit of the failure warning is repaired, including: determining whether the redundant repair area has a redundant address; if so, writing the read / write data to the redundant address and updating the index data of the index area; if not, determining that the memory chip is a waste chip.
[0014] In an implementation of the second aspect, updating the index data in the index area includes: determining whether the data units in the index area are full; if so, determining that the memory chip is a waste chip; if not, writing the index data to be updated into the index area.
[0015] In a third aspect, the present application provides a memory manager, comprising: a memory configured to store a computer program; and a processor configured to execute the computer program so that the memory manager performs the method described in the first aspect of the present application.
[0016] In a fourth aspect, the present application provides a memory chip comprising the memory data storage structure described in any one of the above items.
[0017] In a fourth aspect, the present application provides a memory device, comprising the above-mentioned memory chip and the memory manager according to the third aspect of the present application, wherein the memory manager is used to manage memory data in the memory chip.
[0018] As described above, the memory data storage structure, management method, memory manager, and memory device described in this application have the following beneficial effects:
[0019] (1) The present application designs a redundant repair area to repair failed data units in the main storage area in units of data units, which does not affect the read and write speed of the memory, can be read and written randomly, and has a higher utilization rate of redundant space;
[0020] (2) This application combines error correction technology with redundant repair, which has better reliability. Even if the number of erase and write times of some data units is less than expected, it can effectively avoid read and write failures on the application side.
[0021] (3) In the present application, the same address can be repaired multiple times with redundancy, as long as there is redundant free space. Even if the same address fails multiple times, it can be repaired multiple times. In other words, repeated read and write operations on the same address will not affect the service life of the ReRAM, and the cycle durability is better.
[0022] (4) The present application provides early warning based on error correction codes, which can correctly warn and perform redundant repair before the data unit fails, thereby improving reliability.
[0023] (5) The present application compresses and stores the data in the index area, which can save ReRAM usage space as much as possible and make full use of redundant resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 Shown is a schematic structural diagram of a resistance random access memory according to an embodiment of the present application.
[0025] Figure 2Shown is a schematic diagram of the memory data storage structure described in an embodiment of the present application.
[0026] Figure 3 Shown is a schematic diagram of the data storage structure of the index area described in an embodiment of the present application.
[0027] Figure 4 Shown is a schematic diagram of the overall process of the memory data management method described in an embodiment of the present application.
[0028] Figure 5 Shown is a specific flow chart of the memory data management method described in an embodiment of the present application.
[0029] Figure 6 Shown is a schematic diagram of the structure of the memory manager described in an embodiment of the present application.
[0030] Figure 7 Shown is a structural schematic diagram of a memory device according to an embodiment of the present application.
[0031] Component number description
[0032] 11 Upper electrode
[0033] 12. Resistive layer
[0034] 13. Lower electrode
[0035] 21 Main storage area
[0036] 22 Redundant repair area
[0037] 23 Index area
[0038] 231 Failed data unit location index table compressed data storage area
[0039] 232 Redundant unit mapping location index table compressed data storage area
[0040] 6 Memory Manager
[0041] 61 Memory
[0042] 62 Processors
[0043] 7 Memory Devices
[0044] 71 Memory Chip
[0045] 72 Memory Manager
[0046] Steps S1 to S4
[0047] Steps S111 to S114
[0048] Steps S211 to S215
[0049] Steps S311 to S315
[0050] Steps S411 to S416 DETAILED DESCRIPTION
[0051] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0052] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0053] The following embodiments of the present application provide a memory data storage structure, management method, memory manager, and memory device, including but not limited to applications in resistive random access memory (ReRAM) chips. Resistive random access memory ReRAM is a non-volatile memory based on the reversible conversion of the resistance of non-conductive materials between a high resistance state and a low resistance state under the action of an external electric field. Figure 1 The figure shows a schematic diagram of a resistive random access memory. The ReRAM structure looks like a sandwich. The insulating dielectric layer (resistive layer 12) is sandwiched between two layers of metal to form a metal-insulator-metal (MIM) three-layer structure consisting of an upper electrode 11, a lower electrode 13 and a resistive layer 12. The resistive switching principle of ReRAM is based on the conductive path (generally referred to as conductive filament) in the device resistive layer 12, that is, by applying different pulse voltage excitations to the upper electrode 11 and the lower electrode 13, the resistive layer 12 undergoes resistive switching and produces physical changes. The conductive filaments will present two states of conduction or disconnection in the resistive layer: a non-volatile low resistance state (Low Resistance State, LRS) or a high resistance state (High Resistance State, HRS), thereby realizing the distinction and storage of the "0" and "1" states. However, after multiple executions of ReRAM, some resistor units (cells) will fail.
[0054] In some implementations, error correction code (ECC) is used to solve the reliability problem of ReRAM to extend the service life of ReRAM. Due to process inconsistency and various external factors, it will inevitably lead to poor performance or even unusable performance of individual addresses of some chips. Since these bad chips cannot be picked out during production, this will directly affect the reliability of ReRAM, resulting in the inability to smoothly mass-produce on the application side. When using ECC error correction code to solve the reliability problem of ReRAM, taking 32-bit data as an example, for every 32-bit data, 24-bit ECC code is required to correct 4-bit failed cell data. However, the ECC code also has the possibility of failure, which actually increases the failure probability by 75%. In real ReRAM applications, the probability of failure of the ECC code area will be greater than that of the data area, because even if only a few bits of the data are flipped, the ECC code will also flip, which results in insufficient overall erase and write times of ReRAM, and cannot meet the requirements of most application markets.
[0055] In the performance of the ReRAM cycle endurance experiment, ReRAM has the following characteristics: 1. The failure of a single cell at a certain address is highly random. After a failure occurs during a certain erase, it can be restored to normal after a later erase. 2. The difference in the cycle performance of different addresses is very obvious. Even with the addition of ECC error correction code, some addresses will still fail prematurely. After more erases, the random failure of a single cell will turn into a fixed failure. 3. In most cases, a failure will only cause one more bit than the previous failure, and it will not cause 2-4 more bits of error at a time.
[0056] Based on the above, we have the following ideas. First, since the failure of a single cell is highly random, the ECC error correction algorithm is a good choice to improve reliability. Secondly, since the cyclic persistence of different addresses is significantly different, after more erases and writes, the random failure of a single cell will turn into a fixed failure. A redundant repair mechanism can be introduced to improve the overall reliability and cyclic persistence of the chip. Furthermore, since in most cases a single cell fails, there will only be one more bit than the previous failure, and there will not be 2-4 more bits suddenly at once, so an ECC error warning mechanism for the data unit can be designed, which can correctly warn before the entire data unit fails and use redundant repair. In addition, since redundant repair requires indexing, a large amount of ReRAM space will be wasted. Based on the characteristics of the index, a compression algorithm similar to RLE can be used to compress the ReRAM usage space as much as possible.
[0057] Based on the above ideas, this application proposes a memory data storage structure, management method, memory manager, and memory device, introduces redundancy repair technology, and combines redundancy repair technology with error correction code error correction technology, greatly improving the reliability of ReRAM.
[0058] Some preferred embodiments are listed below to specifically illustrate the memory data storage structure, management method, memory manager, and memory device of the present application.
[0059] like Figure 2 As shown, the present application provides a memory data storage structure, which includes a main storage area 21, a redundant repair area 22 and an index area 23, wherein the main storage area 21, the redundant repair area 22 and the index area 23 respectively include a number of data units; the main storage area 21 is used to store data; the redundant repair area 22 is used to repair the failed data units in the main storage area 21 in units of data units; the index area 23 is used to establish an address mapping relationship for repairing the failed data units. In a preferred embodiment, the data units of the main storage area 21, the redundant repair area 22 and the index area 23 respectively include a data area and an error correction area, the data area stores data, and the error correction area stores an error correction code to correct the corresponding data in the data area. In this embodiment, ECC code is preferably used for error correction.
[0060] exist Figure 2 In the data structure of 1Mbits ReRAM, the allocation of each area in the storage structure is explained. In this example, ReRAM includes 1048 rows of storage space, each row contains 32 data units, and each data unit contains 32bit Data and 24bit ECC code. The main storage area 21 contains 32768 data units, which is the main capacity of ReRAM; the index area 23 is the data area of the index table, which contains 128 data units. Its main function is to provide an index for the data unit in the redundant repair area 22; the redundant repair area 22 contains 640 data units, which is mainly used to repair the failed data units in the main storage area 21, and can repair 2% of the data units in the main storage area 21.
[0061] In some preferred embodiments, the index area includes a failed data unit position index table and a redundant unit mapping position index table, the failed data unit position index table is used to mark the physical state of the data unit in the main storage area, the physical state includes a valid state and a failed state, and the redundant unit mapping position index table is used to establish the address of the failed data unit marked as the failed state in the main storage area mapped to the redundant repair area. The failed data unit position index table is stored after data compression, and the redundant unit mapping position index table is stored after data compression. The compressed data of the failed data unit position index table is stored in a top-down development manner, and the compressed data of the redundant unit mapping position index table is stored in a bottom-up development manner. In this embodiment, the compression algorithm is preferably the RLE compression algorithm. It should be noted that the compression algorithm includes but is not limited to the above-mentioned RLE compression algorithm.
[0062] like Figure 3 The data storage structure diagram of the index area according to the embodiment of the present application is shown. The index area 23 includes a failed data unit location index table compressed data storage area 231 and a redundant unit mapping location index table compressed data storage area 232. Figure 2 In the example ReRAM, since the main storage area 21 has 32768 data units, the failed data unit position index table is 32768 bits (bits), and the Nth bit represents whether the corresponding Nth data in 32768 is invalid, 0 represents not invalid (i.e. valid), and 1 represents invalid. In order to save storage space, the failed data unit position index table is compressed and stored. When storing, 32 bits are stored as a data unit, and the ECC code is used to correct the 32-bit data. This embodiment uses the RLE compression algorithm for compression. Since most of the failed data unit position index table are 0, the RLE compression rate is about 1 / 20. The compressed data of the failed data unit position index table is developed from top to bottom in the index area 23. The redundant unit mapping position index table compressed data storage area 232 stores the position of the failed data unit mapped to the redundant unit. Since the position address has 10 bits, there are a total of 640 redundant positions, that is, 6400 bits, and the RLE compression rate is about 1 / 5. The redundant unit mapping position index table compressed data develops from bottom to top in the index area 23. Since the data compression rate is not fixed, the top-down and bottom-up sampling methods can improve the ReRAM utilization rate. When the number of failed addresses increases, the data in the failed data unit position index table compressed data storage area 231 and the redundant unit mapping position index table compressed data storage area 232 are likely to be close or adjacent, so that the entire ReRAM will trigger a failed state.
[0063] It should be noted that the memory data storage result provided in the present application is not limited to the 1Mbits mentioned in the above embodiment, and can be allocated and designed according to the actual memory size required.
[0064] In the memory data storage structure proposed in the present application, a redundant repair area is designed to repair the failed data units in the main storage area in units of data units, which does not affect the read and write speed of the memory, can read and write randomly, and has a higher utilization rate of redundant space. At the same time, the present application combines error correction technology with redundant repair, which has better reliability. Even if some data units are erased and written less than expected, the read and write failures on the application side can be effectively avoided. In addition, the same address of the present application can be redundantly repaired multiple times, as long as there is redundant free time, even if the same address fails multiple times, it can be repaired multiple times, that is to say, repeated read and write operations on the same address will not affect the service life of ReRAM, and the cycle persistence is better. In addition, the present application compresses and stores the data in the index area, which can save ReRAM usage space as much as possible and make full use of redundant resources.
[0065] Figure 4 The overall flow chart of the memory data management method described in the embodiment of the present application is shown. In the memory data management method, the memory data storage structure described in some of the above embodiments is used to store data, and the method includes steps S1 to S3.
[0066] In step S1, the index area data is read.
[0067] In step S2, a read / write instruction is obtained, and a real read / write address is obtained according to the read / write instruction address and the index area data.
[0068] In step S3, data is read / written in the data unit corresponding to the read / write real address, and failure warning and repair are performed on the data unit corresponding to the read / write real address.
[0069] Among them, in step S3, the failure warning and repair of the data unit corresponding to the read / write real address includes: whether the number of error bits in the ECC code of the read or written data exceeds a preset value, and if so, the failure warning and repair are performed. The failure warning and repair include: judging whether there are any remaining redundant addresses in the redundant repair area, and if so, writing the read or written data to the redundant addresses in the redundant repair area, and updating the data in the index area.
[0070] exist Figure 4In the preferred embodiment shown, the method further includes step S4, in which it is determined whether the data units in the index area are full, and if so, the memory chip is determined to be a waste chip. That is to say, when the data units in the index area are full, it can be regarded as being unable to provide a mapping index of a redundant repair address for more failed data units, so that the memory chip can no longer repair more failed units, and the memory chip is regarded as a waste chip.
[0071] In order to more clearly understand the specific content of the memory data management method of this application, the following Figure 5 The memory data management method of this application is described in detail.
[0072] Figure 5 The specific flow chart of the memory data management method described in the embodiment of the present application is shown. The memory data management includes read data management and write data management, and both the read data management and write data management processes involve failure warning and repair management of failed data units, which are described in detail below.
[0073] In step S111, after the ReRAM is powered on, the index compression information of the index area is automatically loaded, including the failed data unit location index table compression data and the redundant unit mapping location index table compression data, and step S112 is executed.
[0074] In step S112, the compressed data is decompressed to obtain the failed data unit position index table and the redundant unit mapping position index table, thereby obtaining the failed data unit in the current main storage unit and the address of the redundant repair area for repairing the corresponding failed data unit, and then executing step S113. This step pre-parses the index information, which can improve the access speed of reading and writing ReRAM and avoid temporary loading of indexes.
[0075] In step S113, wait for the read and write operation instructions of the ReRAM, and execute step S114.
[0076] In step S114, determine whether it is a read data instruction, if so, go to step S211, otherwise go to step S311.
[0077] In step S211, the read address is parsed through the index table to obtain the read real address. It should be noted that if the data unit corresponding to the read address is in a valid state, the read real address corresponds to the read address, and if the data unit corresponding to the read address is in an invalid state, the corresponding redundant repair address is obtained according to the redundant unit mapping position index table as the read real address, and step S212 is executed.
[0078] In step S212, the data unit corresponding to the real address is read, and step S213 is executed.
[0079] In step S213, the number of bit errors in the ECC code is obtained, and step S214 is executed.
[0080] In step S214, it is determined whether the number of error bits in the ECC code exceeds a preset value. If yes, step S411 is executed, otherwise step S215 is executed. In a preferred embodiment, if the ECC error correction number is 4 bits, the warning value can be set to 2 or 3. This can provide an early warning before the ReRAM actually fails, and perform redundancy repair.
[0081] In step S215, the read data is returned, and the process returns to step S113.
[0082] In step S311, determine whether it is a write data instruction, if so, go to step S312, otherwise return to step S113.
[0083] In step S312, the write address is parsed through the index table to obtain the read real address, and then step S313 is executed. Similar to step S211, if the data unit corresponding to the write address is in a valid state, the write real address corresponds to the write address, and if the data unit corresponding to the write address is in an invalid state, the corresponding redundant repair address is obtained according to the redundant unit mapping position index table as the write real address.
[0084] In step S313, the data is written into the data unit corresponding to the real address, and step S314 is executed.
[0085] In step S314, after the input is written, the data in the data unit is transmitted back, the number of error bits in the ECC code is obtained, and step S315 is executed.
[0086] In step S315, it is determined whether the number of error bits in the ECC code exceeds a preset value. If yes, step S411 is executed, otherwise, step S113 is returned. Similar to step S214, in a preferred embodiment, if the ECC error correction number is 4 bits, the warning value can be set to 2 or 3. This can provide an early warning before the ReRAM actually fails, and perform redundancy repair.
[0087] In step S411, it is determined whether there are any available redundant repair addresses in the redundant repair area, if so, step S412 is executed, otherwise, step S416 is executed.
[0088] In step S412, redundant addresses are allocated, and the read or written data of the data unit that is about to fail is written into the corresponding redundant address, and step S413 is executed.
[0089] In step S413, the index table is updated, including the failed data unit position index table and the redundant unit mapping position index table, and step S414 is executed.
[0090] In step S414, it is determined whether the failed data unit location index table and the redundant unit mapping location index table are adjacent, if so, step S416 is executed, otherwise, step S415 is executed.
[0091] In step S415, the index table (including the failed data unit position index table and the redundant unit mapping position index table) is updated to the index area in the ReRAM, and the process returns to step S113.
[0092] In step S416, the memory chip is determined to be a defective chip.
[0093] In the present application, early warning is performed based on error correction codes, which can correctly warn and perform redundant repair before the data unit fails, thereby improving reliability.
[0094] Figure 6 The structure diagram of the memory manager described in the embodiment of the present application is shown. The memory manager 6 includes: a memory 61 configured to store a computer program; and a processor 62 configured to execute the computer program so that the memory manager 6 executes the memory data management method described in the present application.
[0095] In some embodiments, the memory 61 may include: ROM, RAM, disk, USB flash drive, memory card, optical disk, or other media that can store program codes.
[0096] In some embodiments, the processor 62 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc. In other embodiments, the processor may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0097] Figure 7 The structure diagram of the memory device described in the embodiment of the present application is shown. The memory device 7 includes a memory chip 71 and a memory manager 72, and the memory manager 72 is used to manage the memory data in the memory chip 71. The memory manager 72 can adopt the memory manager in the embodiment shown in Figure 6.
[0098] The present application embodiment also provides a computer-readable storage medium. A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by a program to instruct the processor, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state hard disk (SSD)), etc.
[0099] The present application embodiment may also provide a computer program product, the computer program product including one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer or data center.
[0100] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product may be a software installation package, and when the above method is required, the computer program product may be downloaded and executed on a computer.
[0101] In the several embodiments provided in the present application, it should be understood that the disclosed system, device or method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules or units, which can be electrical, mechanical or other forms.
[0102] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in the various embodiments of the present application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.
[0103] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0104] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.
[0105] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.
Claims
1. A memory data storage structure, characterized in that: It includes a main storage area, a redundant repair area and an index area, wherein the main storage area, the redundant repair area and the index area respectively include a number of data units; The main storage area is used to store data; The redundant repair area is used to repair the failed data units in the main storage area in units of data units; The index area is used to establish an address mapping relationship for repairing the failed data unit.
2. The memory data storage structure according to claim 1, characterized in that: The data unit includes a data subunit and an error correction subunit; the data subunit is used to store data, and the error correction subunit is used to store an error correction code; the error correction code stored in the data unit is used to correct errors in the data stored in the data unit.
3. The memory data storage structure according to claim 1, characterized in that: The index area includes a failed data unit position index table and a redundant unit mapping position index table; the failed data unit position index table is used to mark the physical state of each data unit in the main storage area; the physical state includes a valid state and a failed state; the redundant unit mapping position index table is used to establish the address of the data unit marked as a failed state in the main storage area mapped to the redundant repair area; the data unit in the failed state is the failed data unit; the data unit in the valid state is the valid data unit.
4. The memory data storage structure according to claim 3, characterized in that: The failed data unit position index table and / or the redundant unit mapping position index table are stored after data compression.
5. The memory data storage structure according to claim 4, characterized in that: The compressed data of the failed data unit position index table is stored in a top-down development manner, and the compressed data of the redundant unit mapping position index table is stored in a bottom-up development manner; or The compressed data of the failed data unit position index table is stored in a bottom-up development manner, and the compressed data of the redundant unit mapping position index table is stored in a top-down development manner.
6. The memory data storage structure according to claim 2, characterized in that: The error correction code includes an error correction code.
7. A memory data management method, characterized in that: include: Using the memory data storage structure according to any one of claims 1 to 6 to store data; Read the data in the index area; Obtaining a read / write instruction, and obtaining a read / write real address according to the read / write instruction address and the data in the index area; Read / write data in the data unit corresponding to the read / write real address; Providing a failure warning according to the error correction code stored in the data unit corresponding to the read / write real address; Repair the data unit of the failed warning.
8. The memory data management method according to claim 7, characterized in that: Performing a failure warning according to the error correction code stored in the data unit corresponding to the read / write real address includes: Determining whether the number of bit errors of the error correction code stored in the data unit exceeds a preset value; If yes, a failure warning is issued for the data unit; If not, no failure warning will be issued.
9. The memory data management method according to claim 7, characterized in that: Repair the data unit of the failed warning, including: Determine whether the redundant repair area has a redundant address; If yes, writing the read / write data into the redundant address and updating the index data of the index area; If not, the memory chip is determined to be a waste chip.
10. The memory data management method according to claim 9, characterized in that: Updating the index data of the index area includes: Determining whether the data units in the index area are full; If yes, the memory chip is determined to be a waste chip; If not, the index data that needs to be updated is written into the index area.
11. A memory manager, characterized in that: include: a memory configured to store a computer program; as well as A processor configured to execute the computer program so as to cause the memory manager to perform the method according to any one of claims 7 to 10.
12. A memory chip, characterized in that: A memory data storage structure comprising any one of claims 1 to 6.
13. A memory device, characterized in that: It comprises the memory chip as claimed in claim 12 and the memory manager as claimed in claim 11, wherein the memory manager is used to manage the memory data in the memory chip.