Silicon carbide MOSFET layout structure and manufacturing method

Abstract

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) layout structure and a manufacturing method, the silicon carbide MOSFET layout structure is formed by a periodic array of silicon carbide MOSFET cellular structures, each cellular structure comprises four square silicon carbide MOSFET cells, the four square silicon carbide MOSFET cells are arranged in order to form a square, and a channel is arranged between every two square silicon carbide MOSFET cells; the center of the square is provided with a cross-shaped JFET region; and the cross JFET region is provided with a P-type bridge region which is connected with the corners of any two square silicon carbide MOSFET cells in the diagonal direction. The invention further provides a manufacturing method based on the layout structure. According to the square silicon carbide MOSFET cellular structure, the channel density is improved, the on resistance of a silicon carbide MOSFET device is reduced, the P-type bridge region shields a high electric field in the cross-shaped JFET region, and the device is prevented from being broken down in advance.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a silicon carbide MOSFET layout structure and a manufacturing method thereof. Background Art

[0002] Power Metal Oxide Field Effect Transistors Metal oxide field effect transistors (MOSFETs) can carry large currents in the on state and withstand large breakdown voltages in the off state. The current between the source and drain regions in the semiconductor substrate is controlled by a voltage applied to the gate, which is isolated from the semiconductor surface by an insulator (usually silicon dioxide). For example, in an n-type enhancement MOSFET, a positive bias on the gate causes a surface inversion layer or channel to form in the p-type region under the gate oxide, forming a conductive path between the source and drain. Current is generated between the positive drain and source. Over the years, lateral and vertical power MOSFET structures in silicon have been explored, with the former having the drain, gate, and source on the same surface of the silicon wafer and the latter having the source and drain on opposite surfaces of the silicon wafer. Several different types of vertical power MOSFETs have been proposed, including DMOSFET and UMOSFET.

[0003] The structures of DMOSFET and UMOSFET are still valid for SiC MOSFET. The D in DMOSFET refers to double-implanted MOSFET in SiC MOSFET. The p-base region and n+ source region are produced by ion implantation rather than thermal diffusion. Because the diffusion coefficient of impurities in SiC is very low, it is not practical to apply diffusion process in SiC. SiC is the third generation of wide bandgap semiconductor material. Compared with Si-based MOSFET, SiC-based MOSFET has higher breakdown voltage, lower on-resistance and lower conduction loss. In the field of power devices, the market share of SiC power devices is increasing year by year.

[0004] Despite this, the potential advantages of silicon carbide as a power MOSFET have not yet been fully realized, and there are still problems such as excessive on-resistance and low reliability. The traditional linear layout structure has low channel density and high on-resistance, while the square, hexagonal, and octagonal cell layout structures have high channel density and low on-resistance. However, the square, hexagonal, and octagonal cells have a wider JFET area at the corners of the cells, resulting in the electric field in the local area of ​​the gate oxide layer exceeding the critical breakdown field strength of the gate oxide layer when the MOSFET device is in the blocking state, causing the device to break down prematurely, and avalanche breakdown will also occur prematurely at the P well of the MOSFET, resulting in reduced device reliability. Therefore, it is necessary to propose a silicon carbide MOSFET layout structure with low on-resistance and high breakdown voltage and its manufacturing method to optimize the performance of silicon carbide MOSFET. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a silicon carbide MOSFET layout structure and a manufacturing method, which are used to solve the problem in the prior art that the local electric field faced by the device is too large while maintaining a low on-resistance, resulting in reduced device reliability.

[0006] To solve the above technical problems, the first implementation scheme provided by the present invention is to provide a silicon carbide MOSFET cell structure, including: four square silicon carbide MOSFET cells, the four square silicon carbide MOSFET cells are neatly arranged in a square, and there are channels with equal distances between every two square silicon carbide MOSFET cells; a cross-shaped JFET area is provided at the center of the square; a P-type bridge area is provided on the cross-shaped JFET area, and the P-type bridge area connects the corners of any two square silicon carbide MOSFET cells located in the diagonal direction.

[0007] Preferably, the square silicon carbide MOSFET cell includes a substrate, an epitaxial layer and a CSL layer from bottom to top, a first hard mask layer is provided on the upper layer of the CSL layer, a P-well region injection window for P-well region ion implantation is etched on the first hard mask layer, the P-well region ions are implanted in the P-well region injection window to obtain a P-well region, a P+ region is provided in the middle of the P-well region, and N+ regions are also provided in the P-well regions on both sides of the P+ region, an ohmic contact metal layer is provided above the P+ region and the N+ region, a gate oxide layer, a gate polysilicon and a dielectric layer are provided above the CSL layer, the P-well region and the N+ region in sequence from bottom to top, a source metal layer is provided between the dielectric layer and the ohmic contact metal layer, and the P-type bridge region is connected to the gate oxide layer.

[0008] The second implementation scheme provided by the present invention is to provide a silicon carbide MOSFET layout structure composed of a silicon carbide MOSFET cell structure, wherein the silicon carbide MOSFET layout structure is formed by a periodic array of multiple silicon carbide MOSFET cell structures along the X direction and the Y direction.

[0009] Preferably, the plurality of silicon carbide MOSFET cell structures are arranged in a periodic matrix.

[0010] The third implementation scheme provided by the present invention is to provide a method for manufacturing a silicon carbide MOSFET layout structure, comprising the following steps: An epitaxial layer and a CSL layer are grown from bottom to top on a substrate; wherein the epitaxial layer is an n-type epitaxial layer, the CSL layer is an n-type CSL layer, and the substrate is a 4H-SiC heavily doped low-resistivity n-type silicon carbide substrate, or after a uniformly doped epitaxial layer is grown on the substrate, ion implantation is performed to generate the CSL layer.

[0011] A first hard mask layer is formed on the surface of the CSL layer, and the hard mask layer is etched using a mask plate to expose a P-well region injection window for ion injection into the P-well region; a p-type injection is performed to form a P-well region; The P-well region implantation window only needs to be etched to the ion implantation barrier layer of the first hard mask layer.

[0012] In order to avoid the threshold voltage being too high, the P-well region adopts reverse doping distribution, with low doping concentration on the surface and high doping concentration deep below. Since silicon carbide is a wide bandgap semiconductor material, it has a larger PN junction built-in electric field. Silicon carbide can be used to make normally-off accumulation channel MOSFETs.

[0013] Next, a uniform dielectric silicon nitride layer is deposited and carpet-etched to the same thickness to form a uniform dielectric silicon nitride spacer on the sidewall of the first hard mask layer; the dielectric silicon nitride spacer is used to realize the self-aligned channel of MOSFET; and N-type implantation is performed to form the N+ region.

[0014] The dielectric silicon nitride spacer layer and the first hard mask layer are removed, and a second hard mask layer is formed, and a mask is used to etch a window for P+ region injection and a window for P-type bridge region injection; p-type ion implantation is performed to form a P+ region and a P-type bridge region respectively, and the second hard mask layer is removed after the implantation is completed; The first hard mask layer and the second hard mask layer are composed from bottom to top including the following options: An ion implantation barrier layer (e.g., a silicon dioxide layer), an oxide layer (e.g., a silicon dioxide layer), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, a metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, an oxide layer (e.g., a silicon dioxide layer), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, an oxide layer (e.g., a silicon dioxide layer), a metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum).

[0015] The ions used to make the P+ region and the P-type bridge region are all aluminum ions.

[0016] Next, a cap layer composed of carbon is deposited, and a high-temperature thermal annealing is performed in an inert gas atmosphere to activate the implanted ions; after the annealing is completed, the cap layer is removed; Next, the subsequent production is carried out through the standard MOSFET production process; first, the surface of the wafer obtained above is cleaned; then, silicon carbide is thermally oxidized and annealed to form a gate oxide layer; a layer of gate polysilicon is deposited on the gate oxide layer, and the gate area is etched out using a mask; then a layer of dielectric layer (PMD) is deposited on the gate area of ​​the gate polysilicon, and a window in the source area is etched out using a mask, and the source metal forming the source metal layer is injected into the window in the source area; at the same time, an ohmic contact metal layer is sputtered between two adjacent dielectric layers (PMD) and high-temperature thermal annealing is performed to form an ohmic contact between the ohmic contact metal layer, the N+ area and the P+ area; the source metal is evaporated and the source area is etched out using a mask; then the back side is scribing, cleaning and substrate thinning processes are performed, and ohmic contact metal and drain metal (the drain metal is the drain electrode) are formed on the back side.

[0017] Preferably, the resistivity of the substrate is between 0.015Ω·cm and 0.025Ω·cm. The use of a low resistivity substrate can reduce the on-resistance of the device. The epitaxial layer is lightly doped, and the doping concentration of the epitaxial layer is 1×10 15 cm -3 ~3×10 16 cm -3 ; The doping concentration of the CSL layer is 1×10 16 cm -3 ~1×10 17 cm -3 .

[0018] Preferably, the P-well region adopts reverse doping distribution, with low surface doping concentration and high doping concentration deep below. The surface doping concentration is n-type doping 7×10 16 cm -3 To p-type doping 5×10 16 cm -3 , the peak doping concentration is greater than 1×10 18 cm -3 The P-type bridge region and the P+ region adopt the same doping distribution, the depth is the same as the P-well region, and the peak doping concentration is greater than 1×10 19 cm -3 .

[0019] The reverse doping distribution of the P-well can reduce the channel resistance of the device while ensuring the breakdown voltage, thereby reducing the overall on-resistance of the device. The P-type bridge area uses the same doping distribution as the P+ area and can be made at the same time as the P+ area, reducing the process steps. The same doping distribution is used for the P-type bridge and the P+ area to ensure the breakdown voltage of the device.

[0020] Preferably, the peak concentration of the N+ region should be 1×10 20 cm-3 The N+ doping concentration should be as high as possible to reduce the on-resistance of the device.

[0021] Preferably, the temperature of the high temperature thermal annealing is between 1500° C. and 1900° C., and the high temperature thermal annealing time is between 8 minutes and 15 minutes.

[0022] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention aims at the problem of premature breakdown of a silicon carbide power MOSFET cell structure in a blocking state. The square silicon carbide MOSFET cell of the present invention improves the channel density and reduces the on-resistance of the silicon carbide MOSFET device. A method of connecting the square cells using a P-type bridge is proposed. In this method, the P-type bridge region shields the gate oxide layer in the JFET region and the high electric field at the corners of the square cell, thereby avoiding premature breakdown of the device and improving the reliability of the device.

[0023] 2. In the present invention, the P-type bridge and the P+ region of the square cell are manufactured simultaneously, and no additional process steps are required. The present invention reduces the electric field strength of the gate oxide layer and the cell corners of the silicon carbide power MOSFET without adding process steps, thereby avoiding premature breakdown of the silicon carbide power MOSFET. While reducing the on-resistance of the silicon carbide power MOSFET, the reliability of the silicon carbide power MOSFET is ensured.

[0024] 3. The silicon carbide power MOSFET has square cells and a P-type bridge. A spacer thin dielectric layer is used to achieve channel self-alignment in the n+ source region, ensuring the reliability of the device and achieving a shorter channel less than 0.5um in length, reducing the resistance in the channel region, and thus reducing the overall specific on-resistance of the device. The P-type bridge connects the square cells at the corners, shortening the length of the JFET region. Under reverse withstand voltage, the P-type bridge forms a reverse-biased PN junction with the JFET region to shield the high gate oxide electric field at the corners of the square cells and the electric field at the P well. Under the premise of ensuring low on-resistance, the electric field strength on the gate oxide layer of the power MOSFET device is greatly reduced and the breakdown voltage of the MOSFET is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of a semiconductor device cell layout formed by a method according to an embodiment of the present invention; Figure 2 The chip structure formed according to the method of the embodiment is along Figure 1 Sectional view of AA'; Figure 3 The chip structure formed according to the method of the embodiment is along Figure 1 Sectional view of the middle BB'; Figure 4 is a schematic cross-sectional view of the substrate, epitaxial layer and CSL layer; Figure 5 is a schematic cross-sectional view of a semiconductor device after a P-well region is formed according to a method of an embodiment; Figure 6 is a schematic cross-sectional view of a semiconductor device after an N+ region is formed according to a method of an embodiment; Figure 7 The semiconductor device after forming the P+ region and the P-type bridge region according to the method of the embodiment Figure 1 Schematic diagram of the cross section of AA'; Figure 8 The semiconductor device after forming the P+ region and the P-type bridge region according to the method of the embodiment Figure 1 Schematic diagram of the cross section of BB'; Description of reference numerals: 1. Substrate; 2. Epitaxial layer; 3. CSL layer; 4. First hard mask layer; 5. P-well region injection window; 6. P-well region; 7. Dielectric silicon nitride spacer layer; 8. N+ region; 9. Second hard mask layer; 10. P+ region injection window; 11. P+ region; 12. P-type bridge region injection window; 13. P-type bridge region; 14. Gate oxide layer; 15. Gate polysilicon; 16. Dielectric layer; 17. Ohmic contact metal layer; 18. Source metal layer. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0028] Figure 1 The layout structure of a silicon carbide power MOSFET cell according to the manufacturing method of the present invention is shown. Figure 2 and Figure 3 The cross-sectional views of the silicon carbide MOSFET cells formed according to the manufacturing method of the present invention are respectively shown. Figure 4-Figure 8 The various steps of the manufacturing process of the MOSFET with a P-type bridge of the present invention are described.

[0029] The inventors found that in the layout design of silicon carbide MOSFET, silicon carbide MOSFET cells have higher channel density than linear cells, and therefore have lower channel resistance, thereby achieving lower on-resistance. However, due to the large electric field on the gate oxide layer at the corners of the silicon carbide MOSFET cells and the center of the JFET area, the device will break down prematurely. Providing a P-type bridge shielding area at the corner can shield the large electric field on the gate oxide layer at the corner and the center of the JFET area, preventing the device from breaking down prematurely and protecting the gate oxide layer.

[0030] In view of this, the present invention provides a silicon carbide MOSFET layout structure and a manufacturing method, which are used to solve the problem in the prior art that the local electric field faced by the device is too large while maintaining a low on-resistance, resulting in reduced device reliability.

[0031] Example 1 like Figure 1 A silicon carbide MOSFET cell structure is shown, comprising: four square silicon carbide MOSFET cells, the four square silicon carbide MOSFET cells are neatly arranged in a square, and there are channels with equal distances between every two square silicon carbide MOSFET cells; a cross-shaped JFET area is provided at the center of the square; a P-type bridge area 13 is provided on the cross-shaped JFET area, and the P-type bridge area 13 connects the corners of any two square silicon carbide MOSFET cells located in the diagonal direction.

[0032] The present invention aims at the problem of premature breakdown of the silicon carbide power MOSFET cell structure in the blocking state, and proposes a method of connecting the square cells using a P-type bridge. The present invention reduces the electric field strength of the silicon carbide power MOSFET gate oxide layer and the cell corner without adding process steps, avoids premature breakdown of the silicon carbide power MOSFET, and ensures the reliability of the silicon carbide power MOSFET while reducing the on-resistance of the silicon carbide power MOSFET.

[0033] In order to avoid the problem that the square cell given in the prior art has a large electric field in the JFET area at the corner, which easily causes the silicon carbide square cell to break down prematurely. Therefore, the present invention is proposed. In the present invention, a P-type bridge connects the corners of two diagonal square cells, which can shield the high electric field at the corners and ensure the breakdown voltage of the device. And the specific square silicon carbide MOSFET cell structure is as follows Figure 2 and Figure 3As shown, specifically, the square silicon carbide MOSFET cell includes a substrate 1, an epitaxial layer 2 and a CSL layer 3 from bottom to top, a first hard mask layer 4 is provided on the upper layer of the CSL layer 3, a P-well region injection window 5 for P-well region ion injection is etched on the first hard mask layer 4, the P-well region ion injection window 5 for P-well region ion injection is injected into the P-well region ions to obtain a P-well region 6, a P+ region 11 is provided in the middle of the P-well region 6, N+ regions 8 are also provided in the P-well region 6 on both sides of the P+ region 11, an ohmic contact metal layer 17 is provided above the P+ region 11 and the N+ region 8, a gate oxide layer 14, a gate polysilicon 15 and a dielectric layer 16 are provided above the CSL layer 3, the P-well region 6 and the N+ region 8 from bottom to top, a source metal layer 18 is provided between the dielectric layer 16 and the ohmic contact metal layer 17, and the P-type bridge region 13 is connected to the gate oxide layer 14.

[0034] Specifically, the silicon carbide MOSFET layout structure formed by the silicon carbide MOSFET cell structure is formed by a periodic array of multiple silicon carbide MOSFET cell structures along the X direction and the Y direction.

[0035] Specifically, a plurality of silicon carbide MOSFET cell structures are arranged in a periodic matrix.

[0036] Example 2 A method for manufacturing a silicon carbide MOSFET layout structure comprises the following steps: like Figure 4 As shown, an epitaxial layer 2 and a CSL layer 3 are grown from bottom to top on a substrate 1; wherein the epitaxial layer 2 is an n-type epitaxial layer, and the CSL layer 3 is an n-type CSL layer 3, or after a uniformly doped epitaxial layer 2 is grown on the substrate 1, ion implantation is performed to generate the CSL layer 3.

[0037] Preferably, the substrate 1 is a 4H-SiC n-type heavily doped low resistivity substrate with a resistivity of 0.015Ω·cm~0.025Ω·cm; the epitaxial layer 2 is lightly doped, and the doping concentration of the epitaxial layer 2 is 1×10 15 cm -3 ~3×10 16 cm -3 ; The doping concentration of CSL layer 3 is 1×10 16 cm -3 ~1×10 17 cm -3 .

[0038] like Figure 5As shown, a first hard mask layer 4 is formed on the surface of the CSL layer 3, and the hard mask layer is etched using a mask to expose a P-well region injection window 5 for ion injection into the P-well region; p-type (eg, aluminum ion) injection is performed to form a P-well region 6; The composition of the first hard mask layer 4 from bottom to top includes the following options: Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide layer), or ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, or ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum), or ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer) Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer), metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum).

[0039] The P-well region implantation window 5 only needs to be etched to the ion implantation blocking layer of the first hard mask layer 4 .

[0040] The ions used to make the P-well region 6 are aluminum ions. To achieve a sufficient breakdown voltage, the doping concentration of the P-well region 6 is 1×10 18 cm -3 ~3×10 18 cm -3 The doping concentration at this level is high enough so that the barrier at the source end of the channel is not lowered by the voltage applied to the drain.

[0041] In order to avoid the threshold voltage being too high, the P-well region 6 adopts a reverse doping distribution, with low surface doping concentration and high doping concentration deep below. Since silicon carbide is a wide bandgap semiconductor material, it has a larger PN junction built-in electric field. Silicon carbide can be used to make normally-off accumulation channel MOSFETs. Therefore, the doping concentration in the channel region is 7×10 16 cm -3 To p-type doping 5×10 16 cm -3 between.

[0042] Next, a uniform dielectric silicon nitride layer is deposited and carpet-etched to the same thickness, such as Figure 6 As shown, a uniform dielectric silicon nitride spacer 7 is formed on the side wall of the first hard mask layer 4; the dielectric silicon nitride spacer 7 is used to realize the self-aligned channel of the MOSFET; and n-type implantation is performed to form an N+ region 8.

[0043] The ions used to make the N+ region 8 are nitrogen ions; the peak concentration of the N+ region should be 1×10 20 cm -3The thickness of the dielectric silicon nitride spacer 7 should not exceed 0.5 μm to form a shorter channel of no more than 0.5 μm, thereby reducing the resistance of the channel region and thus reducing the on-resistance of the device.

[0044] The dielectric silicon nitride spacer layer 7 and the first hard mask layer 4 are removed, and a second hard mask layer 9 is formed, and a mask is used to etch out a window 10 for implanting the P+ region and a window 12 for implanting the P-type bridge region. Figure 7 and Figure 8 As shown; p-type ion implantation is performed to form a P+ region 11 and a P-type bridge region 13, and after the implantation is completed, the second hard mask layer 9 is removed; The second hard mask layer 9 has the following composition from bottom to top: an ion implantation barrier layer (e.g., a silicon dioxide layer), an oxide layer (e.g., silicon dioxide), or; an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, or; Ion implantation barrier layer (e.g., silicon dioxide layer), polysilicon layer, metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum), or; an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, an oxide layer (e.g., a silicon dioxide layer), or; Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

[0045] The ions used to make the P+ region 11 and the P-type bridge region 13 are both aluminum ions.

[0046] Next, a cap layer composed of carbon is deposited, and a high-temperature thermal annealing is performed in an inert gas atmosphere to activate the implanted ions; after the annealing is completed, the cap layer is removed; The inert gas is nitrogen or argon; the temperature of the high temperature thermal annealing is 1500° C. to 1900° C., and the time of the high temperature thermal annealing is 8 minutes to 15 minutes.

[0047] like Figure 2 and Figure 3As shown, the subsequent manufacturing is carried out through the standard MOSFET manufacturing process; first, the surface of the wafer obtained above is cleaned; then, a gate oxide layer 14 is formed by thermally oxidizing silicon carbide and annealing; a layer of gate polysilicon 15 is deposited on the gate oxide layer 14, and a gate region is etched out using a mask; then, a layer of dielectric layer 16 is deposited on the gate region of the gate polysilicon 15, and a window of the source region is etched out using a mask, and a source metal forming a source metal layer 18 is injected into the window of the source region; at the same time, an ohmic contact metal layer 17 is sputtered between two adjacent dielectric layers 16 and high-temperature thermal annealing is performed to form an ohmic contact between the ohmic contact metal layer 17, the N+ region 8 and the P+ region 11; the source metal is evaporated and the source region is etched out using a mask; then, back-side scribing, cleaning and substrate thinning processes are performed, and ohmic contact metal and drain metal (the drain metal is a drain electrode) are formed on the back side.

[0048] The ohmic contact metal layer 17 may be made of nickel, titanium, tungsten, tantalum, molybdenum, aluminum or alloys thereof; the source metal layer 18 may be made of aluminum.

[0049] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A silicon carbide MOSFET cell structure, characterized in that: include: Four square silicon carbide MOSFET cells, each two of which have channels with equal distances between them; The four square silicon carbide MOSFET cells are neatly arranged in a square, with a cross-shaped JFET region at the center of the square; a P-type bridge region (13) is provided on the cross-shaped JFET region, and the P-type bridge region (13) connects the corners of any two square silicon carbide MOSFET cells located in the diagonal direction.

2. A silicon carbide MOSFET cell structure according to claim 1, characterized in that: The square silicon carbide MOSFET cell comprises, from bottom to top, a substrate (1), an epitaxial layer (2) and a CSL layer (3); a first hard mask layer (4) is provided on the upper layer of the CSL layer (3); a P-well region injection window (5) for P-well region ion injection is etched on the first hard mask layer (4); P-well region ions are injected into the P-well region injection window (5) to obtain a P-well region (6); a P+ region (11) is provided in the middle of the P-well region (6); and the P-well regions (12) on both sides of the P+ region (11) are provided with a P+ region (13). 6) is also provided with an N+ region (8), an ohmic contact metal layer (17) is provided above the P+ region (11) and the N+ region (8), a gate oxide layer (14), a gate polysilicon (15) and a dielectric layer (16) are provided above the CSL layer (3), the P-well region (6) and the N+ region (8) from bottom to top, a source metal layer (18) is provided between the dielectric layer (16) and the ohmic contact metal layer (17), and the P-type bridge region (13) is connected to the gate oxide layer (14).

3. The silicon carbide MOSFET layout structure formed by the silicon carbide MOSFET cell structure according to claim 2, characterized in that: The silicon carbide MOSFET layout structure is formed by a periodic array of multiple silicon carbide MOSFET cell structures along the X direction and the Y direction.

4. The silicon carbide MOSFET layout structure according to claim 3, characterized in that: A plurality of the silicon carbide MOSFET cell structures are arranged in a periodic matrix.

5. The method for manufacturing a silicon carbide MOSFET layout structure according to claim 4, characterized in that: The steps include: Growing an epitaxial layer (2) and a CSL layer (3) from bottom to top on a substrate (1), wherein the epitaxial layer (2) and the CSL layer (3) are both n-type, and the substrate (1) is an n-type silicon carbide substrate, or after growing a uniformly doped epitaxial layer (2) on the substrate (1), ion implantation is performed to generate the CSL layer (3); Performing multiple ion implantations on the CSL layer (3) to generate a P-well region (6), an N+ region (8), a P+ region (11), and a P-type bridge region (13); performing high temperature thermal annealing in an inert gas atmosphere to activate the implanted ions; An isolation gate region is prepared on the CSL layer (3) by a standard MOSFET process, wherein the isolation gate region comprises a gate oxide layer (14) and a gate polysilicon (15) arranged from bottom to top, a dielectric layer (16) is deposited on the gate polysilicon (15), an ohmic contact metal layer (17) is sputtered between two adjacent dielectric layers (16) to form an ohmic contact metal layer (17) with the N+ region (8) and the P+ region (11), and a source metal layer (18) is formed by evaporating a source metal between the dielectric layer (16) and the ohmic contact metal layer (17) for connection; A drain metal is deposited beneath the n-type silicon carbide substrate.

6. The method for manufacturing a silicon carbide MOSFET layout structure according to claim 5, characterized in that: The substrate (1) is a 4H-SiC n-type heavily doped low-resistivity substrate, the resistivity of the substrate (1) is 0.015Ω·cm~0.025Ω·cm, and the doping concentration of the epitaxial layer (2) is 1×10 15 cm -3 ~3×10 16 cm -3 ; The doping concentration of the CSL layer (3) is 1×10 16 cm -3 ~1×10 17 cm -3 .

7. The method for manufacturing a silicon carbide MOSFET layout structure according to claim 5, characterized in that: The P-well region (6) adopts reverse doping distribution, and when doping, the doping concentration on its surface is low, and the doping concentration deep below it is high; The surface doping concentration of the P-well region (6) is n-type doping 7×10 16 cm -3 To p-type doping 5×10 16 cm -3 , the peak doping concentration of the P-well region (6) is greater than 1×10 18 cm -3 .

8. The method for manufacturing a silicon carbide MOSFET layout structure according to claim 5, characterized in that: The P-type bridge region (13) and the P+ region (11) have the same doping distribution, and the depths of the P-type bridge region (13) and the P+ region (11) are the same as the P-well region (6), and the peak doping concentrations of the P-type bridge region (13) and the P+ region (11) are greater than 1×10 19 cm -3 , the peak concentration of the N+ region (8) is not less than 1×10 20 cm -3 .

9. The method for manufacturing a silicon carbide MOSFET layout structure according to claim 5, characterized in that: The temperature of the high temperature thermal annealing is 1500° C. to 1900° C., and the time of the high temperature thermal annealing is 8 minutes to 15 minutes.

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