Computer bottom plate with reconfigurable functions
By integrating the COM Express module with FPGA, it provides rich interface resources, solves the problem of insufficient interfaces of existing computer baseboards, achieves high integration and generalization, adapts to a variety of application scenarios, and reduces development costs and cycles.
Patent Information
- Application Number
- CN202420325002.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-21
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-02-21
AI Technical Summary
When faced with complex applications, the existing computer baseboards lack the type and number of interfaces, and require external custom expansion boards, resulting in high development costs, long cycles and difficult to reuse.
Integrate resources and functions of COM Express module with FPGA, connect through PCIe high-speed bus, integrate VGA, USB, and LAN interface circuits, and provide rich IO interfaces through FMC high-speed connectors, adapt to a variety of peripheral daughter cards to realize functions and resource reconstruction.
It realizes a computer baseboard with high integration, rich functions, high degree of generalization, low transformation difficulty and low cost, and is adapted to a variety of application scenarios and reduces development costs and cycles.
Smart Images
Figure CN222145507U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of computer baseboards, and in particular relates to a computer baseboard with reconfigurable functions. Background Art
[0002] At present, common computer motherboards only provide some conventional hardware interfaces such as USB, RS232, LAN, VGA, PCIe, etc., which can be connected to simple peripherals such as display screens. Their applications are obviously limited when faced with complex interfaces, high real-time processing requirements, and high versatility requirements. Specifically, the current computer motherboards provide few types of interfaces and a small number of interfaces. When faced with more complex applications, it is often necessary to use its PCIe / PCI slots and other external separate customized expansion boards for interface expansion. At the same time, since expansion boards are often designed based on FPGA, the development cost of expansion boards is high, and most of them are designed to meet a single application requirement. It is difficult to reuse them in new requirements, resulting in high overall costs. Multiple development also leads to a longer overall development cycle and increased difficulty. Utility Model Content
[0003] The purpose of the utility model is to provide a computer baseboard with reconfigurable functions, aiming to solve the above problems. The utility model integrates the resources and functions of COM Express module and FPGA, and takes into account the versatility while combining the advantages of both. By adapting to different peripheral daughter cards, it can cover more application scenarios.
[0004] The utility model is mainly realized through the following technical solutions:
[0005] A functionally reconfigurable computer baseboard comprises a COM Express module, an FPGA and an FMC high-speed connector connected in sequence from front to back, wherein the COM Express module and the FPGA are integrated on a board, and the COM Express module is connected to the FPGA via a PCIe high-speed bus; the COM Express module is connected with a VGA interface circuit, a USB interface circuit and a LAN interface circuit, wherein the VGA interface circuit comprises a first filter circuit, an ESD protection unit, a second filter circuit and a VGA interface connector, wherein the VGA resources of the COM Express module are respectively connected to the first filter circuit and the ESD protection unit, wherein the first filter circuit is connected to the VGA interface connector, and the ESD protection unit is connected to the VGA interface connector via the second filter circuit; the USB interface resources of the COM Express module are connected to the USB interface circuit via the ESD protection unit; the LAN interface circuit comprises an interface conversion chip, and one PCIe channel of the COM Express module is connected to the interface conversion chip to convert into Ethernet.
[0006] In order to better implement the present utility model, further, the VGA-R interface, VGA-G interface and VGA-B interface of the COM Express module are respectively connected to the first filtering circuit, and the VGA-VSYNC interface, VGA-HSYNC interface, VGA-I2C-CLK interface and VGA-I2C-DAT interface of the COM Express module are respectively connected to the ESD protection unit.
[0007] In order to better implement the utility model, further, the USB interface circuit includes two USB2.0 interfaces and two USB3.0 interfaces, and the COM Express module is provided with 6 PCIe×1 and 1 Ethernet resource.
[0008] In order to better implement the utility model, further, the chip model of the ESD protection unit is TPD7S019-15DBQR; the model of the interface conversion chip is WGI210IT S LJXT.
[0009] In order to better implement the present invention, further, the FPGA is connected to a DDR4 circuit, and the multi-channel IO resources of the FPGA are respectively connected to the chip select, clock, data and block pins of the DDR4 circuit to realize data reading of the DDR4 chip; the DDR4 circuit is composed of 4 MT40A512M16LY-062E IT model DDR4 chips, which serve as the DDR memory of the FPGA to form a 4G Byte storage space.
[0010] In order to better implement the utility model, further, it also includes a clock circuit connected to the FPGA, the clock circuit includes a PCIe reference clock circuit and a DDR4 clock reference circuit, the PCIe reference clock circuit is used to provide a PCIE reference clock for the FPGA to realize PCIe bus data communication; the DDR4 clock reference circuit is used to provide a 200MHz reference clock for the DDR4 circuit.
[0011] In order to better implement the utility model, further, the DDR4 clock reference circuit includes a crystal oscillator chip and a filter, the crystal oscillator chip is connected to the DDR4 circuit through the filter, and the model of the crystal oscillator chip is X075L-AGTL-200MHz.
[0012] In order to better implement the utility model, further, the FPGA is connected to a Flash circuit for storing the engineering solidification files of the FPGA; the multi-channel IO resources of the FPGA are respectively connected to the chip selection and data pins of the Flash circuit to realize data interaction between the FPGA and the Flash circuit.
[0013] In order to better implement the present invention, further, the Flash circuit includes two S25FL512SAGMFVG10 Flash chips, and the storage capacity of a single chip is 512M bit.
[0014] The beneficial effects of the utility model are as follows:
[0015] (1) High integration and small size: The utility model integrates the COM Express module and FPGA on a board. Compared with the integration through cables or backplanes, the utility model has a higher integration and a smaller size;
[0016] (2) Rich functions and interfaces: The utility model integrates COM Express module and FPGA, which can provide common USB, LAN, VGA and other interfaces of ordinary computers, as well as multiple DI, DO, AD, DA and serial bus interfaces, greatly enriching the interface resources and expanding the scope of application;
[0017] (3) High degree of commonality, low difficulty in transformation and reconstruction, and low cost: The utility model designs a unified and standardized external interface. Therefore, it allows the adaptation of a variety of peripheral daughter cards, and has a high degree of commonality. When facing new application requirements, it can be reused, and only a small amount of transformation work needs to be done on the peripheral daughter card. The overall cost and difficulty of transformation are greatly reduced.
[0018] (4) The COM Express module is used to provide the functions of a general computer. The FPGA module is used for real-time processing of signal data and provides abundant external interface resources. The high-speed connector is used for interconnection between the baseboard and the peripheral daughter card. The utility model integrates the functions and resources of the COM Express module and the FPGA module, has the functions and interfaces of a general computer, and also provides multiple AD, DA, DI, DO and serial data ports. At the same time, it is compatible with a variety of peripheral daughter cards, has a wide range of applications, and has good practicality. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a principle block diagram of the functionally reconfigurable computer baseboard of the utility model;
[0020] Figure 2 This is the schematic diagram of the VGA interface circuit of the COM Express module;
[0021] Figure 3 This is the USB interface circuit diagram of the COM Express module;
[0022] Figure 4 This is the LAN interface circuit diagram of the COM Express module;
[0023] Figure 5 This is the schematic diagram of the DDR4 circuit for FPGA;
[0024] Figure 6 This is the schematic diagram of the Flash circuit of the FPGA;
[0025] Figure 7 This is the PCIe reference clock circuit diagram;
[0026] Figure 8 This is the clock circuit diagram of the FPGA. DETAILED DESCRIPTION
[0027] Embodiment 1:
[0028] A computer baseboard with reconfigurable functions, such as Figure 1 As shown, it includes a COM Express module, FPGA and a high-speed connector. The PCIe high-speed bus is used for data exchange between the COM Express module and the FPGA. The overall external adapter interface uses an FMC high-speed connector. The COM Express module can simulate the functions of an ordinary computer through a simple interface design, and has common USB ports, LAN ports, VGA ports, etc., and can be connected to external devices such as display screens, keyboards and mice, and switches. FPGA has good real-time performance and efficient signal processing capabilities, and has rich IO resources. After a series of circuit designs, the IO resources are led out through a high-speed connector to obtain various types of external interfaces. During use, the utility model can deploy operating systems and software, provides various types of external interfaces, and is compatible with peripheral boards and cards for further functional expansion.
[0029] Preferably, if Figure 1 As shown, the COM Express module is connected with a VGA interface circuit, a USB interface circuit and a LAN interface circuit. Preferably, the COM Express module is COM Express Type6.
[0030] Furthermore, if Figure 1 and Figure 2 As shown in the figure, in the VGA interface circuit, after the VGA resource of the COM Express module is subjected to ESD protection and filtering, it can be led out to the external interface connector and connected to an external display. The ESD chip protection uses the TPD7S019-15DBQR type.
[0031] Furthermore, if Figure 1 and Figure 3As shown in the figure, in the USB interface circuit, the COM Express module provides multiple USB interface resources, which are similar to the VGA port design. After simple ESD protection treatment, they can be led out to the external interface. Two USB2.0 and two USB3.0 interfaces are designed.
[0032] Furthermore, if Figure 1 and Figure 4 As shown in the figure, in the LAN interface circuit, the COM Express module provides 6 PCIe×1 and 1 Ethernet resources. One PCIe is converted into Ethernet through the interface conversion chip, so that two Ethernet communications can be realized. The interface chip model used is Intel's WGI210IT S LJXT bridge chip.
[0033] Preferably, if Figure 1 As shown, the FPGA is connected to a DDR4 circuit, a Flash circuit and a clock circuit.
[0034] Furthermore, if Figure 1 and Figure 5 As shown in the figure, in the DDR4 circuit, the FPGA's multiple IO resources are connected to the chip select, clock, data and block pins of the DDR4 chip to realize the data reading function of the DDR4 module. Four pieces of Micron's MT40A512M16LY-062E IT (DDR4-3200) are used as DDR memory, which constitutes a total of 4GByte of storage space.
[0035] Furthermore, if Figure 1 and Figure 6 As shown in the figure, the Flash circuit is mainly used to store FPGA engineering fixed files. Figure 6 As shown in the figure, the FPGA's multiple IO resources are connected to the chip select, data and other pins of the Flash chip, and the SPI clock is provided to realize the data interaction between the FPGA and the Flash. Two Sapnsion's S25FL512SAGMFVG10 Flash chips are used, with a single chip storage capacity of 512M bit.
[0036] Furthermore, the clock circuit mainly includes a PCIe reference clock circuit and a DDR4 clock reference circuit.
[0037] like Figure 7As shown in the figure, the PCIe reference clock circuit is implemented as follows: The frequency of PCIE_REFCLK1_P and PCIE_REFCLK1_N is 100MHz, which is the PCIE reference clock provided by FPGA, and finally realizes PCIe bus data communication. Since the clock BUFFER outputs the LVPECL level, the GTHbank of FPGA needs to perform level matching when receiving the LVPECL level clock signal.
[0038] like Figure 8 As shown, the DDR4 clock reference circuit uses a crystal oscillator chip, which is filtered and sent to DDR4 to provide a 200MHz reference clock for its normal operation. The selected crystal oscillator model is X075L-AGTL-200MHz.
[0039] Preferably, an FMC high-speed connector is used, which can support hundreds of high-speed pins, is tightly arranged, has a small size, and can achieve a data throughput rate of several Gb / s, and can support the transmission of discrete line signals, analog signals, general interface signals, and high-speed interface signals. The external IO resources provided by the FMC connector include: 16 DIs, 32 DOs, 16 ADs, 8 DAs, and 16 UART transceiver pairs.
[0040] By unifying and standardizing the pin definitions on the FMC connector, the baseboard can be connected to a variety of external adapter daughter cards to meet application requirements in different usage scenarios.
[0041] The utility model integrates the functions and resources of an embedded computer module (COM Express module) that complies with the COMExpress specification with an FPGA, and has the characteristics of simple operation and low software development difficulty of a general computer, as well as the characteristics of fast processing capability and high real-time performance of an FPGA, and provides a rich IO interface. Considering its versatility, a standardized external interface design is adopted, and a variety of peripheral function modules can be adapted, ultimately achieving the purpose of functional reconfiguration and facilitating further integration.
[0042] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.
Claims
1. A functionally reconfigurable computer chassis, characterized in that: The invention comprises a COM Express module, an FPGA and an FMC high-speed connector connected in sequence from front to back, wherein the COM Express module and the FPGA are integrated on a board, and the COM Express module is connected to the FPGA via a PCIe high-speed bus; the COM Express module is connected to a VGA interface circuit, a USB interface circuit and a LAN interface circuit, wherein the VGA interface circuit comprises a first filter circuit, an ESD protection unit, a second filter circuit and a VGA interface connector, and the VGA resources of the COM Express module are respectively connected to the first filter circuit and the ESD protection unit, wherein the first filter circuit is connected to the VGA interface connector, and the ESD protection unit is connected to the VGA interface connector via the second filter circuit; the USB interface resources of the COM Express module are connected to the USB interface circuit via the ESD protection unit; the LAN interface circuit comprises an interface conversion chip, and one PCIe of the COM Express module is connected to the interface conversion chip for conversion to Ethernet.
2. The functionally reconfigurable computer chassis according to claim 1, characterized in that: The VGA-R interface, VGA-G interface and VGA-B interface of the COMExpress module are respectively connected to the first filtering circuit, and the VGA-VSYNC interface, VGA-HSYNC interface, VGA-I2C-CLK interface and VGA-I2C-DAT interface of the COMExpress module are respectively connected to the ESD protection unit.
3. The functionally reconfigurable computer chassis according to claim 1, characterized in that: The USB interface circuit includes two USB2.0 interfaces and two USB3.0 interfaces, and the COM Express module is provided with 6 PCIe×1 and 1 Ethernet resource.
4. A functionally reconfigurable computer chassis according to any one of claims 1 to 3, characterized in that: The chip model of the ESD protection unit is TPD7S019-15DBQR; the model of the interface conversion chip is WGI210ITSLJXT.
5. The functionally reconfigurable computer chassis according to claim 1, characterized in that: The FPGA is connected to a DDR4 circuit, and the multiple IO resources of the FPGA are respectively connected to the chip select, clock, data and block pins of the DDR4 circuit to realize data reading of the DDR4 chip; the DDR4 circuit is composed of 4 MT40A512M16LY-062E IT model DDR4 chips, which serve as the DDR memory of the FPGA to form a 4G Byte storage space.
6. The functionally reconfigurable computer chassis according to claim 5, characterized in that: It also includes a clock circuit connected to the FPGA, the clock circuit includes a PCIe reference clock circuit and a DDR4 clock reference circuit, the PCIe reference clock circuit is used to provide a PCIE reference clock for the FPGA to realize PCIe bus data communication; The DDR4 clock reference circuit is used to provide a 200 MHz reference clock for the DDR4 circuit.
7. The functionally reconfigurable computer chassis according to claim 6, characterized in that: The DDR4 clock reference circuit includes a crystal oscillator chip and a filter. The crystal oscillator chip is connected to the DDR4 circuit through the filter. The model of the crystal oscillator chip is X075L-AGTL-200MHz.
8. The functionally reconfigurable computer chassis according to claim 1, characterized in that: The FPGA is connected to a Flash circuit for storing the engineering solidification files of the FPGA; the multi-channel IO resources of the FPGA are respectively connected to the chip selection and data pins of the Flash circuit to realize data interaction between the FPGA and the Flash circuit.
9. The functionally reconfigurable computer chassis according to claim 8, characterized in that: The Flash circuit includes two S25FL512SAGMFVG10 Flash chips, and the storage capacity of a single chip is 512M bits.