Distributed temperature measurement system

Abstract

The utility model discloses a distributed temperature measurement system, and the system is characterized in that a pulse laser light source module generates a temperature measurement pulse signal; the wavelength division multiplexing module is electrically connected with the pulse laser light source module, the wavelength division multiplexing module is connected with the temperature measurement optical fiber, the temperature measurement optical fiber is used for transmitting temperature measurement pulse signals, and the wavelength division multiplexing module is used for collecting the temperature measurement pulse signals in the temperature measurement optical fiber and demultiplexing the temperature measurement pulse signals to obtain two paths of backward scattering signals; the photoelectric detection module is electrically connected with the wavelength division multiplexing module and is used for converting the two paths of backscattering signals into two paths of level signals; the RFSoC data acquisition module is connected with the photoelectric detection module through a first radio frequency connecting line and is used for acquiring two paths of level signals according to a preset sampling rate and reducing noise of the two paths of level signals; and the upper computer is electrically connected with the RFSoC data acquisition module and is used for determining temperature information. Functions are integrated in the same component, the occupied space of the system is reduced, the complex design is simplified, and the stability of the system is improved.

Description

Technical Field

[0001] The present application belongs to the field of distributed temperature measurement technology, and in particular, relates to a distributed temperature measurement system. Background Art

[0002] With the development of data processing technology, the ability of data models to process a wide range of information has been widely improved. In terms of temperature signal processing, compared with traditional single-point temperature measurement technology, distributed fiber optic sensing technology has the advantage of distributed temperature measurement and can achieve integrated and full-coverage temperature information measurement on the temperature measurement object. The data acquisition of the distributed temperature measurement system is mainly achieved through parallel computing of analog-to-digital converter (ADC) chips and field-programmable gate arrays (FPGA).

[0003] At present, distributed temperature measurement systems often use ADC, FPGA and ARM processors to independently develop subsystems for signal acquisition and signal noise reduction, which results in a large size, complex design and poor stability of the entire distributed temperature measurement system. Utility Model Content

[0004] The embodiment of the present application provides a distributed temperature measurement system, which uses an RFSoC data acquisition module to replace the design of independent subsystem development of ADC, FPGA and ARM processor, integrates the functions of ADC, FPGA and ARM processor into the same component, reduces the occupied space of the distributed temperature measurement system, simplifies the complex design, and improves the stability of the system.

[0005] In a first aspect, an embodiment of the present application provides a distributed temperature measurement system, which includes a host computer, a pulsed laser light source module, a wavelength division multiplexing module, a temperature measurement optical fiber, a photoelectric detection module, and a radio frequency system-on-chip RFSoC data acquisition module;

[0006] The pulse laser light source module is used to generate a temperature measurement pulse signal;

[0007] The wavelength division multiplexing module is electrically connected to the pulse laser light source module, and the wavelength division multiplexing module is connected to the temperature measurement optical fiber. The temperature measurement optical fiber is used to transmit the temperature measurement pulse signal. The wavelength division multiplexing module is used to collect the temperature measurement pulse signal in the temperature measurement optical fiber, and demultiplex the temperature measurement pulse signal to obtain two backscattering signals.

[0008] The photoelectric detection module is electrically connected to the wavelength division multiplexing module and is used to convert the two-way backscattering signals into two-way level signals;

[0009] The RFSoC data acquisition module is connected to the photoelectric detection module via a first RF connection line, and is used to collect two-way level signals according to a preset sampling rate, and to reduce noise of the two-way level signals;

[0010] The host computer is electrically connected to the RFSoC data acquisition module and is used to determine the temperature information according to the two-way level signals after noise reduction.

[0011] In one possible implementation, the RFSoC data acquisition module includes a signal input submodule, a clock submodule and an RFSoC chip;

[0012] The signal input submodule is electrically connected to the RFSoC chip. The signal input submodule is used to obtain two-way level signals in the photoelectric detection module through the first RF connection line, and convert the two-way level signals after gain amplification into two-way differential signals. The RFSoC chip is used to collect the two-way differential signals after gain amplification in the signal input module according to a preset sampling rate, and convert the differential signals into two-way level signals, and reduce the noise of the two-way level signals.

[0013] The clock submodule is electrically connected to the RFSoC chip and is used to generate a high-frequency clock signal provided to the RFSoC chip.

[0014] In a possible implementation, the signal input submodule includes an input signal source unit and a fully differential amplifier;

[0015] The input signal source unit is electrically connected to the fully differential amplifier. The input signal source unit is used to obtain two-way level signals transmitted by the photoelectric detection module through the first RF connection line. The fully differential amplifier is used to achieve gain amplification of the two-way level signals and convert the two-way level signals after gain amplification into two differential signals.

[0016] In one possible implementation, the clock submodule includes a clock synthesizer and a broadband radio frequency synthesizer;

[0017] The clock synthesizer is electrically connected to the broadband RF synthesizer. The clock synthesizer is used to generate an initial clock signal according to the configuration information in the RFSoC chip. The broadband RF synthesizer is used to amplify the clock frequency and convert the initial clock signal into a high-frequency clock signal.

[0018] In one possible implementation, the RFSoC chip includes an analog-to-digital converter ADC, a field programmable gate array FPGA unit, and an ARM processor;

[0019] The analog-to-digital converter ADC is electrically connected to the field programmable gate array FPGA unit, and the ARM processor is electrically connected to the FPGA unit;

[0020] The ADC is used to collect the two differential signals after gain amplification in the signal input module according to a preset sampling rate, and convert the differential signals into two level signals;

[0021] The FPGA unit is used to reduce noise on the two-way level signals when receiving the control instruction sent by the ARM processor to obtain the two-way level signals after noise reduction.

[0022] In one possible implementation, the RFSoC data acquisition module further includes a data storage submodule;

[0023] The data storage submodule is connected to the RFSoC chip via the advanced scalable interface AXI4 bus, and is used to obtain and store two level signals in the RFSoC chip.

[0024] In one possible embodiment, the data storage submodule includes a DDR4 memory for storing two-way level signals in the RFSoC chip.

[0025] In one possible implementation, the RFSoC data acquisition module further includes a data transmission submodule;

[0026] The data transmission submodule includes an Ethernet cable for transmitting two-way level signals after noise reduction.

[0027] In a possible embodiment, the RFSoC data acquisition module is connected to the pulse laser light source module via a second RF connection line, and the RFSoC data acquisition module is also used for:

[0028] The driving level signal is used to drive the pulse laser light source module to generate a temperature measurement pulse signal.

[0029] In one possible embodiment, the RFSoC chip includes a digital-to-analog converter DAC, which is used to obtain control information from a host computer, generate a drive signal according to the control information, and convert the drive signal into a drive level signal.

[0030] The distributed temperature measurement system of the embodiment of the present application includes a host computer, a pulsed laser light source module, a wavelength division multiplexing module, a temperature measurement optical fiber, a photoelectric detection module and a radio frequency system-on-chip RFSoC data acquisition module; the pulsed laser light source module is used to generate a temperature measurement pulse signal; the wavelength division multiplexing module is electrically connected to the pulsed laser light source module, the wavelength division multiplexing module is connected to the temperature measurement optical fiber, the temperature measurement optical fiber is used to transmit the temperature measurement pulse signal, the wavelength division multiplexing module is used to collect the temperature measurement pulse signal in the temperature measurement optical fiber, and demultiplex the temperature measurement pulse signal to obtain two backscattering signals; the photoelectric detection module is electrically connected to the wavelength division multiplexing module, and is used to convert the two backscattering signals into two level signals; the RFSoC data acquisition module is connected to the photoelectric detection module through a first radio frequency connection line, and is used to collect the two level signals according to a preset sampling rate, and to reduce the noise of the two level signals; the host computer is electrically connected to the RFSoC data acquisition module, and is used to determine the temperature information according to the two level signals after noise reduction. In this way, the RFSoC data acquisition module replaces the design of independent subsystem development of ADC, FPGA and ARM processor, integrates the functions of ADC, FPGA and ARM processor into the same component, reduces the footprint of the distributed temperature measurement system, simplifies the complex design, and improves the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 It is a structural schematic diagram of a distributed temperature measurement system provided by an embodiment of the present application;

[0033] Figure 2 is a structural schematic diagram of a distributed temperature measurement system provided by another embodiment of the present application;

[0034] Figure 3 is a structural schematic diagram of a distributed temperature measurement system provided by another embodiment of the present application;

[0035] Figure 4 is a structural diagram of a distributed temperature measurement system provided in yet another embodiment of the present application;

[0036] Figure 5 is a structural diagram of a distributed temperature measurement system provided in yet another embodiment of the present application;

[0037] Figure 6 is a structural diagram of a distributed temperature measurement system provided in yet another embodiment of the present application;

[0038] Figure 7is a structural diagram of a distributed temperature measurement system provided in yet another embodiment of the present application;

[0039] Figure 8 is a structural diagram of a distributed temperature measurement system provided in yet another embodiment of the present application;

[0040] Fig. 9 is a structural diagram of a distributed temperature measurement system provided in yet another embodiment of the present application; DETAILED DESCRIPTION

[0041] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0042] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0043] With the development of data processing technology, the ability of data models to process a wide range of information has been widely improved. In terms of temperature signal processing, compared with traditional single-point temperature measurement technology, distributed fiber optic sensing technology has the advantage of distributed temperature measurement and can achieve integrated and full-coverage temperature information measurement on the temperature measurement object. The data acquisition of the distributed temperature measurement system is mainly achieved through parallel computing of analog-to-digital converter (ADC) chips and field-programmable gate arrays (FPGA).

[0044] At present, distributed temperature measurement systems often use ADC, FPGA and ARM processors to independently develop subsystems for signal acquisition and signal noise reduction, which results in a large size, complex design and poor stability of the entire distributed temperature measurement system.

[0045] In order to solve the problems of the prior art, the embodiment of the present application provides a distributed temperature measurement system. The distributed temperature measurement system provided by the embodiment of the present application is described in detail below through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0046] Figure 1 A schematic diagram of the structure of a distributed temperature measurement system provided by an embodiment of the present application is shown.

[0047] like Figure 1 As shown, the distributed temperature measurement system 100 provided in the embodiment of the present application includes: a host computer 110, a pulsed laser light source module 120, a wavelength division multiplexing module 130, a temperature measurement optical fiber 140, a photoelectric detection module 150 and a radio frequency system-on-chip RFSoC data acquisition module 160.

[0048] Among them, the pulse laser light source module 120 is used to generate a temperature measurement pulse signal. The wavelength division multiplexing module 130 is electrically connected to the pulse laser light source module 120, and the wavelength division multiplexing module 130 is connected to the temperature measurement optical fiber 140. The temperature measurement optical fiber 140 is used to transmit the temperature measurement pulse signal. The wavelength division multiplexing module 130 is used to collect the temperature measurement pulse signal in the temperature measurement optical fiber 140, and demultiplex the temperature measurement pulse signal to obtain two backscattering signals. The photoelectric detection module 150 is electrically connected to the wavelength division multiplexing module 130, and is used to convert the two backscattering signals into two level signals. The RFSoC data acquisition module 160 is connected to the photoelectric detection module 150 through a first RF connection line, and is used to collect two level signals according to a preset sampling rate, and to reduce the noise of the two level signals. The host computer 110 is electrically connected to the RFSoC data acquisition module 160, and is used to determine the temperature information based on the two level signals after noise reduction.

[0049] In some embodiments, the pulse laser light source module 120 generates and amplifies pulse light based on a driving level signal. The pulse laser light source module 120 includes a laser driving submodule, a laser, and an EDFA (Erbium Doped Fiber Amplifier) ​​erbium-doped fiber amplifier. The laser driving submodule is electrically connected to the laser, and the laser is electrically connected to the EDFA erbium-doped fiber amplifier. The laser driving submodule receives a driving level signal, generates a pulse current for driving the laser, and uses the pulse current to drive the laser to output an initial pulse light, whose repetition rate and pulse width meet the setting requirements of the driving signal. The initial pulse light is power amplified by the EDFA erbium-doped fiber amplifier, and the amplified pulse light can be transmitted over long distances in a multimode optical fiber. Here, the pulse light refers to a temperature measurement pulse signal.

[0050] In some embodiments, the temperature measurement pulse signal is transmitted in the temperature measurement optical fiber 140 and demultiplexed by the wavelength division multiplexing module 130. The amplified temperature measurement pulse signal is introduced into the temperature measurement optical fiber 140 for transmission, and the backscattered Stokes light and Anti-Stokes light in the transmission process are obtained by the wavelength division multiplexing module 130, so as to realize the demodulation of temperature information. According to the wavelength range of the two temperature signals, the two signals can be demultiplexed by wavelength division multiplexing WDM (Wavelength Division Multiplexing) and output to the photoelectric detection module 150. Here, the two backscattered signals include the backscattered Stokes light signal and the Anti-Stokes light signal.

[0051] In some embodiments, the photoelectric detection module 150 realizes the photoelectric conversion of two backscattered signals. It is understandable that by converting the two backscattered signals into two level signals, the temperature information can be calculated. The photoelectric detection module 150 includes a photoelectric conversion device, a trans-impedance amplifier (TIA) and a cascade amplifier. The photoelectric conversion device is electrically connected to the trans-impedance amplifier TIA, and the trans-impedance amplifier TIA is electrically connected to the cascade amplifier. The two demultiplexed Stokes optical signals and the Anti-Stokes optical signals pass through the photoelectric detection module 150 to realize the conversion of light intensity information to voltage information. This process can be implemented with the help of a variety of photoelectric conversion devices. For example, a biased photodiode LD, a photothermal effect converter or an avalanche photodiode APD, etc. As an example, the above functions are realized based on an avalanche photodiode (APD) and a trans-impedance amplifier TIA, and the gain amplification of the two level signals is realized with the help of a cascade amplifier. The photoelectric detection module 150 transmits the amplified two-way level signals to the Radio Frequency System-on-Chip (RFSoC) data acquisition module 160 through the radio frequency connection line to collect and reduce noise of the two-way level signals.

[0052] In some embodiments, the RFSoC data acquisition module 160 integrates the functions of ADC, FPGA and ARM processor to collect and reduce noise of two-way level signals.

[0053] In some embodiments, the host computer 110 is electrically connected to the RFSoC data acquisition module 160 to determine the temperature information based on the two-way level signal after noise reduction. As an example, the temperature information can be obtained by calculating the ratio of the two-way level signal. It can be understood that the two-way level signal is a level signal corresponding to the backscattered Stokes optical signal and a level signal corresponding to the Anti-Stokes optical signal.

[0054] In this way, the RFSoC data acquisition module replaces the design of independent subsystem development of ADC, FPGA and ARM processor, integrates the functions of ADC, FPGA and ARM processor into the same component, reduces the footprint of the distributed temperature measurement system, simplifies the complex design, and improves the stability of the system.

[0055] Based on this, in some embodiments, such as Figure 2 As shown, the RFSoC data acquisition module 160 may include a signal input submodule 161, a clock submodule 162 and an RFSoC chip 163;

[0056] The signal input submodule 161 is electrically connected to the RFSoC chip 163. The signal input submodule 161 is used to obtain two level signals in the photoelectric detection module through the first RF connection line, and convert the two level signals after gain amplification into two differential signals. The RFSoC chip 163 is used to collect the two differential signals after gain amplification in the signal input module according to a preset sampling rate, and convert the differential signals into two level signals, and reduce the noise of the two level signals;

[0057] The clock submodule 162 is electrically connected to the RFSoC chip 163 , and is used to generate a high-frequency clock signal provided to the RFSoC chip 163 .

[0058] It should be noted that only when the RFSoC chip obtains a high-frequency clock signal can the two differential signals after gain amplification in the signal input module be collected at a preset sampling rate.

[0059] In this way, the RFSoC data acquisition module, when including a clock submodule, can preset the sampling rate to collect the two differential signals after gain amplification in the signal input module.

[0060] Based on this, in some embodiments, such as Figure 3 As shown, the signal input submodule 161 may include an input signal source unit 1611 and a fully differential amplifier 1612;

[0061] The input signal source unit 1611 is electrically connected to the fully differential amplifier 1612. The input signal source unit 1611 is used to obtain two-way level signals transmitted by the photoelectric detection module through the first RF connection line. The fully differential amplifier 1612 is used to achieve gain amplification of the two-way level signals and convert the two-way level signals after gain amplification into two differential signals.

[0062] In some embodiments, the two-way level signal is a two-way level signal. The fully differential amplifier 1612 converts the level signals of the two single-ended inputs into differential signals. The fully differential amplifier 1612 is used for peripheral circuit design to realize the conversion of the single-ended input level signal to the differential signal. The signal input submodule 161 also includes an adjustment circuit, which controls the output voltage amplitude by adjusting the resistance in the circuit to ensure that the differential signal amplitude is within the safe voltage range of the RFSoC chip 163 and will not be in an overvoltage state, so as to ensure the internal safety of the RFSoC chip and the stability of the system.

[0063] In some embodiments, the signal input submodule 161 includes a first signal input submodule and a second signal input submodule, each used to receive one (single-ended) level signal of the two level signals. The fully differential amplifier 1612 includes a first fully differential amplifier and a second fully differential amplifier, each used to process one (single-ended) level signal of the two level signals.

[0064] In this way, two level signals can be obtained through the input signal source unit and differentially amplified. Only after the level signals are converted into differential signals can they be collected by the RFSoC chip.

[0065] Based on this, in some embodiments, such as Figure 4 As shown, the clock submodule 162 may include a clock synthesizer 1621 and a broadband RF synthesizer 1622;

[0066] The clock synthesizer 1621 is electrically connected to the broadband RF synthesizer 1622. The clock synthesizer 1621 is used to generate an initial clock signal according to the configuration information in the RFSoC chip. The broadband RF synthesizer 1622 is used to amplify the clock frequency and convert the initial clock signal into a high-frequency clock signal.

[0067] In some embodiments, the clock submodule 162 can be controlled by the SPI bus, and needs to be configured according to the configuration information in the RFSoC chip, that is, the actual clock frequency requirement. The clock synthesizer 1621 and the broadband RF synthesizer 1622 are used to generate a high-frequency clock signal for the RFSoC chip.

[0068] In this way, by combining the clock synthesizer with the broadband RF synthesizer, the generated initial clock signal can be converted into a high-frequency clock signal according to the actual clock frequency requirement.

[0069] Based on this, in some embodiments, such as Figure 5 As shown, the RFSoC chip 163 may include an analog-to-digital converter ADC 1631, a field programmable gate array FPGA unit 1632, and an ARM processor 1633;

[0070] The analog-to-digital converter ADC1631 is electrically connected to the field programmable gate array FPGA unit 1632, and the ARM processor 1633 is electrically connected to the FPGA unit 1632;

[0071] ADC1631 is used to collect the two differential signals after gain amplification in the signal input module according to the preset sampling rate, and convert the differential signals into two level signals;

[0072] The FPGA unit 1632 is used to perform noise reduction on the two-way level signals to obtain the two-way level signals after noise reduction when receiving the control instruction sent by the ARM processor 1633.

[0073] In some embodiments, ADC1631 includes a sampling rate set by a host computer. ARM processor 1633 sends a control instruction to FPGA unit 1632, and FPGA unit 1632 includes a group recursive cumulative average subunit, which uses an internally written group recursive cumulative average algorithm to achieve noise reduction of two-way level signals. Here, ADC is an analog to digital converter (Analog to Digital Converter).

[0074] In some embodiments, the total number of group recursive cumulative averages is set to n according to the noise reduction performance requirements (this can be set in advance and can be obtained through the host computer, ensuring adaptability to different engineering application backgrounds and improving the spatial resolution and flexibility of the system). ADC1633 inputs two-way level signals into the group recursive cumulative average subunit, and divides the total number of cumulative averages n into m groups. The amount of data in each group is set to p, that is, n divided by m, and a recursive deep pipeline accumulator tree is used for cumulative calculation. In order to reduce the computational complexity and the use of logical resources, n and m are set to integer powers of 2, and then arithmetic right shift operations are used instead of division operations to complete the average operation after linear accumulation. The results after each group of linear cumulative averages are recursively accumulated and averaged, and each result is corrected according to the last average result. The specific operation process includes:

[0075] Divide n single-ended level signals into m groups, each group has p level signals, and use formula (1) to perform linear cumulative average calculation on each group of level signals. Formula (1) is as follows:

[0076]

[0077] The recursive calculation using formula (2) is a cumulative average operation, and the correction is made according to the last average result. Formula (2) is as follows:

[0078]

[0079] in, is the single-ended level signal after noise reduction. The calculation method of the other end level signal is the same.

[0080] In some embodiments, all single-ended level signals that need to be accumulated and averaged are grouped, and after grouping, each group uses a deep pipeline accumulator tree to perform a standard linear accumulation operation, and then a recursive accumulation and averaging operation is performed on the operation results of each group, and finally a noise-reduced single-ended level signal with a high signal-to-noise ratio is obtained. Signal noise reduction is achieved through group recursive accumulation and averaging, which effectively improves the signal-to-noise ratio of the output signal.

[0081] In some embodiments, the output clock of the ADC in the RFSoC chip is converted into a clock domain clock through the MMCM. In addition, the PS end can also provide a clock to the PL end. Here, the PS end is the processing system, which is the part that has nothing to do with the FPGA. The PL end is the programmable logic, which is the FPGA part.

[0082] In this way, the RFSoC chip is used to integrate ADC, FPGA unit and ARM processor, and the functions of ADC, FPGA and ARM processor are integrated into the same component, which reduces the occupied space of the distributed temperature measurement system, simplifies the complex design and improves the stability of the system.

[0083] Based on this, in some embodiments, such as Figure 6 As shown, the RFSoC data acquisition module 160 may also include a data storage submodule 164;

[0084] The data storage submodule 164 is connected to the RFSoC chip 163 via an advanced extensible interface AXI4 bus, and is used to obtain and store two level signals in the RFSoC chip.

[0085] In some embodiments, the advanced extensible interface AXI4 bus adopts a READY, VALID handshake communication mechanism. Simply put, there is a handshake process before the master and slave parties communicate data. The VLAID signal generated by the transmission source indicates when the data or control information is valid, which is mainly aimed at the needs of address mapping communication.

[0086] In this way, a data storage submodule is provided in the RFSoC data acquisition module, thereby expanding the storage space of the RFSoC data acquisition module.

[0087] Based on this, in some embodiments, such as Figure 7 As shown, the data storage submodule 164 may include a DDR4 memory 1641 for storing two-way level signals in the RFSoC chip.

[0088] In some embodiments, the address mapping of DDR4 memory is defined by modifying the link script file to the starting address and storage space of two-way level signals. The data interface and command interface from low frequency to high frequency are cached by the data cache FIFO, and then the two-way level signals are stored in the defined DDR4 addresses respectively. Here, DDR4 is DDR4 SDRAM (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory), which is a high-bandwidth computer memory specification. FIFO (First Input First Output) simply means first in, first out.

[0089] In this way, the storage of a large number of level signals is achieved using DDR4.

[0090] Based on this, in some embodiments, such as Figure 8 As shown, the RFSoC data acquisition module 160 may also include a data transmission submodule 165;

[0091] The data transmission submodule 165 includes an Ethernet cable 1651 for transmitting two-way level signals after noise reduction.

[0092] In some embodiments, the noise reduction processed data is transmitted to the host computer via the Ethernet cable 1651.

[0093] In some embodiments, the group recursive cumulative average results are cached, and then the data is transmitted to a host computer through the high-speed Ethernet port of the RFSoC for subsequent data processing or data analysis operations.

[0094] In some embodiments, Fig. 9As shown in the figure, the ADC of the RFSoC chip collects two differential level signals, performs threshold detection, delay compensation, mixing and extraction data preprocessing, adjusts the signal chain gain, keeps the differential signal within the ideal voltage range, and compensates for the delay in the digital data path, and converts it into two level signals. The Data FIFO part is used to buffer the collected two-way level signals. The Direct Memory Access (DMA) bus is used to store the collected two-way level signals to the absolute address preset by the DDR4 on the PL side. The designed group recursive accumulation average subunit improves the operation efficiency through pipeline design and recursive accumulation algorithm, and the sampling arithmetic right shift replaces the divider to quickly perform average calculation and reduce the use of logic resources. The Ethernet cable is used to transmit the signal noise reduction processing results to the host computer.

[0095] In some embodiments, the two-way level signal is passed through the FGPA unit to realize the onboard hard trigger alignment and average noise reduction filtering function. The RFSoC chip realizes data processing, high-speed data signal sampling, data alignment and filtering noise reduction based on the recursive cumulative average algorithm for the two-way level signal through the repackaging of the two-way level signal, sampling rate reduction, input signal alignment and cumulative average filtering noise reduction process, and finally transmits the data through the asynchronous FIFO and DMA IP core and stores it through DDR4. The data in DDR4 uses serial port or Ethernet communication to transmit the collected data to the host computer to realize the demodulation of temperature information.

[0096] In some embodiments, the ADC selects internal trigger or external trigger mode for data acquisition, uses the ARMProcessor on the PS side to send control instructions, determines the data acquisition depth based on the cumulative average times and signal characteristics, and synchronously acquires the input signals of the dual channels. After each acquisition command is received, the control instruction is used to reset the FIFO and DMA before the DMA is initialized to ensure that invalid data is not collected. After the last data acquisition is completed, the FIFO and DMA are placed in a reset state.

[0097] In this way, the noise-reduced level signal is transmitted to the host computer by setting up an Ethernet cable.

[0098] Based on this, in some embodiments, the RFSoC data acquisition module is connected to the pulse laser light source module via a second RF connection line, and the RFSoC data acquisition module can also be used for:

[0099] The driving level signal is used to drive the pulse laser light source module to generate a temperature measurement pulse signal.

[0100] In some embodiments, the RFSoC data acquisition module generates a driving signal according to the control information, and outputs a level signal that meets the set signal amplitude, frequency and pulse width to the pulse laser light source module through a second RF connection line.

[0101] In this way, the set RFSoC data acquisition module can also drive the pulse laser light source module to generate pulse light.

[0102] Based on this, in some embodiments, the RFSoC chip includes a digital-to-analog converter DAC, which can be used to obtain control information in a host computer, generate a drive signal according to the control information, and convert the drive signal into a drive level signal.

[0103] In some embodiments, the RFSoC data acquisition module is electrically connected to the host computer. The RFSoC data acquisition module receives control information from the host computer, generates a dual-channel LVPECL differential drive signal, completes voltage conversion through the DAC, and obtains a drive signal by adjusting the value of each point. Through the second RF connection line, the level signal that meets the set signal amplitude, frequency and pulse width is output to the pulse laser light source module. Here, LVPECL (Low Voltage Positive Emitter-Coupled Logic) is a common high-speed digital circuit signal transmission standard. Here, DAC is an analog-to-digital converter (Digital to Analog Converter).

[0104] In this way, the digital information is converted into an analog signal through a digital-to-analog converter, and the generated analog signal drives the pulse laser light source module to generate pulse light.

[0105] The distributed temperature measurement system provided in the embodiment of the present application realizes high-speed acquisition and on-chip processing of large amounts of data through the high sampling rate of the RFSoC chip and the FPGA logic resources, thereby achieving system integration and performance improvement. It can be used for long-distance high-precision temperature information acquisition and real-time temperature status monitoring, and realizes applications such as fire monitoring scenarios for pipelines, buildings, battery packs, and thermal management system monitoring requirements.

[0106] The distributed temperature measurement system provided in the embodiment of the present application is constructed through the top-level architecture of the configurable IP (Intellectual Property) core of the RFSoC data acquisition module. The parameters of the high-speed signal acquisition system can be quickly changed according to the project requirements of the distributed measurement system. It has good resolution, high integration and strong flexibility.

[0107] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0108] The above are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A distributed temperature measurement system, characterized in that: The temperature measurement system includes a host computer, a pulse laser light source module, a wavelength division multiplexing module, a temperature measurement optical fiber, a photoelectric detection module and a radio frequency system-on-chip RFSoC data acquisition module; The pulse laser light source module is used to generate a temperature measurement pulse signal; The wavelength division multiplexing module is electrically connected to the pulse laser light source module, the wavelength division multiplexing module is connected to the temperature measurement optical fiber, the temperature measurement optical fiber is used to transmit the temperature measurement pulse signal, the wavelength division multiplexing module is used to collect the temperature measurement pulse signal in the temperature measurement optical fiber, and demultiplex the temperature measurement pulse signal to obtain two backscattering signals; The photoelectric detection module is electrically connected to the wavelength division multiplexing module, and is used to convert the two backscattered signals into two level signals; The RFSoC data acquisition module is connected to the photoelectric detection module through a first radio frequency connection line, and is used to collect the two-way level signals according to a preset sampling rate, and reduce the noise of the two-way level signals; The host computer is electrically connected to the RFSoC data acquisition module and is used to determine temperature information based on the two-way level signals after noise reduction.

2. The distributed temperature measurement system according to claim 1, characterized in that: The RFSoC data acquisition module includes a signal input submodule, a clock submodule and an RFSoC chip; The signal input submodule is electrically connected to the RFSoC chip, and the signal input submodule is used to obtain the two-way level signals in the photoelectric detection module through the first RF connection line, and convert the two-way level signals after gain amplification into two-way differential signals, and the RFSoC chip is used to collect the two-way differential signals after gain amplification in the signal input submodule according to the preset sampling rate, and convert the differential signals into the two-way level signals, and reduce the noise of the two-way level signals; The clock submodule is electrically connected to the RFSoC chip and is used to generate a high-frequency clock signal provided to the RFSoC chip.

3. The distributed temperature measurement system according to claim 2, characterized in that: The signal input submodule includes an input signal source unit and a fully differential amplifier; The input signal source unit is electrically connected to the fully differential amplifier, and is used to obtain two level signals transmitted by the photoelectric detection module through the first RF connection line. The fully differential amplifier is used to achieve gain amplification of the two level signals and convert the two level signals after gain amplification into two differential signals.

4. The distributed temperature measurement system according to claim 2, characterized in that: The clock submodule includes a clock synthesizer and a broadband radio frequency synthesizer; The clock synthesizer is electrically connected to the broadband RF synthesizer, and the clock synthesizer is used to generate an initial clock signal according to the configuration information in the RFSoC chip, and the broadband RF synthesizer is used to amplify the clock frequency and convert the initial clock signal into a high-frequency clock signal.

5. The distributed temperature measurement system according to claim 2, characterized in that: The RFSoC chip includes an analog-to-digital converter ADC, a field programmable gate array FPGA unit and an ARM processor; The analog-to-digital converter ADC is electrically connected to a field programmable gate array FPGA unit, and the ARM processor is electrically connected to the FPGA unit; The ADC is used to collect the two differential signals after gain amplification in the signal input submodule according to the preset sampling rate, and convert the differential signals into the two level signals; The FPGA unit is used to perform noise reduction on the two-channel level signals to obtain the two-channel level signals after noise reduction when receiving the control instruction sent by the ARM processor.

6. The distributed temperature measurement system according to claim 2, characterized in that: The RFSoC data acquisition module also includes a data storage submodule; The data storage submodule is connected to the RFSoC chip via an advanced extensible interface AXI4 bus, and is used to obtain and store two level signals in the RFSoC chip.

7. The distributed temperature measurement system according to claim 6, characterized in that: The data storage submodule includes a DDR4 memory for storing two level signals in the RFSoC chip.

8. The distributed temperature measurement system according to claim 2, characterized in that: The RFSoC data acquisition module also includes a data transmission submodule; The data transmission submodule includes an Ethernet cable for transmitting the two-way level signals after noise reduction.

9. The distributed temperature measurement system according to claim 1, characterized in that: The RFSoC data acquisition module is connected to the pulse laser light source module via a second RF connection line, and the RFSoC data acquisition module is also used for: The pulse laser light source module is driven by a driving level signal to generate a temperature measurement pulse signal.

10. The distributed temperature measurement system according to claim 2, characterized in that: The RFSoC chip includes a digital-to-analog converter DAC, which is used to obtain control information in a host computer, generate a drive signal according to the control information, and convert the drive signal into a drive level signal.

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