Chip packaging structure
By setting the mounting surfaces of the semiconductor components of the upper and lower substrates in the chip packaging structure and using socket connections, the problems of complex wire drawing and excessive plastic sealing materials are solved, the heat dissipation performance and process simplification of the chip are improved, and the production cost is reduced .
Patent Information
- Application Number
- CN202420994867.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-05-09
AI Technical Summary
The existing chip packaging structure is complicated to wire and too much plastic sealing material, resulting in poor heat dissipation effect.
By setting the mounting surfaces of the semiconductor components of the upper and lower substrates relative to each other and using socket connections, the use of plastic sealing materials and glue is cancelled, and the process flow is simplified directly through socket support and electrical connections.
It greatly reduces the use of plastic sealing materials, improves the heat dissipation performance of the chip, simplifies the process flow, and reduces production costs.
Smart Images
Figure CN222320275U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, and more specifically, to a chip packaging structure. Background Art
[0002] Chip packaging is mainly completed in the back-end process of semiconductor manufacturing, that is, using membrane technology and micro-connection technology to arrange, fix and connect semiconductor components and other components on a frame or substrate, lead out wiring terminals, and fix them through plastic insulating medium encapsulation to form the overall main structure. The most basic function of chip packaging is to protect circuit chips from the influence of the surrounding environment (including physical and chemical influences).
[0003] like Figure 1 As shown in the figure, an existing chip packaging structure includes an upper substrate, a lower substrate, and semiconductor components arranged on the upper substrate and the lower substrate. The packaging steps are as follows: 1. Install the semiconductor components on the upper substrate; 2. Install the semiconductor components on the lower substrate; 3. Plastic seal the lower substrate with the semiconductor components installed; 4. Fix the upper substrate to the plastic seal body of the lower substrate; 5. Bond wires from the upper substrate to the lower substrate; 6. After bonding, plastic seal everything. Figure 1 In such a structure, the connection between the upper and lower substrates is long, the arc is high, and the wiring is complex.
[0004] During the chip manufacturing process, the problem of chip heat dissipation must also be considered. Using the structure described above, the lower substrate and the semiconductor components mounted thereon must first be plastic-encapsulated, the upper substrate and the lower substrate must be fixed, and after wire bonding, the entire structure must be plastic-encapsulated again. For such a chip, there are too many plastic encapsulation bodies and the thickness of the plastic encapsulation is too thick, which is not conducive to the heat dissipation of the chip. Utility Model Content
[0005] The utility model aims to solve the technical problems of the prior art chip packaging structure in that the wiring is complicated, the plastic packaging material is too much and too thick to be conducive to heat dissipation, and provides a chip packaging structure with simple structure and good heat dissipation effect.
[0006] The above-mentioned purpose of the utility model is achieved through the following technical solutions:
[0007] A chip packaging structure comprises an upper substrate, a lower substrate and semiconductor components mounted on the upper substrate and the lower substrate; the semiconductor component mounting surfaces of the upper substrate and the lower substrate are arranged relative to each other, so that the semiconductor components mounted on the upper substrate and the semiconductor components mounted on the lower substrate are both located between the upper substrate and the lower substrate, the lower substrate mounted with the semiconductor components as a whole does not contain plastic packaging material and glue, the upper substrate and the lower substrate are connected by a socket, and the upper substrate mounted with the semiconductor components and the lower substrate mounted with the semiconductor components as a whole are not connected to form a whole by plastic packaging material and glue.
[0008] The utility model reverses the upper substrate on the basis of the prior art, so that the semiconductor components installed on the upper and lower substrates are located between the upper and lower substrates, and the upper and lower substrates are connected by sockets. Since the upper and lower substrates are connected by sockets, it is not necessary to plastic-encapsulate the lower substrate, nor is it necessary to plastic-encapsulate the upper and lower substrates as a whole again. Compared with the prior art described in the background technology, the utility model does not have steps 3, 4, 5, and 6, which greatly simplifies the process. And since there is no plastic encapsulation, the heat dissipation performance of the chip is greatly improved.
[0009] In the prior art, the plastic packaging material of the lower substrate plays the role of supporting and fixing the upper substrate. The socket of the utility model not only plays the role of support, but also plays the role of electrical connection. Therefore, there is no need to wire between the components of the upper and lower substrates (that is, there is no step 5).
[0010] In summary, the utility model solves the technical problems of the prior art such as too much plastic packaging material, poor heat dissipation effect and complicated wiring.
[0011] The lower substrate on which semiconductor components are mounted does not contain any plastic encapsulation material or glue as a whole, which means that the lower substrate on which semiconductor components are mounted is not solidified into a whole by filling plastic encapsulation material or glue with the lower substrate and the semiconductor components thereon (i.e., there is no operation in step 3 of the prior art to fill the lower substrate and the components thereon with plastic encapsulation material).
[0012] The upper substrate on which semiconductor components are mounted and the lower substrate on which semiconductor components are mounted are not connected as a whole by plastic encapsulation material and glue, which means that the upper substrate on which semiconductor components are mounted and the lower substrate on which semiconductor components are mounted are not solidified as a whole by filling plastic encapsulation material and glue to form the upper substrate, the semiconductor components on the upper substrate, the lower substrate, and the semiconductor components on the lower substrate (i.e., there is no operation in step 6 of the prior art to fill the above four with plastic encapsulation material).
[0013] The semiconductor components include a plastic package and components.
[0014] Furthermore, the upper substrate and the lower substrate are connected via a socket, and the socket is installed between the upper substrate and the lower substrate.
[0015] Socket is a common name used by technicians in this field, which means a socket, base or card holder. It is used as the base for product open circuit, short circuit, and test products, and plays the role of connecting the test baseboard.
[0016] Furthermore, in order to prevent the semiconductor components on the upper substrate from being too close to the semiconductor components on the lower substrate, the thickness of the socket is 100-300 μm higher than the height of the thickest component or package on the upper substrate and the lower substrate.
[0017] Furthermore, the socket includes a socket and a connector, and the socket and the connector are respectively fixed to the upper substrate or the lower substrate; the number of sockets is two pairs, and the height of the socket and the height of the connector may be inconsistent. The thickness of the socket and the connector is determined according to the thickness of the semiconductor components of the upper substrate and the lower substrate.
[0018] Furthermore, the lower substrate and the upper substrate have the same size.
[0019] Furthermore, the upper substrate and the lower substrate are both ceramic substrates.
[0020] The utility model further improves the material of the substrate. The upper and lower substrates are both made of ceramic substrates. The ceramic substrate itself has a high heat dissipation coefficient and can also directly dissipate heat through the back of the ceramic substrate.
[0021] Compared with the prior art, the utility model has the following beneficial effects:
[0022] The chip packaging structure described in the utility model, based on the existing technology, turns the upper substrate upside down so that the semiconductor components installed on the upper and lower substrates are located between the upper and lower substrates, and the upper substrate and the lower substrate are directly connected through the socket. The upper and lower substrates are supported and electrically connected through the socket, so the upper and lower substrates do not need to be filled with plastic packaging materials, which greatly reduces the amount of plastic packaging materials used and is beneficial to the heat dissipation of the chip. In addition, the upper and lower substrates are electrically connected through the socket, and no wiring is required. The utility model solves the technical problems of the chip packaging structure in the existing technology that the wiring is complicated, the plastic packaging materials are too much, and the plastic packaging is too thick, which is not conducive to heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The drawings constituting part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:
[0024] Figure 1 The present invention is a schematic diagram of a chip packaging structure in the prior art.
[0025] Figure 2 The utility model is a schematic diagram of a chip packaging structure.
[0026] 1-upper substrate, 2-lower substrate, 3-wire, 4-socket, 5-filling area 1, 6-filling area 2. DETAILED DESCRIPTION
[0027] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different ways as defined and covered by the claims. Example
[0028] From the analysis of background technology, it can be seen that Figure 1 In the position shown, the upper substrate 1 and the lower substrate 2 are arranged from top to bottom, and semiconductor components are installed on the upper substrate 1 and the lower substrate 2 respectively. The semiconductor components of the upper substrate 1 are installed on the upper substrate 1, and the semiconductor components of the lower substrate 2 are installed on the lower substrate 2. There needs to be a certain gap between the upper and lower substrates to ensure the performance of the chip. Figure 1 In the structure shown, the wire 3 is led from the upper substrate 1 to the lower substrate 2, there are many components, the wiring is complicated, the wire is led from top to bottom, the wire is long, the wire arc is high, and the cost is high. Figure 1 The filling area 1 5 (i.e., the plastic encapsulation material is filled in step 3 in the background technology), Figure 1 The upper and lower substrates are supported by plastic packaging materials. Figure 1 In the filling area 26 shown, after fixing the upper substrate and the plastic encapsulation material and bonding the upper substrate to the lower substrate, the entire plastic encapsulation is performed. In this way, too much plastic encapsulation material is too thick, which is not conducive to heat dissipation. After the chip is manufactured, the heat dissipation performance of the chip must be considered. Good heat dissipation performance is the guarantee for the normal operation of the chip.
[0029] In order to solve this technical problem, the present application provides a chip packaging structure, such as Figure 2 As shown, the upper substrate 1 is turned upside down so that the semiconductor component mounting surfaces of the upper substrate 1 and the lower substrate 2 are arranged opposite to each other, so that the semiconductor components mounted on the upper substrate 1 and the semiconductor components mounted on the lower substrate 2 are both located between the upper substrate 1 and the lower substrate 2, and the upper substrate 1 and the lower substrate 2 are directly connected via the socket 4, and there is no need to first plastic-encapsulate the lower substrate 1 with the semiconductor components mounted thereon, nor is there any need to plastic-encapsulate the lower substrate 2 with the semiconductor components mounted thereon and the upper substrate 1 with the semiconductor components mounted thereon as a whole, which greatly simplifies the process and reduces the amount of plastic encapsulation material, greatly improving the heat dissipation performance of the chip. The upper substrate 1 and the lower substrate 2 are connected via the socket 4, and there is no need for wire bonding, which solves the technical problem of complex wire bonding in the prior art, simplifies the process, and reduces production costs. Comparison Figure 1 and Figure 2 It can be seen that Figure 2 The upper and lower substrates are directly connected through sockets, without complicated wire bonding, and without plastic sealing area 1 5 and plastic sealing area 2 6, so the structure is simple.
[0030] The lower substrate 2 and the upper substrate 1 have the same size, and the socket 4 is installed between the upper substrate 1 and the lower substrate 2 .
[0031] The utility model further improves the material of the substrate. The upper and lower substrates are both made of ceramic substrates. The ceramic substrate itself has a high heat dissipation coefficient and can also directly dissipate heat through the back of the ceramic substrate.
[0032] To prevent the semiconductor components on the upper substrate 1 and the semiconductor components on the lower substrate 2 from being too close, the thickness of the socket 4 is 100-300 μm higher than the height of the thickest component or package on the upper substrate 1 and the lower substrate 2 .
[0033] The socket 4 includes a socket and a connector, which are respectively fixed to the upper substrate 1 or the lower substrate 2; there are two pairs of sockets 4, and the height of the sockets and the height of the connectors may be inconsistent. The thickness of the sockets and the connectors is determined according to the thickness of the components of the upper substrate 1 and the lower substrate 2.
[0034] A chip packaging structure described in the present application has components on an upper substrate 1 and a lower substrate 2 arranged relatively to each other, and the upper and lower substrates are directly connected via sockets, thereby solving the technical problems of the prior art such as complex wiring, too much plastic packaging material, and too thick plastic packaging that is not conducive to heat dissipation, and the structure and process are simple.
[0035] The above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. For those skilled in the art, the utility model may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the scope of the utility model.
Claims
1. A chip packaging structure, comprising an upper substrate, a lower substrate and semiconductor components mounted on the upper substrate and the lower substrate; characterized in that: The semiconductor component mounting surfaces of the upper substrate and the lower substrate are arranged relative to each other, so that the semiconductor components mounted on the upper substrate and the semiconductor components mounted on the lower substrate are both located between the upper substrate and the lower substrate, and the lower substrate on which the semiconductor components are mounted does not contain any plastic packaging material or glue as a whole. The upper substrate and the lower substrate are connected via a socket, and the upper substrate on which the semiconductor components are mounted and the lower substrate on which the semiconductor components are mounted are not connected as a whole via any plastic packaging material or glue as a whole.
2. The chip packaging structure according to claim 1, characterized in that: The socket is installed between the upper substrate and the lower substrate.
3. The chip packaging structure according to claim 2, characterized in that: The socket thickness is 100-300 μm higher than the thickest component or package height on the upper substrate and the lower substrate.
4. The chip packaging structure according to claim 2, characterized in that: The socket comprises a socket and a connector, and the socket and the connector are respectively fixed to the upper substrate or the lower substrate; the number of the socket is two pairs, and the height of the socket and the height of the connector may be inconsistent.
5. The chip packaging structure according to claim 2, characterized in that: The lower substrate and the upper substrate have the same size.
6. The chip packaging structure according to claim 5, characterized in that: The socket is located on both sides of the upper substrate and the lower substrate.
7. The chip packaging structure according to claim 1, characterized in that: The upper substrate and the lower substrate are both ceramic substrates.