Circuit for redundantly identifying wheel speed signal

Abstract

The utility model discloses a circuit for redundantly identifying wheel speed signals. The device comprises a wheel speed signal switching module and a wheel speed signal decoding module. The wheel speed signal switching module comprises four wheel speed signal sub-modules, and each wheel speed signal sub-module is composed of two composite triodes; the wheel speed signal decoding module comprises two decoding chips, and each decoding chip is respectively connected with four wheel speed signal sub-modules; an independent driving switch signal in the wheel speed signal switching module controls power supply of a wheel speed sensor; in the wheel speed signal decoding module, two different decoding modules are used for analyzing wheel speed signals. According to the utility model, through the wheel speed signal switching module, signal identification of the redundant decoding chip on the same wheel speed circuit is isolated, and mutual interference between driving signals of the master control wheel speed decoding chip and the backup wheel speed decoding chip is prevented. By means of the circuit design, the function safety level in vehicle use is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of automobile electronic circuits, in particular to a circuit for redundantly identifying wheel speed signals. Background Art

[0002] Wheel speed sensor is a sensor used to measure the rotation speed of the car wheels. The electronic stability program (ESP), anti-lock braking system (ABS), electronic parking system (EPB) and other systems all require wheel speed information, so the wheel speed sensor is one of the most critical sensors in modern cars.

[0003] In the design, four wheel speed sensors are usually mounted on a decoding chip to convert the sensor speed. In the face of the increasingly high functional safety requirements of vehicles, this processing method obviously has a single point failure problem in which the vehicle speed conversion cannot be performed after the decoding chip fails. Utility Model Content

[0004] In order to solve the problems existing in the background technology, the utility model provides a circuit for redundantly identifying wheel speed signals.

[0005] The technical solution of the utility model is achieved in this way:

[0006] The utility model comprises two parts, namely a wheel speed signal switching module and a wheel speed signal decoding module; the wheel speed signal switching module comprises four wheel speed signal submodules, each of which is composed of two composite triodes; the wheel speed signal decoding module comprises two decoding chips, each of which is respectively connected to the four wheel speed signal submodules.

[0007] The wheel speed signal decoding module includes a decoding chip M1 and a decoding chip M2.

[0008] The decoding chip M1 has pins P_RR1, P_FR1, P_RL1 and P_FL1 as the sensor power supply port, and also has pins M1_DRV_SUP_RR, M1_DRV_SUP_FR, M1_DRV_SUP_RL and M1_DRV_SUP_FL as the power supply drive port; its pins P_RR1, P_FR1, P_RL1 and P_FL1 are connected to interfaces M_RR, M_FR, M_RL and M_FL through resistors R1, R2, R3 and R4 respectively, and are grounded through capacitors C1, C2, C3 and C4 respectively; interfaces M_RR, M_FR, M_RL and M_FL are connected to four wheel speed signal submodules of the wheel speed signal switching module respectively;

[0009] The decoding chip M2 has pins P_RR2, P_FR2, P_RL2, and P_FL2 as sensor power supply ports, and also has pins M2_DRV_SUP_RR, M2_DRV_SUP_FR, M2_DRV_SUP_RL, and M2_DRV_SUP_FL as power supply drive ports; its pins P_RR2, P_FR2, P_RL2, and P_FL2 are connected to interfaces M_RR, M_FR, M_RL, and M_FL via resistors R5, R6, R7, and R8, respectively, and are grounded via capacitors C5, C6, C7, and C8, respectively.

[0010] The decoding chip M1 is used as the main decoding chip, and the decoding chip M2 is used as the backup decoding chip.

[0011] The wheel speed signal switching module includes a first wheel speed signal submodule, a second wheel speed signal submodule, a third wheel speed signal submodule and a fourth wheel speed signal submodule:

[0012] The first wheel speed signal submodule includes a composite transistor Q1 and a composite transistor Q2, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the composite transistor Q1 and the composite transistor Q2 are both composed of two transistors connected; in the composite transistor Q1, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_RR of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_RR, and the emitter of the second transistor is connected to the right rear power supply WSP_RR of the wheel speed sensor; in the composite transistor Q2, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_RR of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_RR, and the emitter of the second transistor is connected to the right rear power supply WSP_RR of the wheel speed sensor.

[0013] The second wheel speed signal submodule includes a compound transistor Q3 and a compound transistor Q4, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the compound transistor Q3 and the compound transistor Q4 are both composed of two transistors connected; in the compound transistor Q3, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_FR of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_FR, and the emitter of the second transistor is connected to the right rear power supply WSP_FR of the wheel speed sensor; in the compound transistor Q4, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_FR of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_FR, and the emitter of the second transistor is connected to the right rear power supply WSP_FR of the wheel speed sensor.

[0014] The third wheel speed signal submodule includes a composite transistor Q5 and a composite transistor Q6, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the composite transistor Q5 and the composite transistor Q6 are both composed of two transistors connected; in the composite transistor Q5, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_RL of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_RL, and the emitter of the second transistor is connected to the right rear power supply WSP_RL of the wheel speed sensor; in the composite transistor Q6, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_RL of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_RL, and the emitter of the second transistor is connected to the right rear power supply WSP_RL of the wheel speed sensor.

[0015] The fourth wheel speed signal submodule includes a composite transistor Q7 and a composite transistor Q8, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the composite transistor Q7 and the composite transistor Q8 are both composed of two transistors connected; in the composite transistor Q7, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_FL of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_FL, and the emitter of the second transistor is connected to the right rear power supply WSP_FL of the wheel speed sensor; in the composite transistor Q8, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_FL of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_FL, and the emitter of the second transistor is connected to the right rear power supply WSP_FL of the wheel speed sensor.

[0016] The decoding chip M1 and the decoding chip M2 are both connected to the wheel speed sensor.

[0017] Beneficial effects of the utility model:

[0018] The utility model isolates the signal recognition of the same wheel speed circuit by the redundant decoding chip through the wheel speed signal switching module, thereby preventing the mutual interference between the driving signals of the main wheel speed decoding chip and the backup wheel speed decoding chip. This circuit design improves the functional safety level of vehicle use. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The schematic diagram of a circuit for redundantly identifying wheel speed signals is shown in FIG. DETAILED DESCRIPTION

[0020] The utility model is further described below in conjunction with the accompanying drawings and embodiments.

[0021] like Figure 1 As shown, the circuit includes two parts: a wheel speed signal switching module 1 and a wheel speed signal decoding module 2; the wheel speed signal switching module 1 includes four wheel speed signal sub-modules, each of which is composed of two composite triodes; the wheel speed signal decoding module 2 includes two decoding chips, each of which is connected to the four wheel speed signal sub-modules.

[0022] The independent driving switch signal in the wheel speed signal switching module 1 controls the power supply of the wheel speed sensor. In the wheel speed signal decoding module 2, two different decoding modules are used to analyze the wheel speed signal.

[0023] The wheel speed signal decoding module 2 includes a decoding chip M1 and a decoding chip M2.

[0024] The decoding chip M1 has pin 1 P_RR1, pin 3 P_FR1, pin 5 P_RL1, pin 7 P_FL1 as the sensor power supply port, and also has pin 9 M1_DRV_SUP_RR, pin 10 M1_DRV_SUP_FR, pin 11 M1_DRV_SUP_RL and pin 12 M1_DRV_SUP_FL as the power supply drive port. Pins 2, 4, 6 and 8 are all grounded; pin 1 is connected to the ground. Pin P_RR1, pin 3 P_FR1, pin 5 P_RL1, pin 7 P_FL1 are connected to interface M_RR, interface M_FR, interface M_RL, interface M_FL through resistor R1, resistor R2, resistor R3, resistor R4 respectively, and are grounded through capacitor C1, capacitor C2, capacitor C3, capacitor C4 respectively; interface M_RR, interface M_FR, interface M_RL, interface M_FL are connected to four wheel speed signal submodules of wheel speed signal switching module 1 respectively;

[0025] The decoding chip M2 has pin 1 P_RR2, pin 3 P_FR2, pin 5 P_RL2, pin 7 P_FL2 as the sensor power supply port, and also has pin 9 M2_DRV_SUP_RR, pin 10 M2_DRV_SUP_FR, pin 11 M2_DRV_SUP_RL and pin 12 M2_DRV_SUP_FL as the power supply drive port. Pins 2, 4, 6 and 8 are all grounded; pin 1 is connected to the ground. Pin P_RR2, pin No. 3 P_FR2, pin No. 5 P_RL2, pin No. 7 P_FL2 are connected to interface M_RR, interface M_FR, interface M_RL, interface M_FL via resistor R5, resistor R6, resistor R7, resistor R8 respectively, and are grounded via capacitor C5, capacitor C6, capacitor C7, capacitor C8 respectively; interface M_RR, interface M_FR, interface M_RL, interface M_FL are connected to four wheel speed signal sub-modules of wheel speed signal switching module 1 respectively.

[0026] The decoding chip M1 is used as the main decoding chip, and the decoding chip M2 is used as the backup decoding chip.

[0027] In a specific implementation, the function of the wheel speed signal switching module 1 is that when the main decoding module operates normally, its driving signal output is high, and the four wheel speed signal power supply lines are transferred to the main decoding chip through the wheel speed signal switching module 1 for identification. The backup decoding chip output is low, and the four wheel speed signal power supply lines are disconnected through the wheel speed signal switching module 1, so as not to interfere with the signal identification of the main decoding chip. When an abnormality is detected in the main decoding chip, the main decoding module driving signal output is low, and the four wheel speed signal power supply lines are disconnected through the wheel speed signal switching module. The backup decoding chip output is high, and the four wheel speed signal power supply lines are transferred to the main decoding chip through the wheel speed signal switching module for identification.

[0028] The wheel speed signal switching module 1 includes a first wheel speed signal submodule, a second wheel speed signal submodule, a third wheel speed signal submodule and a fourth wheel speed signal submodule:

[0029] The first wheel speed signal submodule includes a compound transistor Q1 and a compound transistor Q2, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the compound transistor Q1 and the compound transistor Q2 are both composed of two transistors connected in reverse; in the compound transistor Q1, the emitter of the first transistor is grounded, the base is connected to the No. 9 pin M1_DRV_SUP_RR of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_RR, and the emitter of the second transistor is connected to the right rear power supply WSP_RR of the wheel speed sensor; in the compound transistor Q2, the emitter of the first transistor is grounded, the base is connected to the No. 9 pin M2_DRV_SUP_RR of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_RR, and the emitter of the second transistor is connected to the right rear power supply WSP_RR of the wheel speed sensor;

[0030] The second wheel speed signal submodule includes a compound transistor Q3 and a compound transistor Q4, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the compound transistor Q3 and the compound transistor Q4 are both composed of two transistors connected in reverse; in the compound transistor Q3, the emitter of the first transistor is grounded, the base is connected to the No. 10 pin M1_DRV_SUP_FR of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_FR, and the emitter of the second transistor is connected to the right rear power supply WSP_FR of the wheel speed sensor; in the compound transistor Q4, the emitter of the first transistor is grounded, the base is connected to the No. 10 pin M2_DRV_SUP_FR of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_FR, and the emitter of the second transistor is connected to the right rear power supply WSP_FR of the wheel speed sensor;

[0031] The third wheel speed signal submodule includes a compound transistor Q5 and a compound transistor Q6, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the compound transistor Q5 and the compound transistor Q6 are both composed of two transistors connected in reverse; in the compound transistor Q5, the emitter of the first transistor is grounded, the base is connected to the No. 11 pin M1_DRV_SUP_RL of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_RL, and the emitter of the second transistor is connected to the right rear power supply WSP_RL of the wheel speed sensor; in the compound transistor Q6, the emitter of the first transistor is grounded, the base is connected to the No. 11 pin M2_DRV_SUP_RL of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_RL, and the emitter of the second transistor is connected to the right rear power supply WSP_RL of the wheel speed sensor;

[0032] The fourth wheel speed signal submodule includes a compound transistor Q7 and a compound transistor Q8, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the compound transistor Q7 and the compound transistor Q8 are both composed of two transistors connected in reverse; in the compound transistor Q7, the emitter of the first transistor is grounded, the base is connected to the No. 11 pin M1_DRV_SUP_FL of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_FL, and the emitter of the second transistor is connected to the right rear power supply WSP_FL of the wheel speed sensor; in the compound transistor Q8, the emitter of the first transistor is grounded, the base is connected to the No. 11 pin M2_DRV_SUP_FL of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_FL, and the emitter of the second transistor is connected to the right rear power supply WSP_FL of the wheel speed sensor.

[0033] The decoding chip M1 and the decoding chip M2 are both connected to the wheel speed sensors.

[0034] In the wheel speed signal decoding module 2, the No. 2 ground pin of the decoding chip M1 is connected to the RR ground pin of the wheel speed sensor, the No. 4 ground pin is connected to the FR ground pin of the wheel speed sensor, the No. 6 ground pin is connected to the RL ground pin of the wheel speed sensor, and the No. 8 ground pin is connected to the FL ground pin of the wheel speed sensor. The No. 2 ground pin of the decoding chip M2 is connected to the RR ground pin of the wheel speed sensor, the No. 4 ground pin is connected to the FR ground pin of the wheel speed sensor, the No. 6 ground pin is connected to the RL ground pin of the wheel speed sensor, and the No. 8 ground pin is connected to the FL ground pin of the wheel speed sensor.

[0035] WSP_RR represents the right rear power supply of the wheel speed sensor, WSP_FR represents the right front power supply of the wheel speed sensor, WSP_RL represents the left rear power supply of the wheel speed sensor, and WSP_FL represents the left front power supply of the wheel speed sensor.

[0036] More specifically, the wheel speed sensor signal line RR at the right rear is connected to GND pin No. 2 of the decoding chip M1 and GND pin No. 2 of the decoding chip M2, the wheel speed sensor signal line FR at the right front is connected to GND pin No. 4 of the decoding chip M1 and GND pin No. 4 of the decoding chip M2, the wheel speed sensor signal line RL at the left rear is connected to GND pin No. 6 of the decoding chip M1 and GND pin No. 6 of the decoding chip M2, and the wheel speed sensor signal line FL at the left front is connected to GND pin No. 8 of the decoding chip M1 and GND pin No. 8 of the decoding chip M2.

[0037] In a specific implementation, the models of M1 and M2 are SC900950, the models of the composite triodes Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are PUMD16-Q, the resistance values ​​of the resistors R1, R2, R3, R4, R5, R6, R7, and R8 are 100Ω, and the capacitance values ​​of the capacitors C1, C2, C3, C4, C5, C6, C7, and C8 are 10nF.

[0038] The specific working mode of the utility model includes two modes: normal mode and failure mode;

[0039] Normal Mode:

[0040] The decoding chip M1 decodes the wheel speed signal. At this time, the No. 9 pin M1_DRV_SUP_RR, No. 10 pin M1_DRV_SUP_FR, No. 11 pin M1_DRV_SUP_RL, and No. 12 pin M1_DRV_SUP_FL of M1 all output high potential.

[0041] Pin No. 9 M2_DRV_SUP_RR, pin No. 10 M2_DRV_SUP_FR, pin No. 11 M2_DRV_SUP_RL, and pin No. 12 M2_DRV_SUP_FL of the decoding chip M2 all output low potential.

[0042] At this time, the composite transistor Q1 is turned on, and the power supply WSP_RR can be loaded onto the interface M_RR. The composite transistor Q2 is turned off, and the power supply WSP_RR cannot be loaded onto the interface S_RR.

[0043] The composite transistor Q3 is turned on, and the power supply WSP_FR can be loaded onto the interface M_FR. The composite transistor Q4 is turned off, and the power supply WSP_FR cannot be loaded onto the interface S_FR.

[0044] The composite transistor Q5 is turned on, and the power supply WSP_RL can be loaded onto the interface M_RL. The composite transistor Q6 is turned off, and the power supply WSP_RL cannot be loaded onto the interface S_RL.

[0045] The composite transistor Q7 is turned on, and the power supply WSP_FL can be loaded onto the interface M_FL. The composite transistor Q8 is turned off, and the power supply WSP_FL cannot be loaded onto the interface S_FL.

[0046] Through the above operation, the wheel speed sensor is connected to the decoding chip M1 and disconnected from the decoding chip M2.

[0047] The decoding chip M1 is used as the main decoding chip to identify the wheel speed of the wheel speed sensor.

[0048] Failure Mode:

[0049] The decoding chip M1 decodes the wheel speed signal. At this time, the No. 9 pin M1_DRV_SUP_RR, No. 10 pin M1_DRV_SUP_FR, No. 11 pin M1_DRV_SUP_RL, and No. 12 pin M1_DRV_SUP_FL of M1 all output low potential.

[0050] Pin No. 9 M2_DRV_SUP_RR, pin No. 10 M2_DRV_SUP_FR, pin No. 11 M2_DRV_SUP_RL, and pin No. 12 M2_DRV_SUP_FL of the decoding chip M2 all output high potential.

[0051] At this time, the composite transistor Q2 is turned on, and the power supply WSP_RR can be loaded onto the interface S_RR. The composite transistor Q1 is turned off, and the power supply WSP_RR cannot be loaded onto the interface M_RR.

[0052] The composite transistor Q4 is turned on, and the power supply WSP_FR can be loaded onto the interface S_FR. The composite transistor Q3 is turned off, and the power supply WSP_FR cannot be loaded onto the interface M_FR.

[0053] The composite transistor Q6 is turned on, and the power supply WSP_RL can be loaded onto the interface S_RL. The composite transistor Q5 is turned off, and the power supply WSP_RL cannot be loaded onto the interface M_RL.

[0054] The composite transistor Q8 is turned on, and the power supply WSP_FL can be loaded onto the interface S_FL. The composite transistor Q7 is turned off, and the power supply WSP_FL cannot be loaded onto the interface M_FL.

[0055] Through the above operation, the wheel speed sensor is connected to the decoding chip M2 and disconnected from the decoding chip M1.

[0056] When the decoding chip M1 as the main decoding chip is abnormal or fails, the decoding chip M1 is used as a backup decoding chip to identify the wheel speed of the wheel speed sensor.

Claims

1. A circuit for redundantly identifying wheel speed signals, characterized in that: The invention comprises two parts: a wheel speed signal switching module (1) and a wheel speed signal decoding module (2); the wheel speed signal switching module (1) comprises four wheel speed signal submodules, each wheel speed signal submodule is composed of two composite triodes; the wheel speed signal decoding module (2) comprises two decoding chips, each decoding chip is respectively connected to the four wheel speed signal submodules.

2. A circuit for redundantly identifying wheel speed signals according to claim 1, characterized in that: The wheel speed signal decoding module (2) comprises a decoding chip M1; the decoding chip M1 has pins P_RR1, P_FR1, P_RL1 and P_FL1 as sensor power supply ports, and also has pins M1_DRV_SUP_RR, M1_DRV_SUP_FR, M1_DRV_SUP_RL and M1_DRV_SUP_FL as power supply drive ports; the pins P_RR1, P_FR1, P_RL1 and P_FL1 are connected to the interface M_RR, the interface M_FR, the interface M_RL and the interface M_FL via resistors R1, R2, R3 and R4 respectively, and are grounded via capacitors C1, C2, C3 and C4 respectively; the interface M_RR, the interface M_FR, the interface M_RL and the interface M_FL are connected to the four wheel speed signal submodules of the wheel speed signal switching module (1) respectively.

3. A circuit for redundantly identifying wheel speed signals according to claim 1, characterized in that: The wheel speed signal decoding module (2) comprises a decoding chip M2, which has pins P_RR2, P_FR2, P_RL2 and P_FL2 as sensor power supply ports, and pins M2_DRV_SUP_RR, M2_DRV_SUP_FR, M2_DRV_SUP_RL and M2_DRV_SUP_FL as power supply drive ports; the pins P_RR2, P_FR2, P_RL2 and P_FL2 are connected to the interface M_RR, the interface M_FR, the interface M_RL and the interface M_FL via resistors R5, R6, R7 and R8 respectively, and are grounded via capacitors C5, C6, C7 and C8 respectively.

4. A circuit for redundantly identifying wheel speed signals according to claim 2, characterized in that: The decoding chip M1 is used as a main decoding chip, and the decoding chip M1 is connected to the wheel speed sensor.

5. A circuit for redundantly identifying wheel speed signals according to claim 3, characterized in that: The decoding chip M2 is used as a backup decoding chip, and the decoding chip M2 is connected to the wheel speed sensor.

6. A circuit for redundantly identifying wheel speed signals according to claim 1, characterized in that: The wheel speed signal switching module (1) comprises a first wheel speed signal submodule, a second wheel speed signal submodule, a third wheel speed signal submodule and a fourth wheel speed signal submodule.

7. A circuit for redundantly identifying wheel speed signals according to claim 6, characterized in that: The first wheel speed signal submodule includes a composite transistor Q1 and a composite transistor Q2, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the composite transistor Q1 and the composite transistor Q2 are both composed of two transistors connected; in the composite transistor Q1, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_RR of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_RR, and the emitter of the second transistor is connected to the right rear power supply WSP_RR of the wheel speed sensor; in the composite transistor Q2, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_RR of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_RR, and the emitter of the second transistor is connected to the right rear power supply WSP_RR of the wheel speed sensor.

8. A circuit for redundantly identifying wheel speed signals according to claim 6, characterized in that: The second wheel speed signal submodule includes a compound transistor Q3 and a compound transistor Q4, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the compound transistor Q3 and the compound transistor Q4 are both composed of two transistors connected; in the compound transistor Q3, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_FR of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_FR, and the emitter of the second transistor is connected to the right rear power supply WSP_FR of the wheel speed sensor; in the compound transistor Q4, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_FR of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_FR, and the emitter of the second transistor is connected to the right rear power supply WSP_FR of the wheel speed sensor.

9. A circuit for redundantly identifying wheel speed signals according to claim 6, characterized in that: The third wheel speed signal submodule includes a composite transistor Q5 and a composite transistor Q6, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the composite transistor Q5 and the composite transistor Q6 are both composed of two transistors connected; in the composite transistor Q5, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_RL of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_RL, and the emitter of the second transistor is connected to the right rear power supply WSP_RL of the wheel speed sensor; in the composite transistor Q6, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_RL of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_RL, and the emitter of the second transistor is connected to the right rear power supply WSP_RL of the wheel speed sensor.

10. The circuit for redundantly identifying wheel speed signals according to claim 6, characterized in that: The fourth wheel speed signal submodule includes a composite transistor Q7 and a composite transistor Q8, which are connected to the decoding chip M1 and the decoding chip M2 respectively, and the composite transistor Q7 and the composite transistor Q8 are both composed of two transistors connected; in the composite transistor Q7, the emitter of the first transistor is grounded, the base is connected to the pin M1_DRV_SUP_FL of the decoding chip M1, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface M_FL, and the emitter of the second transistor is connected to the right rear power supply WSP_FL of the wheel speed sensor; in the composite transistor Q8, the emitter of the first transistor is grounded, the base is connected to the pin M2_DRV_SUP_FL of the decoding chip M2, the collector is connected to the base of the second transistor, the collector of the second transistor is connected to the interface S_FL, and the emitter of the second transistor is connected to the right rear power supply WSP_FL of the wheel speed sensor.

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