Enhanced semiconductor packaging device

Abstract

The utility model relates to the technical field of semiconductor devices, and discloses a reinforced semiconductor packaging device, which comprises a packaging body and a chip, the semiconductor packaging device further comprises a die bonding base island, at least one annular groove is arranged at the upper end of the die bonding base island, the chip is arranged above the annular groove, and the chip is arranged above the annular groove. The bonding area of the bonding sheet base island and the bonding sheet glue is increased, and the bonding strength is improved; the lower end of the heat dissipation pad is exposed outside the packaging body, so that heat can be directly dissipated to the outside, high heat dissipation efficiency of the chip is ensured, meanwhile, the bonding sheet base island can be prevented from being directly exposed outside, the bonding sheet base island is better protected, and the problems of water vapor permeation, electric leakage or short circuit and the like caused by the fact that the bonding sheet base island is exposed outside are solved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a reinforced semiconductor packaging device. Background Art

[0002] Currently, consumer products are developing in the direction of miniaturization and high integration. The existing semiconductor packaging structure is to fix the chip on the adhesive base island, and set pins around the adhesive base island. The chip, the adhesive base island and the pins are packaged through the packaging body. The semiconductor packaging structure is widely used due to its superior performance and applicability.

[0003] The semiconductor packaging device can refer to the semiconductor packaging device and lead frame disclosed in Chinese patents such as application number CN202222640473.0. The semiconductor packaging device includes a plastic packaging material, a film-bonding base island encapsulated by the plastic packaging material, a chip fixing pin arranged on the upper surface of the film-bonding base island, and a functional pin electrically connected to the chip. The lower surface of the functional pin is flush with the lower surface of the film-bonding base island, and the lower surface of the film-bonding base island extends out of the lower surface of the plastic packaging material. When the semiconductor packaging device is installed on the circuit board, the film-bonding base island and the functional pins are directly in contact with the circuit board. At this time, the heat generated by the chip can be quickly discharged through the film-bonding base island, and the heat dissipation effect of the semiconductor packaging device is good.

[0004] The existing semiconductor packaging devices have the following problems: 1. The surface of the adhesive substrate island is conventionally designed to be flat, and the adhesive adhesive has poor adhesion to the surface of the adhesive substrate island, which easily causes delamination and detachment between the adhesive adhesive and the substrate island during use; 2. The adhesive substrate island is directly exposed to the outside, which is easy for water vapor to penetrate, and is prone to leakage or short circuit problems, causing device failure. Therefore, the existing technology needs to be improved and developed. Utility Model Content

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a reinforced semiconductor packaging device to solve the problem of delamination and detachment of the adhesive and the base island and the problem that the adhesive base island is directly exposed to the outside and is prone to water vapor penetration, leakage or short circuit.

[0006] A reinforced semiconductor package device comprises a package body and a chip arranged in the package body, and the semiconductor package device further comprises:

[0007] A wafer-bonding base island, wherein the wafer-bonding base island is disposed in the package body, and at least one annular groove is disposed at the upper end of the wafer-bonding base island, and the chip is located above the annular groove;

[0008] A heat dissipation pad is connected to the lower end of the adhesive base island, and the lower end of the heat dissipation pad is exposed outside the packaging body.

[0009] Specifically, the semiconductor packaging device also includes a first pin and a second pin, the first pin is connected to the adhesive base island, and the lower end of the first pin is exposed outside the packaging body; the second pin is connected to the chip through a wire, and the lower end of the second pin is exposed outside the packaging body.

[0010] Specifically, the first pin includes a first inner layer connected to the adhesive base island and a first outer layer connected to the lower end of the first inner layer, the first inner layer is a "convex" structure, and the first outer layer is a "earth" structure.

[0011] Specifically, the second pin includes a second inner layer connected to the chip through the wire and a second outer layer connected to the lower end of the second inner layer, the second inner layer has a "convex" structure, and the second outer layer has a "earth" structure.

[0012] Specifically, the number of the wafer-bonding base islands and the chips is two, and the two wafer-bonding base islands are symmetrically arranged.

[0013] Specifically, at least one groove is provided on the opposite inner sides of the two adhesive base islands.

[0014] Specifically, the groove is an arc-shaped groove.

[0015] Specifically, at least one boss connecting rib is disposed on the outer side surface of the adhesive base island, one end of the boss connecting rib is connected to the frame body and is exposed outside the packaging body after the finished product is cut.

[0016] Specifically, there is a die bonding adhesive between the chip and the die bonding base island.

[0017] Specifically, there are two annular grooves, the depth of the inner annular groove is 0.01-0.03 mm, and the depth of the outer annular groove is 0.03-0.05 mm.

[0018] Beneficial effects of the utility model:

[0019] The utility model discloses a reinforced semiconductor packaging device, wherein at least one annular groove is provided on the upper end of the wafer-bonding base island, so as to increase the bonding area between the wafer-bonding base island and the wafer-bonding adhesive and improve the bonding strength; for ultra-thin chips, the wafer-bonding adhesive can be prevented from overflowing onto the chip surface to cause short circuit and leakage; the outer annular groove design can prevent the wafer-bonding adhesive from spreading out over a large area and overflowing from the plane of the wafer-bonding base island, resulting in poor overflow of adhesive; a heat dissipation pad is connected to the lower end of the wafer-bonding base island, and the lower end of the heat dissipation pad is exposed to the outside of the package body, and the heat is dissipated to the outside through the heat dissipation pad, so as to ensure that the chip has high heat dissipation efficiency and prevent the wafer-bonding base island from being directly exposed to the outside, thereby better protecting the wafer-bonding base island and preventing the wafer-bonding base island from being exposed to the outside to cause water vapor to easily penetrate, thereby causing leakage or short circuit and other problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0021] Figure 1 This is a three-dimensional structural diagram of a reinforced semiconductor packaging device of the utility model;

[0022] Figure 2 This is a planar structural diagram of the interior of an enhanced semiconductor packaging device of the utility model;

[0023] Figure 3 It is a schematic structural diagram of the chip, the adhesive base island, the first pin and the second pin of the utility model;

[0024] Figure 4 It is a front structural schematic diagram of the adhesive base island, the first pin and the second pin of the utility model;

[0025] Figure 5 It is a schematic diagram of the back structure of the adhesive base island, the first pin and the second pin of the utility model;

[0026] Figure 6 It is a cross-sectional structural diagram of the bonding base island and chip position of the utility model.

[0027] The reference numerals are: package body 10 , chip 20 , wafer base island 30 , annular groove 31 , heat dissipation pad 40 , first pin 50 , second pin 60 , wire 63 , groove 32 , boss connecting rib 33 , first inner layer 51 , first outer layer 52 , second inner layer 61 , second outer layer 62 , wafer adhesive 70 . DETAILED DESCRIPTION

[0028] The utility model provides a reinforced semiconductor packaging device. In order to make the purpose, technical solution and effect of the utility model clearer and more specific, the utility model is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0029] In the description of the present invention, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0030] like Figure 1 , Figure 2 , Figure 3As shown, this embodiment discloses a reinforced semiconductor package device, including a package body 10 and a chip 20 disposed in the package body 10, and the semiconductor package device further includes:

[0031] The wafer-bonding base island 30 is disposed in the package body 10, and at least one annular groove 31 is provided at the upper end of the wafer-bonding base island 30, and the chip 20 is located above the annular groove 31;

[0032] The heat dissipation pad 40 is connected to the lower end of the adhesive base island 30 , and the lower end of the heat dissipation pad 40 is exposed outside the package body 10 .

[0033] The semiconductor packaging device of this embodiment is provided with at least one annular groove 31 at the upper end of the wafer base island 30, so as to increase the bonding area between the wafer base island 30 and the wafer adhesive 70 and improve the bonding strength; for ultra-thin chips (chips with a thickness of less than 100 μm), the wafer adhesive 70 can be prevented from overflowing onto the surface of the chip 20 and causing a short circuit; and a space for accommodating the overflowed wafer adhesive 70 is provided for the bonding chip, so as to prevent the wafer adhesive 70 from overflowing the plane of the wafer base island 30 and causing adhesive overflow.

[0034] In the semiconductor packaging device of this embodiment, a heat dissipation pad 40 is connected to the lower end of the wafer base island 30. The heat dissipation pad 40 is located directly below the chip 20. The heat of the chip 20 is first transferred to the wafer base island 30 and then to the heat dissipation pad 40. The heat is dissipated to the outside through the heat dissipation pad 40. By providing the heat dissipation pad 40, the wafer base island 30 can be prevented from being directly exposed to the outside, and the wafer base island 30 can be better protected to prevent the wafer base island 30 from being exposed to the outside, thereby preventing problems such as water vapor penetration, leakage or short circuit caused by the wafer base island 30 being exposed to the outside.

[0035] In the semiconductor packaging device of the present embodiment, the heat dissipation pad 40 can be formed by etching the bottom of the adhesive base island 30. When the PCB pad is designed in the later stage, the lower end of the heat dissipation pad 40 is directly combined with the pad through solder, thereby enhancing the welding strength between the device and the PCB, and at the same time increasing the contact area between the drain of the chip 20 and the PCB, thereby enhancing the electrical and thermal conductivity.

[0036] In addition, the heat dissipation pad 40 of the present embodiment is a rectangular structure, but is not limited to a rectangular structure, and can also be a circular structure, a polygonal structure, etc. The length and width of the heat dissipation pad 40 are smaller than the length and width of the adhesive base island 30, so that a hollow area is formed around the heat dissipation pad 40, and the hollow area is used to fill the plastic encapsulation material. When the plastic encapsulation material is filled and cured, it can not only completely cover the adhesive base island 30 to avoid exposure of the adhesive base island 30, but also improve the structural stability of the adhesive base island 30.

[0037] The semiconductor package device of this embodiment is a MOS tube, having a gate, a source, and a drain, which correspond to the G pole, the S pole, and the D pole respectively. The G pole is an electrode covered with a layer of metal on the insulating layer of the chip 20 and led out. The G pole is the ground terminal, the D pole is the internal MOS tube drain, and the S pole is the internal MOS tube source. In the circuit, the G pole is grounded, the D pole is connected to the positive pole of the power supply, and the S pole is connected to the negative pole of the power supply.

[0038] like Figure 4 As shown, the semiconductor packaging device also includes a first pin 50, which is connected to the wafer base island 30. The lower end of the chip 20 is a drain and is conductively connected to the wafer base island 30, so the first pin 50 serves as a drain lead-out terminal for grounding. The wafer base island 30 and the first pin 50 of this embodiment are made of the same metal plate through punching and etching, so that the first pin 50 and the wafer base island 30 are integrally formed and have good electrical conductivity. This is a better structure, which can ensure the conductive stability of both and reduce costs. Of course, as an alternative, the first pin 50 and the wafer base island 30 can also be designed as separate structures, and then the first pin 50 and the wafer base island 30 are connected by a wire 63, which can also achieve the effect of electrically connecting the first pin 50 and the wafer base island 30.

[0039] like Figure 2 and Figure 4 As shown, the semiconductor package device also includes a second pin 60. The number of second pins 60 corresponding to the same chip 20 is two. The wafer-bonding island 30 and the two second pins 60 of this embodiment are formed by punching out the same metal plate. There is a gap between the two second pins 60 and the wafer-bonding island 30, so that the second pins 60 and the wafer-bonding island 30 are not conductive. One of the second pins 60 is connected to the upper end of the chip 20 through a plurality of wires 63. The upper end of the chip 20 is the source. Therefore, the second pin 60 serves as a source lead-out terminal for an externally connected negative power supply. The other second pin 60 is connected to the metal on the gate of the chip 20 through a wire 63. Therefore, the second pin 60 serves as a gate lead-out terminal.

[0040] like Figure 1 As shown, after the package body 10 of the present embodiment is plastic-sealed, the package body 10 covers the first inner layer 51 of the first pin 50 and the second inner layer 61 of the second pin 60. Since the lower ends of the first pin 50 and the second pin 60 are exposed on the outside of the package body 10, half-mold plastic sealing can be used, that is, only the upper mold is used to plastic-seale the adhesive base island 30, the chip 20, etc. together for protection. The upper ends of the first pin 50 and the second pin 60 are plastic-sealed and covered by the package body 10, and the lower ends of the first pin 50 and the second pin 60 are directly exposed. Therefore, there is no need to use a lower mold, saving the mold opening cost.

[0041] like Figure 5As shown, the first pin 50 includes a first inner layer 51 connected to the adhesive base island 30 and a first outer layer 52 connected to the lower end of the first inner layer 51. The first inner layer 51 is integrally formed with the adhesive base island 30. The first inner layer 51 is a "convex" structure. The "convex" structure is adopted, the outside is closed, and the inside expands the lead welding working surface. The structure is ingenious, and positioning grooves are formed on both sides of the closing position. After the package body 10 is plastic-encapsulated, part of the plastic encapsulation material is filled in the positioning groove position, which enhances the firmness of the first pin 50 and the package body 10.

[0042] like Figure 5 As shown, the first outer layer 52 is in a "earth"-shaped structure or a "work"-shaped structure. The first outer layer 52 in the "earth"-shaped structure or the "work"-shaped structure also forms a clamping groove in the middle of both sides, and the middle clamping groove is effectively used to increase the combination between the plastic encapsulation material and the first pin 50 to prevent the first pin 50 from loosening. In addition, the first pin 50 is designed to be layered, and both layers have clamping grooves, which strengthens the firmness of the first pin 50 and the plastic encapsulation material and solves the problem of loosening and layering caused by the dicing process.

[0043] like Figure 5 As shown, the second pin 60 includes a second inner layer 61 connected to the chip 20 through a wire 63 and a second outer layer 62 connected to the lower end of the second inner layer 61. The second inner layer 61 is a welding layer for welding the wire 63. The second inner layer 61 is a "convex" structure, with a closed end on the outside and an enlarged welding surface on the inside. The structure is ingenious, and positioning grooves are formed on both sides of the closed end. After the package body 10 is plastic-sealed, part of the plastic sealing material is filled in the positioning groove position, thereby enhancing the firmness of the second pin 60 and the package body 10.

[0044] like Figure 5 As shown, the second outer layer 62 is in a "earth"-shaped structure or a "work"-shaped structure. The second outer layer 62 in the "earth"-shaped structure or the "work"-shaped structure also forms a clamping groove in the middle of both sides, and the middle clamping groove is effectively used to increase the combination between the plastic encapsulation material and the second pin 60 to prevent the second pin 60 from loosening. The second pin 60 is designed in layers, and both layers have clamping grooves to strengthen the firmness of the second pin 60 and the plastic encapsulation material, and solve the problem of loosening and delamination caused by the dicing process.

[0045] For small packages, the single-island, single-chip design cannot meet the requirements of dual-chip integrated packaging and separate control. Based on this problem, Figures 1 to 3 As shown, this embodiment adopts a double base island and double chip design, specifically: the number of the adhesive base island 30 and the chip 20 is two, and the two adhesive base islands 30 are symmetrically arranged, and a double base island and double chip bidirectional control output is adopted to achieve the effect of integrated separate control.

[0046] Correspondingly, the number of the first pins 50 is also two, and the number of the second pins 60 is four. After plastic encapsulation, the first pin 50 corresponding to the first chip 20 is arranged on the left side of the lower end of the package body 10, and the second pin 60 corresponding to the second chip 20 is arranged on the left side of the lower end of the package body 10; the first pin 50 corresponding to the second chip 20 is arranged on the right side of the lower end of the package body 10, and the second pin 60 corresponding to the first chip 20 is arranged on the right side of the lower end of the package body 10. Through such a structural arrangement, it is more convenient to solder on the circuit board, and the two heat dissipation pads 40 are located between the two rows of pins, and the heat dissipation efficiency is high.

[0047] like Figure 4 As shown, at least one groove 32 is provided on the inner side surfaces of the two wafer-bonding islands 30 facing each other, and the inner side surface refers to the side surface of the wafer-bonding island 30 facing the center of the package body 10. The groove 32 is an arc groove, but is not limited to the arc groove, and a rectangular groove, a stepped groove, a U-shaped groove, a V-shaped groove, etc. can also be used. The present embodiment uses an arc groove. During packaging, the molding compound can more easily fill the groove 32 along the arc surface. Since the arc structure has no bends or corners, the molding compound is easier to flow. After filling, there is no dead angle, and the filling effect is better. The positions of the grooves 32 of the two wafer-bonding islands 30 are symmetrically arranged along the center of the semiconductor packaging device. After the package body 10 is molded by molding, part of the molding compound is filled in the groove 32 position, which enhances the bite between the wafer-bonding island 30 and the molding compound, and enhances the relative stability between the two wafer-bonding islands 30.

[0048] like Figure 1 and Figure 3 As shown, at least one boss connecting rib 33 is provided on the outer side surface of the wafer base island 30, and the outer side surface refers to the side surface of the wafer base island 30 away from the center of the packaging body 10. The edge gap position of the boss connecting rib 33 is used to fill the plastic molding compound. After the plastic molding compound is molded, the limiting effect of the boss connecting rib 33 is effectively utilized to strengthen the firmness of the wafer base island 30 and the plastic molding compound. The boss connecting rib 33 also serves as a connecting bridge between the wafer base island 30 and the frame body (not shown, an annular frame structure surrounding the outer periphery of the boss connecting rib 33 before cutting), thereby enhancing the firmness of the wafer base island 30 in the frame body.

[0049] Similarly, in order to further strengthen the firmness of the boss connecting rib 33 and the packaging body 10 and prevent water vapor from penetrating, some retaining grooves can be opened on any one side or both sides of the boss connecting rib 33 along the width direction. These retaining grooves can be directly formed when the adhesive base island 30 is punched. The retaining grooves can be arc grooves, but are not limited to arc grooves. Rectangular grooves, stepped grooves, U-shaped grooves, V-shaped grooves, etc. can also be used. After the packaging body 10 is plastic-encapsulated, part of the plastic encapsulation material is filled in the retaining groove position to enhance the bite between the boss connecting rib 33 and the plastic encapsulation material, thereby improving the moisture-proof level of the structure.

[0050] As another way, in order to further strengthen the firmness of the boss connecting rib 33 and the packaging body 10, at least one through hole can be opened at any position of the boss connecting rib 33. These through holes can be directly formed when the adhesive base island 30 is punched, or obtained by subsequent punching. The through holes can be circular holes, but are not limited to circular holes. Rectangular holes, waist-shaped holes, polygonal holes, etc. can also be used. After the packaging body 10 is plastic-encapsulated, part of the plastic encapsulation material fills the through holes to enhance the structural stability between the boss connecting rib 33 and the plastic encapsulation material.

[0051] Conventional base island surfaces are generally designed with a flat surface. The adhesive bonding between the adhesive and the base island surface is poor, and delamination between the adhesive and the base island is likely to occur during use. Based on this problem, Figure 6 As shown, in this embodiment, at least one annular groove 31 is provided at the upper end of the wafer base island 30, and there is a wafer adhesive 70 between the chip 20 and the wafer base island 30. After the wafer adhesive 70 is applied and cured, due to the presence of the annular groove 31, the wafer base island 30 becomes uneven, that is, non-planar. The uneven groove structure increases the roughness of the surface of the wafer base island 30, and the bonding between the wafer adhesive 70 and the wafer base island 30 is more firmly maintained, which avoids the separation and detachment of the wafer adhesive 70 and the wafer base island 30 during the later use process, and has good structural stability.

[0052] like Figure 4 As shown, there are two annular grooves 31 in this embodiment, wherein the depth of the inner annular groove 31 is 0.01-0.03 mm, and the depth of the outer annular groove 31 is 0.03-0.05 mm. The depth of the inner annular groove 31 is designed to be smaller. During the chip bonding process, the adhesive 70 is firstly coated on the lower end of the chip 20, and then the chip 20 is pressed to make the adhesive 70 gradually flow outward under pressure. The flowing adhesive 70 gradually fills the inner annular groove 31 and squeezes out the air in the annular groove 31, and then fills the inner annular groove 31, thereby avoiding the inner annular groove 31 having empty space due to incomplete filling. The air in the inner annular groove 31 is formed into a cavity defect. After the inner annular groove 31 is filled, the outer annular groove 31 is filled. The outer annular groove 31 has a greater depth, which can increase the filling thickness of the adhesive 70 and the storage volume of the filling adhesive 70, effectively preventing the adhesive 70 from overflowing onto the surface of the chip 20. Moreover, the outer annular groove 31 is arranged at the edge of the chip 20, and the chip 20 does not completely cover the outer annular groove 31. Therefore, when the flowing adhesive 70 gradually fills the annular groove 31, the air can be gradually discharged along the outermost edge of the annular groove 31 until the annular groove 31 is filled. In this embodiment, by providing a plurality of annular grooves 31, a space for accommodating the overflow adhesive 70 is provided for bonding the chip 20, so as to prevent the adhesive 70 from overflowing the plane of the adhesive base island 30 and causing adhesive overflow defect.

[0053] The preferred implementation modes of the present invention are specifically described above, but the present invention is not limited to the described embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A reinforced semiconductor package device, comprising a package body (10) and a chip (20) arranged in the package body (10), characterized in that: The semiconductor package device further comprises: A wafer-bonding base island (30), the wafer-bonding base island (30) being arranged in the packaging body (10), the upper end of the wafer-bonding base island (30) being provided with at least one annular groove (31), and the chip (20) being located above the annular groove (31); A heat dissipation pad (40) is connected to the lower end of the adhesive base island (30), and the lower end of the heat dissipation pad (40) is exposed outside the packaging body (10).

2. The enhanced semiconductor package device according to claim 1, characterized in that: The semiconductor package device further comprises a first pin (50) and a second pin (60), wherein the first pin (50) is connected to the adhesive base island (30), and the lower end of the first pin (50) is exposed outside the package body (10); and the second pin (60) is connected to the chip (20) via a wire (63), and the lower end of the second pin (60) is exposed outside the package body (10).

3. The enhanced semiconductor package device according to claim 2, characterized in that: The first pin (50) comprises a first inner layer (51) connected to the adhesive base island (30) and a first outer layer (52) connected to the lower end of the first inner layer (51); the first inner layer (51) is a "convex" structure, and the first outer layer (52) is a "soil" structure.

4. The enhanced semiconductor package device according to claim 2, characterized in that: The second pin (60) comprises a second inner layer (61) connected to the chip (20) via the wire (63) and a second outer layer (62) connected to the lower end of the second inner layer (61); the second inner layer (61) is a "convex" structure, and the second outer layer (62) is a "earth" structure.

5. The enhanced semiconductor package device according to claim 1, characterized in that: The number of the wafer-bonding base island (30) and the chip (20) is two, and the two wafer-bonding base islands (30) are symmetrically arranged.

6. The enhanced semiconductor package device according to claim 5, characterized in that: The opposite inner sides of the two adhesive base islands (30) are each provided with at least one groove (32).

7. The enhanced semiconductor package device according to claim 6, characterized in that: The groove (32) is an arc-shaped groove.

8. The enhanced semiconductor package device according to claim 1, characterized in that: At least one boss connecting rib (33) is provided on the outer side surface of the adhesive base island (30), and one end of the boss connecting rib (33) is exposed outside the packaging body (10).

9. The enhanced semiconductor package device according to claim 1, characterized in that: There is an adhesive tape (70) between the chip (20) and the adhesive base island (30).

10. The enhanced semiconductor package device according to claim 1, characterized in that: There are two annular grooves (31), the depth of the inner annular groove (31) is 0.01-0.03 mm, and the depth of the outer annular groove (31) is 0.03-0.05 mm.

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