QFN packaging structure

Abstract

The utility model provides a quad flat no-lead (QFN) packaging structure, which relates to the field of integrated circuit chip packaging structures, and comprises a chip group, a lead frame and a plastic packaging shell, the chip group is positioned on the upper surface of the lead frame and is fixedly connected with the lead frame, the chip group comprises a plurality of groups of chips, pins of the chips are electrically connected with pins of the lead frame, and the plastic packaging shell is fixedly connected with the chip group. The plastic package shell wraps the chip set and the lead frame to play a role in protecting the chip set and the lead frame, the lower surfaces of the pins in the lead frame are exposed on the outer side of the plastic package shell, the first grooves are formed in the pins, and when the pins of the lead frame are electrically connected and welded with the PCB, the effects of improving pin stress release and material locking are achieved. The first fixing groove and the second fixing groove are formed in the non-electroplating area of the upper surface of the lead frame at intervals, the roughness degree of the upper surface of the lead frame is effectively increased through the first fixing groove and the second fixing groove, then the firmness degree of connection between the plastic package shell and the lead frame is increased, and the problem of large-area layering of the frame is effectively solved.

Description

Technical Field

[0001] The utility model relates to the field of integrated circuit chip packaging structures, in particular to a QFN packaging structure. Background Art

[0002] The traditional QFN package is a package structure in which the pin contact surface is a whole horizontal plane. A pad for mounting the die (chip) is set in the middle of the lead frame, and the pins of the lead frame are distributed around the pad. This traditional QFN package structure has a low pin density, cannot achieve the lead-out of more chip pin signals, cannot meet the arc length and arc height requirements of RF signal control, and the leads will be knocked down during the plastic sealing process and overlap with adjacent leads to cause a short circuit.

[0003] In view of the above shortcomings of the traditional QFN packaging structure, people have improved the traditional QFN packaging structure, and a QFN lead frame with double-row pins has appeared, that is, two rows of pins in the inner and outer circles are made on the lead frame base island, which effectively improves the pin density of the QFN packaging structure. However, in the actual production and application process of this improved QFN packaging structure, the lead frame and the plastic package shell are easily delaminated, and the pins are easily short-circuited during soldering, which reduces the product qualification rate and affects the product quality. Utility Model Content

[0004] In order to solve the problems existing in the above-mentioned prior art, a QFN packaging structure is provided. The technical solution adopted by the utility model to solve the technical problem is:

[0005] A QFN packaging structure comprises a chipset, a lead frame and a plastic package shell, wherein the chipset is located on the upper surface of the lead frame, the chipset comprises a plurality of chips, the chips are electrically connected to the pins of the lead frame, the plastic package shell covers the chipset and the lead frame, the lower surfaces of the pins are exposed outside the plastic package shell, a first fixing groove and a second fixing groove are respectively arranged in a non-electroplating area on the upper surface of the lead frame, and the first fixing groove and the second fixing groove are respectively connected to the plastic package shell.

[0006] Preferably, a first groove is formed on the lower surface of the pin, and the first groove comprises a Solt-shaped half-etched groove.

[0007] Preferably, the first fixing groove comprises a cross-shaped half-etched groove, and the second fixing groove comprises a Solt-shaped half-etched groove.

[0008] Preferably, the length of one side of the first fixing groove is ≥150 μm, and the width of one side of the first fixing groove is ≥70 μm.

[0009] Preferably, the length of one side of the first fixing groove is 150-300 μm, and the width of one side of the first fixing groove is 70-100 μm.

[0010] Preferably, the length of the second fixing groove is ≥200 μm, and the width of the second fixing groove is ≥50 μm.

[0011] Preferably, the length of the second fixing groove is 200-300 μm, and the width of the second fixing groove is 50-100 μm.

[0012] Preferably, the chip is fixedly connected to the upper surface of the lead frame in a coplanar manner, a chip adhesive is coated between the chip and the upper surface of the lead frame, and the chip is electrically connected to the pins by wire bonding.

[0013] Preferably, the chips are fixedly connected to the upper surface of the lead frame in a stacked manner, a top layer glue is coated between the chip located below and the chip adjacent to and above it, the bottom chip is electrically connected to the pins by flip-chip welding, and the other chips are electrically connected to the pins by wire bonding.

[0014] Compared with the prior art, the beneficial effects of the utility model are:

[0015] 1. In the utility model, a first fixing groove and a second fixing groove are arranged in a non-electroplating area on the upper surface of the lead frame at intervals, wherein the first fixing groove comprises a cross-shaped half-etched groove, and the second fixing groove comprises a Solt-shaped half-etched groove, which is beneficial to increase the roughness of the contact surface between the plastic package shell and the lead frame. When the plastic package material is used for plastic packaging, a part of the plastic package material on the plastic package shell will be embedded in the first fixing groove and the second fixing groove, thereby increasing the firmness of the connection between the plastic package shell and the lead frame and improving the problem of large-area delamination of the frame.

[0016] 2. In the utility model, a first groove is provided on the lower surface of the pin of the lead frame, and the first groove includes a Solt-shaped half-etched groove. The lower surface of the pin of the lead frame contacts the PCB board. When welding, the Solt-shaped half-etched groove can not only effectively absorb the stress deformation of the pin caused by heating, but also improve the stress release of the pin caused by thermal deformation. In addition, during welding, excess solder paste flows into the Solt-shaped half-etched groove to form a locking material, and the solder paste does not overflow, which effectively solves the problem of uneven tinning between the DFN package pin and the PCB due to deformation, resulting in a short circuit of the pin.

[0017] 3. The pins of the lead frame in the utility model include two layers of pins, inner pins and outer pins, which effectively improves the density of the pins and is conducive to the miniaturization and high integration of the finished product after packaging. The chip loading method of the chipset can be a multi-chip coplanar method or a chip stacking method according to the design requirements, thereby meeting the arc length and arc height requirements of special leads for different chip packages, and also meeting the common ground requirements of the ground wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 It is a sectional view of the overall structure of the utility model;

[0020] Figure 2 This is a top view of the utility model (chip coplanar mode, plastic packaging shell removed);

[0021] Figure 3 This is a top view of the utility model (chip stacking mode, removing the plastic packaging shell);

[0022] Figure 4 It is a bottom view of the utility model;

[0023] Figure 5 This is an enlarged view of the first fixing groove structure of the utility model;

[0024] Figure 6 This is an enlarged view of the second fixing groove structure of the utility model;

[0025] Figure 7 It is an enlarged view of the first groove structure of the utility model.

[0026] Description of reference numerals:

[0027] 100 chipset; 101 chip; 110 lead frame; 111 first fixing groove; 112 second fixing groove; 113 pin; 114 first groove; 115 adhesive for upper film; 120 plastic package shell. DETAILED DESCRIPTION

[0028] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0029] like Figure 1 As shown, the utility model proposes a QFN packaging structure, which includes:

[0030] A QFN packaging structure, characterized in that it includes a chipset 100, a lead frame 110 and a plastic shell 120, the chipset 100 is located on the upper surface of the lead frame 110, the chipset 100 includes a plurality of chips 101, the chips 101 are electrically connected to the pins 113 of the lead frame 110, the plastic shell 120 covers the chipset 100 and the lead frame 110, the lower surface of the pin 113 is exposed outside the plastic shell 120, and the first fixing groove 111 and the second fixing groove 112 are respectively arranged in a non-electroplating area on the upper surface of the lead frame 110, and the first fixing groove 111 and the second fixing groove 112 are respectively connected to the plastic shell 120.

[0031] A first groove 114 is formed on the lower surface of the pin 113. The first groove 114 includes a Solt-shaped half-etched groove.

[0032] In this embodiment, the chipset 100 is fixedly connected to the upper surface of the lead frame 110, and the pins of the chip 101 in the chipset 100 are electrically connected to the pins 113 of the lead frame 110. During plastic packaging, the plastic packaging shell 120 covers the chipset 100 and the lead frame 110. The plastic packaging shell 120 plays a role in protecting the chipset 100 and the lead frame 110, and the lower surface of the pin 113 is exposed on the outside of the plastic packaging shell 120.

[0033] It should be specially noted that the first fixing grooves 111 and the second fixing grooves 112 are respectively arranged at intervals in the non-electroplating area on the upper surface of the lead frame 110. In the present embodiment, the first fixing grooves 111 are arranged in a circular shape with equal intervals, and the second fixing grooves 112 are arranged in a U-shape with equal intervals. The first fixing grooves 111 and the second fixing grooves 112 effectively increase the roughness of the lead frame 110. During plastic sealing, a portion of the plastic sealing material on the plastic sealing shell 120 will be embedded in the first fixing grooves 111 and the second fixing grooves 112, thereby increasing the firmness of the connection between the plastic sealing shell 120 and the lead frame 110 and improving the problem of large-area delamination of the frame. After the plastic sealing is completed, it is cut to form a single QFN packaged product.

[0034] When the QFN package product is soldered to the PCB board, after applying solder paste on the pad of the PCB board, the lower surface of the pin 113 is brought into contact with the pad of the PCB board. During the heating and soldering process, the first groove 114 can not only effectively absorb the stress deformation of the pin 113 caused by heating, and improve the stress release of the pin 113 caused by thermal deformation, but also the excess solder paste flows into the first groove 114 to form a locking material during welding, and the solder paste does not overflow, which effectively solves the problem of uneven soldering between the DFN package pin and the PCB due to deformation, resulting in a short circuit between the pins.

[0035] like Figure 1-7 As shown, in one embodiment of the QFN package structure of the utility model,

[0036] The first fixing groove 111 includes a cross-shaped half-etched groove, and the second fixing groove 112 includes a Solt-shaped half-etched groove.

[0037] The length of one side of the first fixing groove 111 is ≥150 μm, and the width of one side of the first fixing groove 111 is ≥70 μm.

[0038] The length of one side of the first fixed groove 111 is 150 to 300 μm, and the width of one side of the first fixed groove 111 is 70 to 100 μm. For example, the length a of one side of the first fixed groove 111 can be 150 μm, 200 μm, 250 μm, or 300 μm, and the width b of one side of the first fixed groove 111 can be 70 μm, 80 μm, 90 μm, or 100 μm.

[0039] The length of the second fixing groove 112 is ≥200 μm, and the width of the second fixing groove 112 is ≥50 μm.

[0040] The length of the second fixing groove 112 is 200-300 μm, and the width of the second fixing groove 112 is 50-100 μm. For example, the length c of the second fixing groove 112 can be 200 μm, 250 μm, or 300 μm, and the width d of one side of the second fixing groove 112 can be 50 μm, 75 μm, or 100 μm.

[0041] It should be specially noted that, in the present embodiment, the first fixing groove 111 and the second fixing groove 112 are both made by a half-etching process, which has high precision and consistency, so that the length, width and depth of the first fixing groove 111 and the second fixing groove 112 on the lead frame 110 are consistent, so that when mass production is carried out, each chip product has the same quality and characteristics.

[0042] The chip 101 in the chipset 100 can be fixedly connected to the upper surface of the lead frame 110 in a coplanar manner or a stacked manner according to actual needs, thereby meeting the arc length and arc height requirements of special leads for different chip packages and also meeting the common ground requirements of the ground wires.

[0043] In this embodiment, the pins 113 of the lead frame 110 include two layers of pins, namely, inner pins and outer pins, thereby effectively improving the density of the pins 113 and facilitating miniaturization and high integration of the finished product after packaging.

[0044] When the coplanar form is adopted, the chips 101 in the chipset 100 are laid on the upper surface of the lead frame 110 in a single layer plane, and the chips 101 and the lead frame 110 are coated with a top adhesive 115, and the top adhesive 115 is used to fix the chips 101 and the lead frame 110, and the chips 101 and the pins 113 are connected by wire bonding.

[0045] When the stacking method is adopted, the chips 101 in the chipset 100 are stacked in sequence from bottom to top, and a top layer glue 115 is coated between the chip 101 located at the bottom and the chip 101 adjacent to it and located above it, so as to realize the mutual fixed connection of the chips 101 in the chipset 100, and the bottom chip 101 is electrically connected to the pin 113 by flip-chip welding, and the other chips 101 are electrically connected to the pin 113 by wire bonding.

[0046] Taking the stacking of two layers of chips 101 as an example, the two layers of chips 101 are stacked from bottom to top, and the second layer of chips 101 is bonded to the first layer of chips 101 through the upper glue 115. Then the first layer of chips 101 is interconnected with the inner pins of the lead frame 110 by wire bonding, and the second layer of chips 101 is interconnected with the outer pins of the lead frame 110. Alternatively, pads are also distributed on the back of the first layer of chips 101, and the first layer of chips 101 is welded to the inner pins of the lead frame 110 by flip-chip welding, and the second layer of chips 101 is bonded to the first layer of chips 101 by the upper glue 115, and is interconnected with the outer pins of the lead frame 110 by wire bonding. Finally, through plastic encapsulation and cutting, a single QFN package product is formed.

[0047] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A QFN packaging structure, characterized in that: The invention comprises a chipset (100), a lead frame (110) and a plastic package shell (120); the chipset (100) is located on the upper surface of the lead frame (110); the chipset (100) comprises a plurality of chips (101); the chips (101) are electrically connected to pins (113) of the lead frame (110); the plastic package shell (120) covers the chipset (100) and the lead frame (110); the lower surface of the pins (113) is exposed outside the plastic package shell (120); a first fixing groove (111) and a second fixing groove (112) are respectively arranged in a non-electroplating area on the upper surface of the lead frame (110); the first fixing groove (111) and the second fixing groove (112) are respectively connected to the plastic package shell (120).

2. The QFN package structure according to claim 1, characterized in that: A first groove (114) is formed on the lower surface of the pin (113), and the first groove (114) comprises a Solt-shaped half-etched groove.

3. The QFN package structure according to claim 2, characterized in that: The first fixing groove (111) comprises a cross-shaped half-etched groove, and the second fixing groove (112) comprises a Solt-shaped half-etched groove.

4. The QFN package structure according to claim 3, characterized in that: The length of a single side of the first fixing groove (111) is ≥150 μm, and the width of a single side of the first fixing groove (111) is ≥70 μm.

5. The QFN package structure according to claim 4, characterized in that: The length of a single side of the first fixing groove (111) is 150 to 300 μm, and the width of a single side of the first fixing groove (111) is 70 to 100 μm.

6. The QFN package structure according to claim 3, characterized in that: The length of the second fixing groove (112) is ≥200 μm, and the width of the second fixing groove (112) is ≥50 μm.

7. The QFN package structure according to claim 6, characterized in that: The length of the second fixing groove (112) is 200-300 μm, and the width of the second fixing groove (112) is 50-100 μm.

8. The QFN package structure according to claim 2, characterized in that: The chip (101) is fixedly connected to the upper surface of the lead frame (110) in a coplanar manner, a top layer glue (115) is applied between the chip (101) and the upper surface of the lead frame (110), and the chip (101) is electrically connected to the lead (113) in a wire bonding manner.

9. The QFN package structure according to claim 2, characterized in that: The chips (101) are fixedly connected to the upper surface of the lead frame (110) in a stacked manner, a top layer glue (115) is applied between the chip (101) located at the bottom and the chip (101) adjacent to it and located above it, the bottommost chip (101) is electrically connected to the lead (113) by flip-chip welding, and the other chips (101) are electrically connected to the lead (113) by wire bonding.

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