Protection starting, resetting and alarm hardware logic interlocking circuit

Abstract

The utility model relates to a protection starting, resetting and alarming hardware logic interlocking circuit, which comprises two configurable multifunctional logic gates U41 and U44, a six-path inverter U42 and a six-path open-drain output buffer U43, the configurable multifunctional logic gate U41 receives an alarming signal and an alarming resetting either-or signal output by a central processing unit (CPU), and the six-path open-drain output buffer U43 receives the alarming signal and the alarming resetting either-or signal output by the CPU. The configurable multifunctional logic gate U41 receives a reset signal and an alarm reset either-or signal output by the CPU, output signals of the two configurable multifunctional logic gates enter an input port of the six-way phase inverter U42 respectively, and output signals of the six-way phase inverter U42 enter an input port of the six-way open-drain output buffer U43. The six-way open-drain output buffer U43 further receives a reset signal and a starting signal output by the CPU, and the six-way open-drain output buffer U43 outputs an alarm signal, a reset signal and the starting signal respectively. The circuit is simple in structure, and the reliability is greatly enhanced.

Description

Technical Field

[0001] The utility model relates to the field of electrical automation relay protection, in particular to a protection start, reset and alarm hardware logic interlocking circuit. Background Art

[0002] A relay protection system is a system that automatically removes faulty equipment from the system in the shortest possible time and smallest area when a fault or abnormal operating condition occurs in the power system, or sends a signal to the on-duty personnel to eliminate the root cause of the abnormal condition, so as to reduce or avoid damage to the equipment and the impact on power supply to adjacent areas.

[0003] Relay protection system devices should meet the four basic requirements of reliability, selectivity, sensitivity and speed: these four "properties" are closely related, both contradictory and unified.

[0004] Reliability means that the protection should be reliable when the moving object is being protected and should not be reliable when it should not be. Reliability is the most fundamental requirement for the performance of relay protection system devices.

[0005] If the control logic of the protection circuit of the opening and closing output is too dependent on software interlocking, the reliability is low and it is easily affected by program failure, which will lead to the failure of the protection function and the failure of the power system to operate normally when it fails, causing heavy losses. Therefore, it is necessary to provide a hardware circuit that can realize relay protection. Summary of the invention

[0006] In order to solve the existing technical problems, the utility model provides a protection start, reset and alarm hardware logic interlocking circuit.

[0007] The specific content of the utility model is as follows: a protection start, reset, alarm hardware logic interlock circuit, including two configurable multifunctional logic gates U41, U44, a six-way inverter U42, and a six-way open-drain output buffer U43. The configurable multifunctional logic gate U41 receives the alarm signal and the alarm reset two-choice signal output by the CPU, and the configurable multifunctional logic gate U41 receives the reset signal and the alarm reset two-choice signal output by the CPU. The output signals of the two configurable multifunctional logic gates enter the six-way inverter U42 and the six-way open-drain output buffer U43. The output signal of the six-way inverter U42 enters the input port of the six-way open-drain output buffer U43. The six-way open-drain output buffer U43 also receives a reset signal and a start signal output by the CPU, and the output signals of the 8th, 10th and 12th pins of its output port enter the 13th pin of the six-way inverter U42 after voltage division, and the output signal of the 12th pin of the six-way inverter U42 enters the six-way open-drain output buffer U43. The six-way open-drain output buffer U43 outputs an alarm signal, a reset signal and a start signal respectively.

[0008] Furthermore, the configurable multifunctional logic gates U41 and U44 are both 74LVC1G97GV chips, the six-way inverter U42 is a 74LVC14APW chip, and the six-way open-drain output buffer U43 is a 74LVC07APW chip.

[0009] Furthermore, the alarm signal output from the CPU enters pin 3 of the configurable multifunctional logic gate U41, and pins 3 and 1 of the configurable multifunctional logic gate U41 are grounded through resistors R432 and R433 respectively. The alarm reset binary selection signal output by the CPU enters pin 6 of the configurable multifunctional logic gate U41, and pin 6 of the configurable multifunctional logic gate U41 is also grounded through resistor R438. Pin 4 of the configurable multifunctional logic gate U41 is connected to pin 1 of the six-way inverter U42.

[0010] Furthermore, the resistance of the resistors R432, R433, and R438 is 4.7 kΩ.

[0011] Furthermore, the reset signal output from the CPU enters pin 3 of the configurable multifunctional logic gate U44, and pins 3 and 1 of the configurable multifunctional logic gate U44 are grounded through resistors R443 and R446 respectively. The alarm reset binary selection signal output by the CPU enters pin 6 of the configurable multifunctional logic gate U44, and pin 4 of the configurable multifunctional logic gate U44 is connected to pin 3 of the six-way inverter U42.

[0012] Furthermore, the resistance of the resistors R443 and R446 is 4.7 kΩ.

[0013] Furthermore, pins 5, 9, and 11 of the six-way inverter U42 are grounded through resistors R436, R439, and R441 respectively, pin 2 of the six-way inverter U42 is connected to pins 1 and 9 of the six-way open-drain output buffer U43, pin 4 is connected to pin 3 of the six-way open-drain output buffer U43, and pin 12 is connected to pin 5 of the six-way open-drain output buffer U43.

[0014] Furthermore, the resistance value of the resistors R436, R439, and R441 is 1 kΩ.

[0015] Furthermore, the reset signal output by the hardware watchdog enters pin 11 of the six-way open-drain output buffer U43, and the start signal output by the CPU enters pin 13 of the six-way open-drain output buffer U43. Pin 13 of the six-way open-drain output buffer U43 is also grounded through resistor R447. Pins 2, 4 and 6 of the six-way open-drain output buffer U43 pass through resistors R434, R435 and R437 in turn to output alarm signals, reset signals and start signals. Pins 8, 10 and 12 of the six-way open-drain output buffer U43 pass through resistors R440, R442 and R444 in turn and are connected in parallel to pin 13 of the six-way inverter U42. The parallel circuit of resistors R440, R442 and R444 is connected to the power supply VCC through resistor R445.

[0016] Furthermore, the resistance values ​​of resistors R447 and R445 are 4.7 kΩ, and the resistance values ​​of resistors R434, R435, R437, R440, R442, and R444 are 100Ω.

[0017] The beneficial effects of the utility model are as follows: the circuit structure of the present application is simple, easy to manufacture and maintain, can conveniently realize the protection startup, reset and alarm functions, and is realized in the form of hardware circuits, reducing the dependence on software, and can avoid the problem that software control is susceptible to program runaway and hanging, so the reliability is greatly enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The specific implementation of the utility model is further explained below in conjunction with the accompanying drawings.

[0019] Figure 1 It is a schematic diagram of the protection start, reset and alarm hardware logic interlock circuit of the utility model. DETAILED DESCRIPTION

[0020] Combination Figure 1 The protection start, reset and alarm hardware logic interlock circuit of the utility model is as follows:

[0021] The circuit includes two configurable multifunctional logic gates U41 and U44, a six-way inverter U42, and a six-way open-drain output buffer U43. The configurable multifunctional logic gate U41 receives an alarm signal and an alarm reset signal output by the CPU. The configurable multifunctional logic gate U41 receives a reset signal and an alarm reset signal output by the CPU. The output signals of the two configurable multifunctional logic gates enter the input ports of the six-way inverter U42 respectively. The output signal of the six-way inverter U42 enters the input port of the six-way open-drain output buffer U43. The six-way open-drain output buffer U43 also receives a reset signal and a start signal output by the CPU. The output signals of the 8th, 10th and 12th pins of its output port enter the 13th pin of the six-way inverter U42 after voltage division. The output signal of the 12th pin of the six-way inverter U42 enters the six-way open-drain output buffer U43. The six-way open-drain output buffer U43 outputs an alarm signal, a reset signal and a start signal respectively.

[0022] Preferably, in this embodiment, the configurable multifunctional logic gates U41 and U44 are both 74LVC1G97GV chips, the six-way inverter U42 is a 74LVC14APW chip, and the six-way open-drain output buffer U43 is a 74LVC07APW chip.

[0023] The alarm signal output from the CPU enters pin 3 of the configurable multifunctional logic gate U41, and pins 3 and 1 of the configurable multifunctional logic gate U41 are grounded through resistors R432 and R433 respectively. The alarm reset binary selection signal output by the CPU enters pin 6 of the configurable multifunctional logic gate U41, and pin 6 of the configurable multifunctional logic gate U41 is also grounded through resistor R438. Pin 4 of the configurable multifunctional logic gate U41 is connected to pin 1 of the six-way inverter U42.

[0024] Preferably, in this embodiment, the resistance of resistors R432, R433, and R438 is 4.7 kΩ.

[0025] The reset signal output from the CPU enters pin 3 of the configurable multifunctional logic gate U44. Pins 3 and 1 of the configurable multifunctional logic gate U44 are grounded through resistors R443 and R446 respectively. The alarm reset binary selection signal output by the CPU enters pin 6 of the configurable multifunctional logic gate U44. Pin 4 of the configurable multifunctional logic gate U44 is connected to pin 3 of the six-way inverter U42.

[0026] Preferably, in this embodiment, the resistance of resistors R443 and R446 is 4.7 kΩ.

[0027] Pins 5, 9 and 11 of the six-way inverter U42 are grounded through resistors R436, R439 and R441 respectively, pin 2 of the six-way inverter U42 is connected to pins 1 and 9 of the six-way open-drain output buffer U43, pin 4 is connected to pin 3 of the six-way open-drain output buffer U43, and pin 12 is connected to pin 5 of the six-way open-drain output buffer U43.

[0028] Preferably, in this embodiment, the resistance of the resistors R436, R439, and R441 is 1 kΩ.

[0029] The reset signal output by the hardware watchdog enters pin 11 of the six-way open-drain output buffer U43, and the start signal output by the CPU enters pin 13 of the six-way open-drain output buffer U43. Pin 13 of the six-way open-drain output buffer U43 is also grounded through resistor R447. Pins 2, 4 and 6 of the six-way open-drain output buffer U43 pass through resistors R434, R435 and R437 in turn to output alarm signals, reset signals and start signals. Pins 8, 10 and 12 of the six-way open-drain output buffer U43 pass through resistors R440, R442 and R444 in turn and are connected in parallel to pin 13 of the six-way inverter U42. The parallel circuit of resistors R440, R442 and R444 is connected to the power supply VCC through resistor R445.

[0030] Preferably, in this embodiment, the resistance values ​​of the resistors R447 and R445 are 4.7 kΩ, and the resistance values ​​of the resistors R434, R435, R437, R440, R442, and R444 are 100Ω.

[0031] Here’s how this application works:

[0032] The definition of each signal is as follows: To DO board signal:

[0033] DO_GJ: Alarm signal, low level is valid;

[0034] DO_FG: reset signal, low level is valid;

[0035] DO_QD: Start signal, low level is valid.

[0036] Output signal from the host processor:

[0037] DO_GJ_IN: CPU outputs alarm signal, high level is valid, low level by default;

[0038] DO_FG_IN: CPU output reset signal, high level is valid, low level by default;

[0039] DO_SEL_GJ_FG#: CPU outputs alarm or reset signals, either high level for alarm output or low level for reset output.

[0040] RSTn: reset signal, output from hardware watchdog, low level is valid;

[0041] DO_QD_IN: CPU output start signal, high level is valid, low level by default.

[0042] When DO_SEL_GJ_FG# =1, DO_GJ = / DO_GJ_IN, otherwise DO_GJ=1;

[0043] When DO_SEL_GJ_FG# = 0, DO_FG = / DO_FG_IN, otherwise DO_FG = 1;

[0044] / When the three signal lines DO_GJ_IN, RSTn, and DO_QD_IN are 1 at the same time, DO_QD can output a valid signal 0, otherwise it is 1.

[0045] Specific working process:

[0046] DO_GJ alarm signal output:

[0047] DO_SEL_GJ_FG# =1 (U41.6, which can be used to configure the 6th pin of the multi-function logic gate U41), DO_GJ_IN=1 (U41.3), then U41.4 outputs 1, enters U42.1, and after inversion, U42.2 outputs 0, enters U43.1, and finally U43.2 outputs 0 to the DO board's DO_GJ signal. At the same time, the 0 output by U42.2 also enters U43.9, the purpose is to lock the start signal, so that U43.8 outputs 0, this signal goes to U42.13, after inversion, U42.12 outputs 1, enters U43.5, and then U43.6 outputs high impedance to the DO board's DO_QD signal.

[0048] DO_FG reset signal output:

[0049] DO_SEL_GJ_FG# =0 (U44.6), DO_FG_IN=1 (U44.1), then U44.4 outputs 1 and enters U42.3. After inversion, U42.4 outputs 0 and enters U43.3. Finally, U43.4 outputs 0 to the DO_FG signal of the DO board.

[0050] DO_QD start signal output:

[0051] U43.9=1 (no alarm), RSTn=1 (U43.11, the system is not in reset state), DO_QD_IN=1 (U43.13), then the 8th, 10th, and 12th pins of U43 are all in high impedance state. Due to the addition of the R445 pull-up resistor, the input of U42.13 is 1, and after inversion, U42.12 outputs 0 and enters U43.5. Finally, U43.6 outputs 0 to the DO_QD signal of the DO board.

[0052] It can be seen that the present application forms a circuit through two configurable multifunctional logic gates 74LVC1G97GV, a six-inverter 74LVC14APW, a six-way open-drain output buffer 74LVC07APW and other pull-up and pull-down resistors and series resistors. Among them, the two multifunctional logic gates 74LVC1G97GV play the role of mutually exclusive output of reset and alarm signals, the six-inverter 74LVC14APW plays an inverting role, the open-drain output buffer 74LVC07APW plays an open-drain output, as well as the line AND function of the alarm, reset and start signals. Finally, the functions of protection start, reset and alarm are realized through hardware, which improves the reliability of the relay protection system, and therefore has good application prospects.

[0053] In the above description, many specific details are described to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited by the specific implementation disclosed above. At the same time, any person familiar with the technical field can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A protection start, reset, and alarm hardware logic interlock circuit, characterized in that: It includes two configurable multifunctional logic gates U41 and U44, a six-way inverter U42, and a six-way open-drain output buffer U43. The configurable multifunctional logic gate U41 receives an alarm signal and an alarm reset signal output by the CPU. The configurable multifunctional logic gate U41 receives a reset signal and an alarm reset signal output by the CPU. The output signals of the two configurable multifunctional logic gates enter the input ports of the six-way inverter U42 respectively, and the output signal of the six-way inverter U42 enters the input port of the six-way open-drain output buffer U43. The six-way open-drain output buffer U43 also receives a reset signal and a start signal output by the CPU, and the output signals of the 8th, 10th and 12th pins of its output port enter the 13th pin of the six-way inverter U42 after voltage division, and the output signal of the 12th pin of the six-way inverter U42 enters the six-way open-drain output buffer U43. The six-way open-drain output buffer U43 outputs an alarm signal, a reset signal and a start signal respectively.

2. The protection start, reset and alarm hardware logic interlock circuit according to claim 1 is characterized in that: The configurable multifunctional logic gates U41 and U44 are both 74LVC1G97GV chips, the six-way inverter U42 is a 74LVC14APW chip, and the six-way open-drain output buffer U43 is a 74LVC07APW chip.

3. The protection start, reset and alarm hardware logic interlock circuit according to claim 2, characterized in that: The alarm signal output from the CPU enters pin 3 of the configurable multifunctional logic gate U41, and pins 3 and 1 of the configurable multifunctional logic gate U41 are grounded through resistors R432 and R433 respectively. The alarm reset binary selection signal output by the CPU enters pin 6 of the configurable multifunctional logic gate U41, and pin 6 of the configurable multifunctional logic gate U41 is also grounded through resistor R438. Pin 4 of the configurable multifunctional logic gate U41 is connected to pin 1 of the six-way inverter U42.

4. The protection start, reset and alarm hardware logic interlock circuit according to claim 3 is characterized in that: The resistance of resistors R432, R433, and R438 is 4.7 kΩ.

5. The protection start, reset and alarm hardware logic interlock circuit according to claim 3 is characterized in that: The reset signal output from the CPU enters pin 3 of the configurable multifunctional logic gate U44. Pins 3 and 1 of the configurable multifunctional logic gate U44 are grounded through resistors R443 and R446 respectively. The alarm reset binary selection signal output by the CPU enters pin 6 of the configurable multifunctional logic gate U44. Pin 4 of the configurable multifunctional logic gate U44 is connected to pin 3 of the six-way inverter U42.

6. The protection start, reset and alarm hardware logic interlock circuit according to claim 5 is characterized in that: The resistance of resistors R443 and R446 is 4.7 kΩ.

7. The protection start, reset and alarm hardware logic interlock circuit according to claim 5 is characterized in that: Pins 5, 9 and 11 of the six-way inverter U42 are grounded through resistors R436, R439 and R441 respectively, pin 2 of the six-way inverter U42 is connected to pins 1 and 9 of the six-way open-drain output buffer U43, pin 4 is connected to pin 3 of the six-way open-drain output buffer U43, and pin 12 is connected to pin 5 of the six-way open-drain output buffer U43.

8. The protection start, reset and alarm hardware logic interlock circuit according to claim 7, characterized in that: The resistance value of resistors R436, R439, and R441 is 1 kΩ.

9. The protection start, reset and alarm hardware logic interlock circuit according to claim 7 is characterized in that: The reset signal output by the hardware watchdog enters pin 11 of the six-way open-drain output buffer U43, and the start signal output by the CPU enters pin 13 of the six-way open-drain output buffer U43. Pin 13 of the six-way open-drain output buffer U43 is also grounded through resistor R447. Pins 2, 4 and 6 of the six-way open-drain output buffer U43 pass through resistors R434, R435 and R437 in turn to output alarm signals, reset signals and start signals. Pins 8, 10 and 12 of the six-way open-drain output buffer U43 pass through resistors R440, R442 and R444 in turn and are connected in parallel to pin 13 of the six-way inverter U42. The parallel circuit of resistors R440, R442 and R444 is connected to the power supply VCC through resistor R445.

10. The protection start, reset and alarm hardware logic interlock circuit according to claim 9, characterized in that: The resistance values ​​of resistors R447 and R445 are 4.7 kΩ, and the resistance values ​​of resistors R434, R435, R437, R440, R442, and R444 are 100Ω.

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