Combination key forced restart system

Abstract

The utility model provides a combination key forced restart system. The combination key forced restart system comprises a PWRON key circuit, a RESTORE key circuit, an RC low-level delay circuit, an AND gate circuit, an RC high-level delay circuit, an open-drain output circuit, a load switch circuit and a battery. The PWRON key circuit is connected with the AND gate circuit; the RESTORE key circuit is connected with the RC low-level delay circuit, and the RC low-level delay circuit is connected with the AND gate circuit; the RC high-level delay circuit is connected with the AND gate circuit, and the RC high-level delay circuit is connected with the open-drain output circuit; the output end of the open-drain output circuit is connected with the enable pin of the load switch circuit; the input end of the load switch circuit is connected with the VBAT pin of the battery, and the output end of the load switch circuit is connected with the main system. According to the utility model, effective restarting can be realized through the two combined keys, the participation of software is completely eliminated, the design cost is lower, the development is simpler and more efficient, the maintainability is high, the application range is wide, and the stability is high.

Description

Technical Field

[0001] The utility model relates to the technical field of forced shutdown and restart, in particular to a combination key forced restart system. Background Art

[0002] With the rapid development of electronic products, the requirements for product appearance are getting higher and higher, and thin and light bodies are deeply loved by people. Therefore, the design of non-removable batteries has become the development direction of such products.

[0003] However, the fact that the battery cannot be removed also brings a problem while pursuing a thin body and aesthetics. When the system freezes, it can no longer be solved by simply removing the battery. If the forced restart operation is not designed properly, it will affect the overall performance of the electronic product.

[0004] The existing forced restart method is usually: when the system crashes, an external key interrupt is processed by an MCU independent of the system, thereby achieving a forced restart of the system.

[0005] However, the existing forced restart method is only applicable to solutions with independent MCUs, which has a very limited scope of application, and the MCU itself may also have abnormalities and cannot cover all scenarios when the system crashes. In addition, since an additional MCU is required, the cost of use is high. Utility Model Content

[0006] In view of this, the purpose of the utility model is to design a combination key forced restart system, which adopts RC delay circuit, AND gate circuit, open drain output circuit and load switch circuit in hardware, and completes the control of powering off, powering on and booting up the system by pressing two combination keys of PWRON key circuit and RESTORE key circuit at the same time, completely gets rid of the involvement of software and does not need to connect to an external MCU; on the basis of non-removable battery, the product can be effectively restarted by long pressing the combination key after encountering an extreme freeze, thereby improving the maintainability of the product, reducing the design cost, making the development simpler and more efficient, flexible in configuration, more widely applicable, and improving the stability of the product.

[0007] The utility model provides a combination key forced restart system, comprising: a PWRON (power switch) key circuit, a RESTORE (reset) key circuit, an RC low level delay circuit, an AND gate circuit, an RC high level delay circuit, an open drain output circuit, a load switch circuit, and a battery;

[0008] The PWRON key circuit is electrically connected to the AND gate circuit; the RESTORE key circuit is electrically connected to the RC low-level delay circuit, and the RC low-level delay circuit is electrically connected to the AND gate circuit; the high level generated by the RESTORE key circuit is input to the AND gate circuit as a low-level delay, and the low-level delay time is set by matching the resistor R and the capacitor C, and the time from the high level to the power-off of the main system input voltage VSYS is adjusted, and at the same time, the PWRON key circuit and the RESTORE key circuit can be prevented from being triggered by mistake and causing abnormal power-off of VSYS;

[0009] The PWRON button circuit and the RESTORE button circuit act on the source of the PMOS tube and the gate of the NMOS tube of the AND gate circuit respectively by direct connection and delay. Only when the two buttons of the PWRON button circuit and the RESTORE button circuit are pressed at the same time, will they output a high level, so that the combination button can take effect. Pressing the PWRON button alone can realize the power on and off function of the main system under normal conditions, and pressing the RESTORE button alone can realize the factory reset function of the main system under normal conditions.

[0010] The RC high-level delay circuit is electrically connected to the AND gate circuit, and the RC high-level delay circuit is electrically connected to the open-drain output circuit; the RC high-level delay circuit delays the high level generated by the AND gate circuit to the open-drain output circuit, and sets the high-level delay time by matching the resistor R and the capacitor C, adjusts the time from power-off to power-on recovery of the input voltage VSYS of the main system, and realizes the setting of the effective time of the combination key forced restart.

[0011] The output end of the open-drain output circuit is electrically connected to the enable pin of the load switch circuit; the load switch circuit is enabled by the input level of the open-drain output circuit to realize powering off and powering on of the input voltage VSYS of the main system.

[0012] The input end of the load switch circuit is connected to the battery voltage power supply VBAT pin of the battery, and the output end of the load switch circuit is connected to the main system.

[0013] Furthermore, the AND gate circuit includes: a PMOS tube Q2, a resistor R4, an NMOS tube Q1, and a resistor R2; the PMOS tube Q2 and the resistor R4 are connected in series, the NMOS tube Q1 and the resistor R2 are connected in series, and the PMOS tube Q2 and the resistor R4 are connected in parallel with the NMOS tube Q1 and the resistor R2;

[0014] The source of the PMOS tube Q2 is electrically connected to the output end of the PWRON key circuit; the gate of the NMOS tube Q1 is electrically connected to the output end of the RC low-level delay circuit.

[0015] The AND gate circuit generates a high level only when both the PMOS tube and the NMOS tube are at a high level; even if one of the MOS tubes is at a low level, the AND gate circuit outputs a low level. Thus, pressing the PWRON button or the RESTORE button alone has no effect on the output of the AND gate circuit.

[0016] Further, the RC low-level delay circuit includes: a resistor R1, a diode D2, and a capacitor C4, wherein the resistor R1 and the diode D2 are connected in parallel and then connected in series with the capacitor C4;

[0017] The output end of the RESTORE button circuit is electrically connected to the input end of the RC low-level delay circuit.

[0018] In the RC low-level delay circuit, resistor R1 charges capacitor C4, and diode D2 discharges capacitor C4 instantly, so that the RC low-level delay circuit is always effective.

[0019] Further, the RC high-level delay circuit includes: a resistor R9, a diode D4, and a capacitor C7, wherein the resistor R9 and the diode D4 are connected in parallel and then connected in series with the capacitor C7;

[0020] The input end of the RC high-level delay circuit is electrically connected to the output end of the AND gate circuit, and the output end of the RC high-level delay circuit is electrically connected to the input end of the open-drain output circuit.

[0021] In the RC high-level delay circuit, resistor R9 charges capacitor C7, and diode D4 discharges capacitor C7 instantly, so that the RC high-level delay circuit is always effective.

[0022] Furthermore, the open-drain output circuit includes: a MOS tube Q3, a gate of the MOS tube Q3 is electrically connected to the output end of the RC high-level delay circuit, and a drain of the MOS tube Q3 is electrically connected to the enable pin of the load switch circuit.

[0023] The open-drain output circuit enables the load switch circuit according to the input level.

[0024] Further, the load switch circuit includes: a resistor R6, a resistor R7, a resistor R8, a capacitor C9, an NMOS tube Q5, and an NMOS tube Q4, wherein the resistor R6, the resistor R7, and the resistor R8 are connected in parallel, the capacitor C9 is connected in parallel between the source and the gate of the NMOS tube Q5, the resistor R6 and the resistor R7 are connected between the source of the NMOS tube Q5 and the gate of the NMOS tube Q4, the resistor R8 is connected between the gate of the NMOS tube Q5 and the drain of the NMOS tube Q4, and the drain of the NMOS tube Q5 is connected to the input voltage VSYS pin of the main system;

[0025] The enable pin of the load switch circuit is the gate of the NMOS tube Q4.

[0026] The output end of the load switch circuit supplies power to the main system, and the enable pin of the load switch circuit powers off and on the main system input voltage VSYS pin from the battery voltage power supply VBAT pin according to the enable state of the open-drain output circuit.

[0027] Further, the PWRON key circuit includes: a capacitor C5, a capacitor C6, a diode D3, a switch S2, and a diode D6. The capacitor C5, the capacitor C6, and the diode D3 are connected in parallel and then connected in series with the output end of the switch S2. The diode D6 is connected in series with the input end of the switch S2.

[0028] The input end of the switch S2 is connected to the battery voltage power supply VBAT pin of the battery.

[0029] Furthermore, the RESTORE button circuit includes: a capacitor C1, a capacitor C2, a diode D1, a switch S1, and a diode D5. The capacitor C1, the capacitor C2, and the diode D1 are connected in parallel and then connected in series with the output end of the switch S1. The diode D5 is connected in series with the input end of the switch S1.

[0030] The input end of the switch S1 is connected to the battery voltage power supply VBAT pin of the battery.

[0031] Furthermore, the drain of the PMOS tube Q2 of the AND gate circuit is used as an output terminal, connected to the ground GND by a resistor R4 (preferably a 1K resistor), to suppress parasitic conduction from the source to the drain of the PMOS tube, and prevent abnormal power-off of VSYS caused by pressing the PWRON button alone.

[0032] Furthermore, the source of the NMOS tube Q1 of the AND gate circuit is grounded GND, which suppresses the parasitic conduction from the source to the drain of the NMOS tube, thereby preventing abnormal power-off of VSYS caused by pressing the PWRON button alone.

[0033] Compared with the prior art, the beneficial effects of the utility model are:

[0034] The combination key forced restart system of the utility model adopts RC delay circuit, AND gate circuit, open-drain output circuit and load switch circuit in hardware. On the basis of non-removable battery, after the product encounters an extreme freeze, by simultaneously pressing two combination keys of PWRON key circuit and RESTORE key circuit, the main system can be effectively restarted, and the control of powering off, powering on and then starting the main system is completed. The whole process is completely free from the participation of software and does not need to connect to an external MCU. Compared with the existing external interrupt in the freeze state handled by an independent MCU, the design cost is lower, the development is simpler and more efficient, the maintainability is higher, the application is wider, and the product stability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those skilled in the art. The accompanying drawings are only for the purpose of illustrating the preferred embodiment and are not to be considered as limiting the present invention.

[0036] In the attached picture:

[0037] Figure 1 This is a schematic diagram of the architecture of a combination key forced restart system of the utility model;

[0038] Figure 2 This is a circuit schematic diagram of a combination key forced restart system according to an embodiment of the utility model.

[0039] The symbols in the accompanying drawings are:

[0040] 1. RESTORE button circuit; 2. RC low level delay circuit;

[0041] 3. AND gate circuit; 4. PWRON button circuit;

[0042] 5. RC high level delay circuit; 6. Open drain output circuit;

[0043] 7. Load switch circuit; 8. Battery;

[0044] 9. Main system. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0046] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0047] It should be understood that although the terms first, second, and third may be used in the present disclosure to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0048] The utility model embodiment provides a combination key forced restart system, see Figure 1 , 2 As shown, it includes: a PWRON button circuit 4, a RESTORE button circuit 1, an RC low level delay circuit 2, an AND gate circuit 3, an RC high level delay circuit 5, an open drain output circuit 6, a load switch circuit 7, and a battery 8;

[0049] The PWRON button circuit 4 is electrically connected to the AND gate circuit 3; after the PWRON button is pressed, the PWRON button circuit 4 generates a high level output to provide an input to the AND gate circuit 3;

[0050] The RESTORE button circuit 1 is electrically connected to the RC low level delay circuit 2, and the RC low level delay circuit 2 is electrically connected to the AND gate circuit 3;

[0051] Specifically, after the RESTORE button is pressed, the RESTORE button circuit 1 generates a high level output, and the RC low level delay circuit 2 delays the high level generated by the RESTORE button circuit 1 to the AND gate circuit 3 as a low level, providing another input of the AND gate circuit 3. The high level generated by the RESTORE button circuit 1 is delayed as a low level input to the AND gate circuit 3, and the low level delay time is set by matching the resistor R and the capacitor C, and the time from the high level to the power-off of the main system input voltage VSYS is adjusted, and at the same time, the PWRON button circuit 4 and the RESTORE button circuit 1 can be prevented from being triggered by mistake, resulting in abnormal power-off of VSYS;

[0052] The PWRON button circuit 4 and the RESTORE button circuit 1 act on the source and gate input terminals of the PMOS tube and the NMOS tube of the AND gate circuit 3 respectively by direct connection and delay. Only when the two buttons of the PWRON button circuit 4 and the RESTORE button circuit are pressed at the same time, will they output a high level, so that the combination button can take effect.

[0053] The RC high-level delay circuit 5 is electrically connected to the AND gate circuit 3, and the RC high-level delay circuit 5 is electrically connected to the open-drain output circuit 6; the RC high-level delay circuit 5 delays the high level generated by the AND gate circuit 3 and inputs it to the open-drain output circuit 6, and sets the high-level delay time by matching the resistor R and the capacitor C, and adjusts the time from power-off to power-on recovery of the input voltage VSYS of the main system 9, so as to realize the setting of the effective time of the combination key forced restart.

[0054] The output end of the open-drain output circuit 6 is electrically connected to the enable pin of the load switch circuit 7; the load switch circuit 7 is enabled by the input level of the open-drain output circuit 6, so as to power on and off the input voltage VSYS of the main system 9.

[0055] The input end of the load switch circuit 7 is connected to the battery voltage power supply VBAT pin of the battery 8; the output end of the load switch circuit 7 is connected to the main system 9 to supply power to the input voltage VSYS of the main system 9, and completes the power-off and power-on of VBAT to VSYS according to the enable state of the open-drain output circuit 6.

[0056] When the main system 9 of the electronic product freezes and cannot respond to external interrupts, when the two buttons of the PWRON button circuit 4 and the RESTORE button circuit 1 are pressed and held for a set time at the same time, all circuits work closely together to allow the main system 9 to complete the entire process from power-off to power-on and then to startup, and restore the main system 9 to normal without the involvement of software.

[0057] In this embodiment, the AND gate circuit 3 includes: a PMOS tube Q2, a resistor R4, an NMOS tube Q1, and a resistor R2; the PMOS tube Q2 and the resistor R4 are connected in series, the NMOS tube Q1 and the resistor R2 are connected in series, and the PMOS tube Q2 and the resistor R4 are connected in parallel with the NMOS tube Q1 and the resistor R2;

[0058] The source of the PMOS tube Q2 is electrically connected to the output end of the PWRON key circuit 4 ; the gate of the NMOS tube Q1 is electrically connected to the output end of the RC low-level delay circuit 2 .

[0059] The AND gate circuit 3 generates a high level only when both the PMOS tube and the NMOS tube are at a high level; even if one of the MOS tubes is at a low level, the AND gate circuit 3 outputs a low level. Thus, pressing the PWRON button or the RESTORE button alone has no effect on the output of the AND gate circuit 3.

[0060] The RC low-level delay circuit 2 comprises: a resistor R1, a diode D2, and a capacitor C4, wherein the resistor R1 and the diode D2 are connected in parallel and then connected in series with the capacitor C4;

[0061] The output end of the RESTORE button circuit 1 is electrically connected to the input end of the RC low-level delay circuit 2 .

[0062] In the RC low-level delay circuit 2, the resistor R1 charges the capacitor C4, and the diode D2 discharges the capacitor C4 instantly, so that the RC low-level delay circuit 2 is always effective.

[0063] The RC high level delay circuit 5 comprises: a resistor R9, a diode D4, and a capacitor C7, wherein the resistor R9 and the diode D4 are connected in parallel and then connected in series with the capacitor C7;

[0064] The input end of the RC high level delay circuit 5 is electrically connected to the output end of the AND gate circuit 3 , and the output end of the RC high level delay circuit 5 is electrically connected to the input end of the open drain output circuit 6 .

[0065] In the RC high level delay circuit 5 , the resistor R9 charges the capacitor C7 , and the diode D4 discharges the capacitor C7 instantly, so that the RC high level delay circuit 5 is always effective.

[0066] The open-drain output circuit 6 includes a MOS transistor Q3 , a gate of which is electrically connected to the output end of the RC high-level delay circuit 5 , and a drain of which is electrically connected to the enable pin of the load switch circuit 7 .

[0067] The open-drain output circuit 6 enables the load switch circuit 7 according to the input level.

[0068] The load switch circuit 7 includes: a resistor R6, a resistor R7, a resistor R8, a capacitor C9, an NMOS tube Q5, and an NMOS tube Q4. The resistors R6, R7, and R8 are connected in parallel. The capacitor C9 is connected in parallel between the source and the gate of the NMOS tube Q5. The resistors R6 and R7 are connected between the source of the NMOS tube Q5 and the gate of the NMOS tube Q4. The resistor R8 is connected between the gate of the NMOS tube Q5 and the drain of the NMOS tube Q4. The drain of the NMOS tube Q5 is connected to the input voltage VSYS pin of the main system 9.

[0069] The enable pin of the load switch circuit 7 is the gate of the NMOS tube Q4.

[0070] The output end of the load switch circuit 7 supplies power to the main system 9, and the enable pin of the load switch circuit 7 completes powering off and on of the main system input voltage VSYS pin from the battery voltage power supply VBAT pin according to the enable state of the open-drain output circuit 6.

[0071] The PWRON key circuit 4 includes: a capacitor C5, a capacitor C6, a diode D3, a switch S2, and a diode D6. The capacitor C5, the capacitor C6, and the diode D3 are connected in parallel and then connected in series with the output end of the switch S2. The diode D6 is connected in series with the input end of the switch S2.

[0072] The input end of the switch S2 is connected to the battery voltage power supply VBAT pin of the battery 8 .

[0073] The RESTORE button circuit includes: a capacitor C1, a capacitor C2, a diode D1, a switch S1, and a diode D5. The capacitor C1, the capacitor C2, and the diode D1 are connected in parallel and then connected in series with the output end of the switch S1. The diode D5 is connected in series with the input end of the switch S1.

[0074] The input end of the switch S1 is connected to the battery voltage power supply VBAT pin of the battery 8 .

[0075] The drain of the PMOS tube Q2 of the AND gate circuit 3 is used as an output terminal, and is connected to the ground GND with a 1K resistor to suppress the parasitic conduction from the source to the drain of the PMOS tube, thereby preventing abnormal power-off of VSYS caused by pressing the PWRON button alone.

[0076] The source of the NMOS tube Q1 of the AND gate circuit 3 is grounded GND, which suppresses the parasitic conduction from the source to the drain of the NMOS tube, and prevents abnormal power-off of VSYS caused by pressing the PWRON button alone.

[0077] In specific use, when the main system 9 of the electronic product freezes and cannot respond to external interrupts, the PWRON button circuit 4 and the RESTORE button circuit 1 are pressed and held for a set time at the same time. Through the combination key, all circuits of the system are forced to work closely together to restart the main system 9, so that the main system 9 can complete the entire process from power-off to power-on and then to startup. In addition, when the main system 9 is in normal working condition, it will not cause abnormal power-off due to false triggering of the combination key, nor will it cause abnormal power-off due to triggering of a single key.

[0078] So far, the technical solution of the utility model has been described in conjunction with the preferred embodiments shown in the accompanying drawings, but it is easy for those skilled in the art to understand that the protection scope of the utility model is obviously not limited to these specific embodiments. Without departing from the principle of the utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the utility model.

[0079] The above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. For those skilled in the art, the utility model may have various modifications and changes. Any modification, replacement, and improvement made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A key combination for forcibly restarting a system, characterized in that: include: PWRON button circuit, RESTORE button circuit, RC low level delay circuit, AND gate circuit, RC high level delay circuit, open drain output circuit, load switch circuit, battery; The PWRON key circuit is electrically connected to the AND gate circuit; the RESTORE key circuit is electrically connected to the RC low level delay circuit, and the RC low level delay circuit is electrically connected to the AND gate circuit; The RC high level delay circuit is electrically connected to the AND gate circuit, and the RC high level delay circuit is electrically connected to the open drain output circuit; The output end of the open-drain output circuit is electrically connected to the enable pin of the load switch circuit; The input end of the load switch circuit is connected to the battery voltage power supply VBAT pin of the battery, and the output end of the load switch circuit is connected to the main system.

2. The combination key forced restart system according to claim 1, characterized in that: The AND gate circuit includes: a PMOS tube Q2, a resistor R4, an NMOS tube Q1, and a resistor R2; the PMOS tube Q2 and the resistor R4 are connected in series, the NMOS tube Q1 and the resistor R2 are connected in series, and the PMOS tube Q2 and the resistor R4 are connected in parallel with the NMOS tube Q1 and the resistor R2; The source of the PMOS tube Q2 is electrically connected to the output end of the PWRON key circuit; the gate of the NMOS tube Q1 is electrically connected to the output end of the RC low-level delay circuit.

3. The combination key forced restart system according to claim 1, characterized in that: The RC low-level delay circuit comprises: a resistor R1, a diode D2, and a capacitor C4, wherein the resistor R1 and the diode D2 are connected in parallel and then connected in series with the capacitor C4; The output end of the RESTORE button circuit is electrically connected to the input end of the RC low-level delay circuit.

4. The combination key forced restart system according to claim 1, characterized in that: The RC high level delay circuit comprises: a resistor R9, a diode D4, and a capacitor C7, wherein the resistor R9 and the diode D4 are connected in parallel and then connected in series with the capacitor C7; The input end of the RC high-level delay circuit is electrically connected to the output end of the AND gate circuit, and the output end of the RC high-level delay circuit is electrically connected to the input end of the open-drain output circuit.

5. The combination key forced restart system according to claim 1, characterized in that: The open-drain output circuit includes: a MOS tube Q3, a gate of the MOS tube Q3 is electrically connected to the output end of the RC high-level delay circuit, and a drain of the MOS tube Q3 is electrically connected to the enable pin of the load switch circuit.

6. The combination key forced restart system according to claim 1, characterized in that: The load switch circuit includes: a resistor R6, a resistor R7, a resistor R8, a capacitor C9, an NMOS tube Q5, and an NMOS tube Q4. The resistors R6, R7, and R8 are connected in parallel. The capacitor C9 is connected in parallel between the source and the gate of the NMOS tube Q5. The resistors R6 and R7 are connected between the source of the NMOS tube Q5 and the gate of the NMOS tube Q4. The resistor R8 is connected between the gate of the NMOS tube Q5 and the drain of the NMOS tube Q4. The drain of the NMOS tube Q5 is connected to the input voltage VSYS pin of the main system. The enable pin of the load switch circuit is the gate of the NMOS tube Q4.

7. The combination key forced restart system according to claim 1, characterized in that: The PWRON key circuit includes: a capacitor C5, a capacitor C6, a diode D3, a switch S2, and a diode D6. The capacitor C5, the capacitor C6, and the diode D3 are connected in parallel and then connected in series with the output end of the switch S2. The diode D6 is connected in series with the input end of the switch S2. The input end of the switch S2 is connected to the battery voltage power supply VBAT pin of the battery.

8. The combination key forced restart system according to claim 1, characterized in that: The RESTORE button circuit includes: a capacitor C1, a capacitor C2, a diode D1, a switch S1, and a diode D5. The capacitor C1, the capacitor C2, and the diode D1 are connected in parallel and then connected in series with the output end of the switch S1. The diode D5 is connected in series with the input end of the switch S1. The input end of the switch S1 is connected to the battery voltage power supply VBAT pin of the battery.

9. The combination key forced restart system according to claim 2, characterized in that: The drain of the PMOS tube Q2 of the AND gate circuit is used as an output terminal, and is connected to the resistor R4 and the ground GND.

10. The combination key forced restart system according to claim 2, characterized in that: The source of the NMOS transistor Q1 of the AND gate circuit is grounded GND.

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