High-speed bus signal processing circuit

Abstract

The utility model provides a high-speed bus signal processing circuit. According to the technical scheme, the high-speed bus signal processing circuit is characterized by comprising an airborne power supply conversion unit, a bus signal shunt isolation unit and an interface unit, the interface unit is configured to be electrically connected with the airborne power supply conversion unit and the bus signal shunt isolation unit, and the interface unit is also connected with an aviation platform direct current power supply and an aviation platform bus acquisition end; the airborne power supply conversion unit is configured to be electrically connected with the interface unit and the bus signal shunt isolation unit and is used for performing voltage conversion to obtain a target voltage; and the bus signal shunt isolation unit is configured to be electrically connected with the interface unit and the airborne power supply conversion unit, perform two-way shunt signal isolation on the high-speed bus signal, and output the high-speed bus signal after the two-way shunt signal isolation. The utility model provides a high-speed bus signal processing circuit suitable for complex conditions of an airborne platform, and shunting and isolation of a 10Mbp code rate RS-485 / 422 high-speed bus signal and transformation of a topological structure are realized.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to a high-speed bus signal processing circuit. Background Art

[0002] Currently, there are industrial-grade RS-485 / 422 bus hubs that can complete the branching, isolation and topology transformation of high-speed bus signals, but the bit rate is limited to 115200bps, and they are large in size and complex in power supply. They cannot meet the requirements of high-speed bus branching and topology transformation under the complex airborne conditions of aviation platforms.

[0003] The present application provides a high-speed bus signal processing circuit to solve the problems in the prior art of low signal code rate, large size, difficulty in integrating with airborne equipment, and complex power supply of existing RS-485 / 422 bus hubs. Utility Model Content

[0004] To achieve the above objectives, the present application provides a high-speed bus signal processing circuit.

[0005] The present application provides a high-speed bus signal processing circuit, comprising: an onboard power conversion unit, a bus signal shunt isolation unit and an interface unit, wherein the onboard power conversion unit, the bus signal shunt isolation unit and the interface unit are all arranged on a circuit board;

[0006] An interface unit is configured to be electrically connected to the airborne power conversion unit and the bus signal branch isolation unit, and the interface unit is also connected to the aviation platform DC power supply and the aviation platform bus acquisition terminal;

[0007] an airborne power conversion unit, configured to be electrically connected to the interface unit and the bus signal shunt isolation unit, for converting the voltage of the aviation platform DC power supply from the interface unit to obtain a target voltage, and outputting the target voltage to the bus signal shunt isolation unit;

[0008] The bus signal branch isolation unit is configured to be electrically connected to the interface unit and the airborne power conversion unit, and is used to receive the target voltage from the airborne power conversion unit, and to isolate the high-speed bus signal from the aviation platform bus acquisition end of the interface unit into two branches, and output the high-speed bus signal after the two branches are isolated.

[0009] Preferably, the interface unit includes a first interface J1, a second interface J2, a third interface J3, a fourth interface J4, a fifth interface J5, a sixth interface J6, a seventh interface J7, and an eighth interface J8;

[0010] The first interface J1 and the second interface J2 are electrically connected to the onboard power conversion unit, and the third interface J3, the fourth interface J4, the fifth interface J5, the sixth interface J6, the seventh interface J7, and the eighth interface J8 are electrically connected to the bus signal branch isolation unit;

[0011] The fifth interface J5 and the sixth interface J6 are respectively set as backup interfaces of the third interface J3 and the fourth interface J4.

[0012] Preferably, the airborne power conversion unit includes a resettable fuse F1, a first chip U1, a second chip U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a transient suppression diode D1, a light emitting diode D2, a transient suppression diode D3, and a transistor Q1;

[0013] The first pin ends of the first interface J1 and the second interface J2 are both electrically connected to the resettable fuse F1, the second pin ends of the first interface J1 and the second interface J2 are both electrically connected to the fourth pin end of the transistor Q1, the second pin ends of the first interface J1 and the second interface J2 are both electrically connected to one end of the transient suppression diode D1, the other end of the transient suppression diode D1 is electrically connected to the resettable fuse F1, the third pin end of the transistor Q1 is electrically connected to the fifth resistor R5, the transient suppression diode D3 and the seventh capacitor C7, the first pin end of the transistor Q1 is electrically connected to the fifth resistor R5, the transient suppression diode D3 and the other end of the seventh capacitor C7 and the fourth resistor R4, the fifth resistor R5, the transient suppression diode D3 and the seventh capacitor C7 are connected in parallel, one end of the seventh capacitor C7 electrically connected to the third pin end of the transistor Q1 is grounded, and the second resistor R2, the third resistor R3 and the fourth resistor R4 are connected in series;

[0014] The second resistor R2 is electrically connected to the first capacitor C1 and the third pin end of the first chip U1, the other end of the first capacitor C1 is grounded, the first pin end of the first chip U1 is electrically connected to the sixth resistor R6 and the fifth capacitor C5, the sixth resistor R6 and the fifth capacitor C5 are connected in parallel, the other ends of the sixth resistor R6 and the fifth capacitor C5 are both grounded, the second pin end of the first chip U1 is electrically connected to the fourth pin end of the first chip U1 and the second capacitor C2, and the other end of the second capacitor C2 is grounded;

[0015] The second pin end of the first chip U1 is electrically connected to the third capacitor C3 and the third pin end of the second chip U2, and the other end of the third capacitor C3 is grounded. The first pin end of the second chip U2 is electrically connected to the seventh resistor R7 and the sixth capacitor C6. The seventh resistor R7 and the sixth capacitor C6 are connected in parallel, and the other ends of the seventh resistor R7 and the sixth capacitor C6 are both grounded. The second pin end of the second chip U2 is electrically connected to the fourth pin end of the second chip U2 and the fourth capacitor C4, and the other end of the fourth capacitor C4 is grounded.

[0016] Preferably, the second pin end of the second chip U2 is electrically connected to the first resistor R1, the other end of the first resistor R1 is electrically connected to the light emitting diode D2, and the other end of the light emitting diode D2 is grounded.

[0017] Preferably, the bus signal branch isolation unit includes a third chip U3, a fourth chip U4, an eighth resistor R8, a tenth resistor R10, an eighth capacitor C8, and a ninth capacitor C9;

[0018] The second pin end of the second chip U2 is electrically connected to the eighth capacitor C8 and the first pin end of the third chip U3, the other end of the eighth capacitor C8 is grounded, the second pin end of the third chip U3 is electrically connected to the third pin end of the third chip U3, the fourth pin end of the third chip U3 is grounded, the fifth pin end of the third chip U3 is electrically connected to the first pin end of the eighth interface J8, the sixth pin end of the third chip U3 is electrically connected to the second pin end of the eighth interface J8, the seventh pin end of the third chip U3 is electrically connected to the fifth pin end of the third interface J3 and the fifth pin end of the fourth interface J4, the eighth pin end of the third chip U3 is electrically connected to the fourth pin end of the third interface J3 and the fourth pin end of the fourth interface J4, and the eighth resistor R8 is electrically connected between the seventh pin end and the eighth pin end of the third chip U3;

[0019] The second pin end of the second chip U2 is electrically connected to the ninth capacitor C9 and the first pin end of the fourth chip U4, the other end of the ninth capacitor C9 is grounded, the second pin end of the fourth chip U4 is electrically connected to the third pin end of the fourth chip U4, the fourth pin end of the fourth chip U4 is grounded, the fifth pin end of the fourth chip U4 is electrically connected to the first pin end of the seventh interface J7, the sixth pin end of the fourth chip U4 is electrically connected to the second pin end of the seventh interface J7, the seventh pin end of the fourth chip U4 is electrically connected to the second pin end of the third interface J3 and the second pin end of the fourth interface J4, the eighth pin end of the fourth chip U4 is electrically connected to the first pin end of the third interface J3 and the first pin end of the fourth interface J4, and the tenth resistor R10 is electrically connected between the seventh pin end and the eighth pin end of the fourth chip U4;

[0020] The third pin ends of the third interface J3 and the fourth interface J4 are both grounded, and the third pin end of the eighth interface J8 is grounded.

[0021] In summary, the beneficial effects of this application are:

[0022] 1. The aviation platform DC power supply inputs a 28V DC voltage to the airborne power conversion unit through the interface unit. The airborne power conversion unit converts the 28V DC voltage into a 3.3V DC voltage through two LDO voltage conversions, and transmits the 3.3V DC voltage to the bus signal branch isolation unit for the bus signal branch isolation unit to work; the two LDO voltage conversions effectively improve the heat dissipation problem during the step-down process. The airborne power conversion unit is also designed with an overvoltage protection circuit and has an overvoltage protection function.

[0023] 2. The high-speed bus signal is introduced into the seventh pin and the eighth pin of the third chip and the fourth chip through the third interface J3 and the fourth interface J4, and the driver in the third chip and the fourth chip determines the high and low levels of the seventh pin and the eighth pin, and outputs the logic level 0 / 1 through the second pin of the third chip and the fourth chip. After the logic level 0 / 1 output from the second pin is branched and input to the third pin of the third chip and the fourth chip according to actual needs, the driver in the third chip and the fourth chip converts the 0 / 1 logic level into a positive and negative differential signal, and the high-speed bus signal after branching, isolation and driving is output from the fifth pin and the sixth pin of the third chip and the fourth chip.

[0024] 3. The technical solution of the present application provides a high-speed bus branching solution suitable for complex conditions on airborne platforms, which realizes the branching, isolation and topology structure transformation of 10Mbps RS-485 / 422 high-speed bus signals. The technical solution of the present application is presented in the form of a single circuit board, which can be integrated with airborne equipment, and is flexible to deploy and save space. The power supply adopts the universal 28V DC power of the aviation platform, which has good applicability and meets the requirements of aviation platform testing for branching, isolation and topology structure changes of the airborne high-speed bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, some of the drawings in the embodiments of the present application will be briefly described below. It should be understood that the following drawings only show some embodiments of the present application and therefore should not be considered as limiting the scope of the present application.

[0026] Figure 1 A schematic diagram of the structure of a high-speed bus signal processing circuit provided in an embodiment of the present application;

[0027] Figure 2A schematic diagram of the structure of an interface unit of a high-speed bus signal processing circuit provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of the structure of an onboard power conversion unit of a high-speed bus signal processing circuit provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of the structure of a bus signal branch isolation unit of a high-speed bus signal processing circuit provided in an embodiment of the present application.

[0030] In the figure: 1. Interface unit; 2. Airborne power conversion unit; 3. Bus signal branch isolation unit. DETAILED DESCRIPTION

[0031] Below is a combination of the embodiments and Figures 1 to 4 The present application is further described in detail, but the implementation methods of the present application are not limited thereto.

[0032] Reference Figure 1 As shown, it is a structural schematic diagram of a high-speed bus signal processing circuit provided in an embodiment of the present application. In the embodiment of the present application, the application scenario is to solve the problems of low signal code rate, large size, difficulty in integration with airborne equipment, and complex power supply in the existing RS-485 / 422 bus hub. The difference is that in the prior art, there is an industrial-grade RS-485 / 422 bus hub that can complete the branching, isolation and topological structure transformation of the high-speed bus signal, but the code rate is limited to 115200bps, and the size is large, the power supply is complex, and it does not meet the requirements of the branching and topological structure transformation of the high-speed bus under the complex airborne conditions of the aviation platform. The present application provides a high-speed bus branching solution suitable for the complex conditions of the airborne platform, realizes the branching, isolation and topological structure transformation of the RS-485 / 422 high-speed bus signal with a code rate of 10Mbps, and the solution is presented in the form of a single circuit board, which can be integrated with the airborne equipment, has flexible deployment and saves space, and uses the general 28V DC power of the aviation platform for power supply, which has good applicability and meets the requirements of the aviation platform test for the branching, isolation and topological structure changes of the airborne high-speed bus.

[0033] Reference Figure 1 , a high-speed bus signal processing circuit, comprising: an interface unit 1, an onboard power conversion unit 2 and a bus signal shunt isolation unit 3, wherein the interface unit 1, the onboard power conversion unit 2 and the bus signal shunt isolation unit 3 are all arranged on a circuit board;

[0034] The interface unit 1 is configured to be electrically connected to the airborne power conversion unit 2 and the bus signal branch isolation unit 3, and the interface unit 1 is also electrically connected to the aviation platform DC power supply and the aviation platform bus acquisition terminal;

[0035] The airborne power conversion unit 2 is configured to be electrically connected to the interface unit 1 and the bus signal shunt isolation unit 3, and is used to convert the voltage of the aviation platform DC power supply from the interface unit 1 to obtain a target voltage, and output the target voltage to the bus signal shunt isolation unit 3;

[0036] The bus signal branch isolation unit 3 is configured to be electrically connected to the interface unit 1 and the airborne power conversion unit 2, and is used to receive the target voltage from the airborne power conversion unit 2, and to isolate the high-speed bus signal from the aviation platform bus acquisition end of the interface unit 1 into two branches, and output the high-speed bus signal after the two branches are isolated.

[0037] In some embodiments, the circuit board is configured as an RS485 circuit board, the aviation platform DC power supply adopts the aviation platform's universal 28V DC power, the target voltage is 3.3V DC voltage, and the aviation platform bus acquisition terminal is used to transmit high-speed bus signals to the interface unit 1.

[0038] Reference Figure 1 and Figure 2 , the interface unit 1 includes a first interface J1, a second interface J2, a third interface J3, a fourth interface J4, a fifth interface J5, a sixth interface J6, a seventh interface J7, and an eighth interface J8;

[0039] The first interface J1 and the second interface J2 are electrically connected to the onboard power conversion unit 2, and the third interface J3, the fourth interface J4, the seventh interface J7, and the eighth interface J8 are electrically connected to the bus signal branch isolation unit 3;

[0040] The fifth interface J5 and the sixth interface J6 are respectively set as backup interfaces of the third interface J3 and the fourth interface J4.

[0041] In some embodiments, the first interface J1 and the second interface J2 are set as power interfaces, the third interface J3 and the fourth interface J4 are set as input / output interfaces of the RS485 circuit board, the fifth interface J5 and the sixth interface J6 are set as backup input / output interfaces of the RS485 circuit board, and the seventh interface J7 and the eighth interface J8 are set as relay output interfaces of the RS485 circuit board.

[0042] Reference Figure 2 and Figure 3 The onboard power conversion unit 2 includes a resettable fuse F1, a first chip U1, a second chip U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a transient suppression diode D1, a light emitting diode D2, a transient suppression diode D3, and a transistor Q1;

[0043] The first pin ends of the first interface J1 and the second interface J2 are both electrically connected to the resettable fuse F1, the second pin ends of the first interface J1 and the second interface J2 are both electrically connected to the fourth pin end of the transistor Q1, the second pin ends of the first interface J1 and the second interface J2 are both electrically connected to one end of the transient suppression diode D1, the other end of the transient suppression diode D1 is electrically connected to the resettable fuse F1, the third pin end of the transistor Q1 is electrically connected to the fifth resistor R5, the transient suppression diode D3 and the seventh capacitor C7, the first pin end of the transistor Q1 is electrically connected to the fifth resistor R5, the transient suppression diode D3 and the other end of the seventh capacitor C7 and the fourth resistor R4, the fifth resistor R5, the transient suppression diode D3 and the seventh capacitor C7 are connected in parallel, one end of the seventh capacitor C7 electrically connected to the third pin end of the transistor Q1 is grounded, and the second resistor R2, the third resistor R3 and the fourth resistor R4 are connected in series;

[0044] The second resistor R2 is electrically connected to the first capacitor C1 and the third pin end of the first chip U1, the other end of the first capacitor C1 is grounded, the first pin end of the first chip U1 is electrically connected to the sixth resistor R6 and the fifth capacitor C5, the sixth resistor R6 and the fifth capacitor C5 are connected in parallel, the other ends of the sixth resistor R6 and the fifth capacitor C5 are both grounded, the second pin end of the first chip U1 is electrically connected to the fourth pin end of the first chip U1 and the second capacitor C2, and the other end of the second capacitor C2 is grounded;

[0045] The second pin end of the first chip U1 is electrically connected to the third capacitor C3 and the third pin end of the second chip U2, and the other end of the third capacitor C3 is grounded. The first pin end of the second chip U2 is electrically connected to the seventh resistor R7 and the sixth capacitor C6. The seventh resistor R7 and the sixth capacitor C6 are connected in parallel, and the other ends of the seventh resistor R7 and the sixth capacitor C6 are both grounded. The second pin end of the second chip U2 is electrically connected to the fourth pin end of the second chip U2 and the fourth capacitor C4, and the other end of the fourth capacitor C4 is grounded.

[0046] In some embodiments, the 28V DC power supply of the aviation platform inputs the 28V DC voltage to the airborne power conversion unit 2 through the interface unit 1, and the airborne power conversion unit 2 converts the 28V DC voltage into a 3.3V DC voltage through two LDO voltage conversions, and transmits the 3.3V DC voltage to the bus signal branch isolation unit 3, so that the bus signal branch isolation unit 3 can work;

[0047] In addition, the two LDO voltage conversions effectively improve the heat dissipation problem during the step-down process. The airborne power conversion unit 2 is also designed with an overvoltage protection circuit and has an overvoltage protection function. In addition, the airborne power conversion unit 2 can be changed to a DC filter + airborne power conversion unit 2 mode. The 28V DC power supply of the aviation platform inputs the 28V DC voltage to the DC filter through the interface unit 1. The 28V DC voltage first passes through the DC filter and is then transmitted to the airborne power conversion unit 2 for two DC-DC conversions to obtain the required 3.3V power supply.

[0048] Reference Figure 3 The second pin end of the second chip U2 is electrically connected to the first resistor R1, the other end of the first resistor R1 is electrically connected to the light emitting diode D2, and the other end of the light emitting diode D2 is grounded.

[0049] In some embodiments, the light emitting diode D2 is configured as a green LED indicator light for indicating the power supply working status of the RS485 circuit board.

[0050] Reference Figure 2 , Figure 3 and Figure 4 The bus signal branch isolation unit 3 includes a third chip U3, a fourth chip U4, an eighth resistor R8, a tenth resistor R10, an eighth capacitor C8, and a ninth capacitor C9;

[0051] The second pin end of the second chip U2 is electrically connected to the eighth capacitor C8 and the first pin end of the third chip U3, the other end of the eighth capacitor C8 is grounded, the second pin end of the third chip U3 is electrically connected to the third pin end of the third chip U3, the fourth pin end of the third chip U3 is grounded, the fifth pin end of the third chip U3 is electrically connected to the first pin end of the eighth interface J8, the sixth pin end of the third chip U3 is electrically connected to the second pin end of the eighth interface J8, the seventh pin end of the third chip U3 is electrically connected to the fifth pin end of the third interface J3 and the fifth pin end of the fourth interface J4, the eighth pin end of the third chip U3 is electrically connected to the fourth pin end of the third interface J3 and the fourth pin end of the fourth interface J4, and the eighth resistor R8 is electrically connected between the seventh pin end and the eighth pin end of the third chip U3;

[0052] The second pin end of the second chip U2 is electrically connected to the ninth capacitor C9 and the first pin end of the fourth chip U4, the other end of the ninth capacitor C9 is grounded, the second pin end of the fourth chip U4 is electrically connected to the third pin end of the fourth chip U4, the fourth pin end of the fourth chip U4 is grounded, the fifth pin end of the fourth chip U4 is electrically connected to the first pin end of the seventh interface J7, the sixth pin end of the fourth chip U4 is electrically connected to the second pin end of the seventh interface J7, the seventh pin end of the fourth chip U4 is electrically connected to the second pin end of the third interface J3 and the second pin end of the fourth interface J4, the eighth pin end of the fourth chip U4 is electrically connected to the first pin end of the third interface J3 and the first pin end of the fourth interface J4, and the tenth resistor R10 is electrically connected between the seventh pin end and the eighth pin end of the fourth chip U4;

[0053] The third pin ends of the third interface J3 and the fourth interface J4 are both grounded, and the third pin end of the eighth interface J8 is grounded.

[0054] In some embodiments, the third chip U3 and the fourth chip U4 are configured as driver chips, which contain two drivers, that is, the third chip U3 and the fourth chip U4 each contain two drivers, and the driver chip is MaximMAX3490EESA, supporting a maximum rate of 10Mbps. The A and B pins of the driver chip correspond to the eighth pin end and the seventh pin end of the third chip U3 and the fourth chip U4, respectively; the RO and DI pins of the driver chip correspond to the second pin end and the third pin end of the third chip U3 and the fourth chip U4, respectively; the Y and Z pins of the driver chip correspond to the fifth pin end and the sixth pin end of the third chip U3 and the fourth chip U4, respectively; the high-speed bus signal is introduced into the A and B pins of the driver chip through the third interface J3 and the fourth interface J4, and the driver in the driver chip determines the high and low levels of the A and B pins, and outputs the logic level 0 / 1 through the R0 pin. After the logic level 0 / 1 output by the driver chip is input to the DI pin of the driver in the driver chip according to actual needs, the driver converts the 0 / 1 logic level into a positive and negative differential signal, and the high-speed bus signal after branching, isolation and driving is output from the Y and Z pins. Among them, the third chip U3 is used to output the high-speed bus clock signal after two-way branching and isolation, and the fourth chip U4 is used to output the high-speed bus data signal after two-way branching and isolation.

[0055] In some embodiments, three socket cables need to be made and welded to the RS485 circuit board before use, and the connection between the maintenance socket and the RS485 circuit board is realized by connecting the interface unit 1 with the socket cable, wherein the first external cable is set as a maintenance socket cable, which is used to connect the maintenance socket connected to the recorder and data tube system signals; the second external cable is set as a maintenance socket cable, which is used to connect the maintenance socket connected to the first-line equipment signal; the third external cable is set as a flight parameter acquisition equipment socket cable, which is used to connect the FXSP-7AXP1 socket; in addition, four non-metallized holes are set on the right side of the circuit board for cable tying and fixing.

[0056] The implementation principle of a high-speed bus signal processing circuit in an embodiment of the present application is as follows: the present application is electrically connected to an airborne power conversion unit 2 and a bus signal shunt isolation unit 3 through an interface unit 1, and is connected to an aviation platform DC power supply and an aviation platform bus acquisition terminal through the interface unit 1; the airborne power conversion unit 2 is electrically connected to the interface unit 1 and the bus signal shunt isolation unit 3, the voltage of the aviation platform DC power supply from the interface unit 1 is converted to a target voltage, and the target voltage is output to the bus signal shunt isolation unit 3; the bus signal shunt isolation unit 3 is electrically connected to the interface unit 1 and the airborne power conversion unit 2, the target voltage from the airborne power conversion unit 2 is received, and the high-speed bus signal from the aviation platform bus acquisition terminal of the interface unit 1 is isolated from two shunt signals, and the high-speed bus signal after the two shunt isolation is output.

[0057] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A high-speed bus signal processing circuit, characterized in that: include: An interface unit (1), an onboard power conversion unit (2) and a bus signal shunt isolation unit (3), wherein the interface unit (1), the onboard power conversion unit (2) and the bus signal shunt isolation unit (3) are all arranged on a circuit board; The interface unit (1) is configured to be electrically connected to the airborne power conversion unit (2) and the bus signal branch isolation unit (3), and the interface unit (1) is also connected to the aviation platform DC power supply and the aviation platform bus acquisition terminal; The onboard power conversion unit (2) is configured to be electrically connected to the interface unit (1) and the bus signal shunt isolation unit (3), and is used to convert the voltage of the aviation platform DC power supply from the interface unit (1) into a target voltage, and output the target voltage to the bus signal shunt isolation unit (3); The bus signal branch isolation unit (3) is configured to be electrically connected to the interface unit (1) and the airborne power conversion unit (2), and is used to receive the target voltage from the airborne power conversion unit (2), and to isolate the high-speed bus signal from the aviation platform bus acquisition end of the interface unit (1) into two branch signals, and output the high-speed bus signal after the two branch isolations.

2. A high-speed bus signal processing circuit according to claim 1, characterized in that: The interface unit (1) comprises a first interface J1, a second interface J2, a third interface J3, a fourth interface J4, a fifth interface J5, a sixth interface J6, a seventh interface J7, and an eighth interface J8; The first interface J1 and the second interface J2 are electrically connected to the onboard power conversion unit (2), and the third interface J3, the fourth interface J4, the fifth interface J5, the sixth interface J6, the seventh interface J7, and the eighth interface J8 are electrically connected to the bus signal branch isolation unit (3); The fifth interface J5 and the sixth interface J6 are respectively set as backup interfaces of the third interface J3 and the fourth interface J4.

3. A high-speed bus signal processing circuit according to claim 2, characterized in that: The onboard power conversion unit (2) comprises a resettable fuse F1, a first chip U1, a second chip U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a transient suppression diode D1, a light emitting diode D2, a transient suppression diode D3, and a transistor Q1; The first pin ends of the first interface J1 and the second interface J2 are both electrically connected to the resettable fuse F1, the second pin ends of the first interface J1 and the second interface J2 are both electrically connected to the fourth pin end of the transistor Q1, the second pin ends of the first interface J1 and the second interface J2 are both electrically connected to one end of the transient suppression diode D1, the other end of the transient suppression diode D1 is electrically connected to the resettable fuse F1, the third pin end of the transistor Q1 is electrically connected to the fifth resistor R5, the transient suppression diode D3 and the seventh capacitor C7, the first pin end of the transistor Q1 is electrically connected to the fifth resistor R5, the transient suppression diode D3 and the other end of the seventh capacitor C7 and the fourth resistor R4, the fifth resistor R5, the transient suppression diode D3 and the seventh capacitor C7 are connected in parallel, one end of the seventh capacitor C7 electrically connected to the third pin end of the transistor Q1 is grounded, and the second resistor R2, the third resistor R3 and the fourth resistor R4 are connected in series; The second resistor R2 is electrically connected to the first capacitor C1 and the third pin end of the first chip U1, the other end of the first capacitor C1 is grounded, the first pin end of the first chip U1 is electrically connected to the sixth resistor R6 and the fifth capacitor C5, the sixth resistor R6 and the fifth capacitor C5 are connected in parallel, the other ends of the sixth resistor R6 and the fifth capacitor C5 are both grounded, the second pin end of the first chip U1 is electrically connected to the fourth pin end of the first chip U1 and the second capacitor C2, and the other end of the second capacitor C2 is grounded; The second pin end of the first chip U1 is electrically connected to the third capacitor C3 and the third pin end of the second chip U2, and the other end of the third capacitor C3 is grounded. The first pin end of the second chip U2 is electrically connected to the seventh resistor R7 and the sixth capacitor C6. The seventh resistor R7 and the sixth capacitor C6 are connected in parallel, and the other ends of the seventh resistor R7 and the sixth capacitor C6 are both grounded. The second pin end of the second chip U2 is electrically connected to the fourth pin end of the second chip U2 and the fourth capacitor C4, and the other end of the fourth capacitor C4 is grounded.

4. The high-speed bus signal processing circuit according to claim 3, characterized in that: The second pin end of the second chip U2 is electrically connected to the first resistor R1 , the other end of the first resistor R1 is electrically connected to the light emitting diode D2 , and the other end of the light emitting diode D2 is grounded.

5. A high-speed bus signal processing circuit according to claim 4, characterized in that: The bus signal branching isolation unit (3) comprises a third chip U3, a fourth chip U4, an eighth resistor R8, a tenth resistor R10, an eighth capacitor C8, and a ninth capacitor C9; The second pin end of the second chip U2 is electrically connected to the eighth capacitor C8 and the first pin end of the third chip U3, the other end of the eighth capacitor C8 is grounded, the second pin end of the third chip U3 is electrically connected to the third pin end of the third chip U3, the fourth pin end of the third chip U3 is grounded, the fifth pin end of the third chip U3 is electrically connected to the first pin end of the eighth interface J8, the sixth pin end of the third chip U3 is electrically connected to the second pin end of the eighth interface J8, the seventh pin end of the third chip U3 is electrically connected to the fifth pin end of the third interface J3 and the fifth pin end of the fourth interface J4, the eighth pin end of the third chip U3 is electrically connected to the fourth pin end of the third interface J3 and the fourth pin end of the fourth interface J4, and the eighth resistor R8 is electrically connected between the seventh pin end and the eighth pin end of the third chip U3; The second pin end of the second chip U2 is electrically connected to the ninth capacitor C9 and the first pin end of the fourth chip U4, the other end of the ninth capacitor C9 is grounded, the second pin end of the fourth chip U4 is electrically connected to the third pin end of the fourth chip U4, the fourth pin end of the fourth chip U4 is grounded, the fifth pin end of the fourth chip U4 is electrically connected to the first pin end of the seventh interface J7, the sixth pin end of the fourth chip U4 is electrically connected to the second pin end of the seventh interface J7, the seventh pin end of the fourth chip U4 is electrically connected to the second pin end of the third interface J3 and the second pin end of the fourth interface J4, the eighth pin end of the fourth chip U4 is electrically connected to the first pin end of the third interface J3 and the first pin end of the fourth interface J4, and the tenth resistor R10 is electrically connected between the seventh pin end and the eighth pin end of the fourth chip U4; The third pin ends of the third interface J3 and the fourth interface J4 are both grounded, and the third pin end of the eighth interface J8 is grounded.

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