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Common cache control device, common cache control method, and integrated circuit

A technology of control device and shared cache, applied in memory system, data processing power supply, electrical digital data processing and other directions, can solve the problems of unutilized area, ineffective use of area, waste and other problems

Inactive Publication Date: 2010-02-17
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, in the prior art described above, it is necessary to allocate an area of ​​an available cache storage device to each operating system in advance.
Therefore, there is a problem that even when one of the operating systems transitions to a sleep state, the other operating systems cannot effectively use the area in the cache storage device used by the operating system.
That is, depending on the execution state of the operating system such as low power consumption mode and sleep mode, the allocated area may not be used, resulting in wasteful

Method used

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  • Common cache control device, common cache control method, and integrated circuit
  • Common cache control device, common cache control method, and integrated circuit
  • Common cache control device, common cache control method, and integrated circuit

Examples

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Embodiment 1

[0033] figure 1 is a diagram showing the configuration of a computer system in Embodiment 1 of the present invention. The computer system 100 is a virtual computer system that runs multiple operating systems on one processor. The computer system 100 includes: an internal bus 110 , a cache storage device 111 , a processor 112 , a memory 113 , peripheral modules 114 , and a status register (status register) 115 .

[0034] The cache storage device 111 , the memory 113 , the peripheral module group 114 , and the status register 115 are connected to the internal bus 110 , respectively. Due to the high integration of LSIs in recent years, it is also possible to mount a plurality of circuits constituting the computer system 100 in one system LSI. It can also be provided by a different system LSI. In addition, in figure 1 Among them, although the status register 115 is connected to the internal bus 110, it may be directly connected to the processor 112.

[0035] The processor 112...

Embodiment 2

[0106] Figure 6 is a diagram showing the configuration of a computer system in Embodiment 2 of the present invention. Computer system 500 is a multi-processor system in which multiple processors share memory and cache storage.

[0107] Computer system 500 includes: internal bus 110, peripheral module group 114, status register 115, multiple processors (the first processor 502 and the second processor 503), multiple primary cache storage devices (the first primary cache storage device 504 and the second level cache storage device 505), the second level cache storage device 501, and the memory 506. The structural elements of the internal bus 110, the peripheral module group 114, and the status register 115 are the same as figure 1 The structural elements described in are the same.

[0108] Due to the high integration of LSIs in recent years, it is also possible to mount a plurality of circuits constituting the computer system 500 in one system LSI. They are provided by diff...

Embodiment 3

[0153] Figure 9 is a diagram showing the configuration of a computer system in Embodiment 3 of the present invention. Computer system 800 is a virtual computer system running multiple operating systems on one processor. The computer system 800 includes: an internal bus 110 , a cache storage device 801 , a processor 112 , a memory 813 , peripheral modules 114 , and a status register 115 . The cache storage device 801 , the memory 813 , the peripheral module group 114 , and the status register 115 are connected to the internal bus 110 , respectively. The structural elements of the internal bus 110, the processor 112, the peripheral module group 114, and the status register 115 are the same as figure 1 The structural elements described in are the same.

[0154] The memory 813 includes first to nth tasks 823 to 827 , first and second operating systems 821 and 822 , and a hypervisor 820 . figure 1 The memory 113 includes three operating systems, as opposed to, Figure 9 The m...

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PUM

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Abstract

A common cache control device includes a monitoring unit (139), a cache entry setting unit (141), and a replacement object selection unit (136). The monitoring unit (139) monitors a processor operating a plurality of operating systems or a power control command for controlling power supplied to a plurality of processors. When selecting a cache entry to be replaced from cache entries constituting a cache storage device (111), the cache entry setting unit (141) uses the plurality of operating systems or processor execution states modified according to the power control command so as to set the operating system which has executed the control command or the cache entry which has been used by the processor, to the state used in the past. The replacement object selection unit (136) selects the cache entry which has been set to the state used in the past, as the cache entry to be replaced. Thus, a plurality of operating systems or a plurality of processors can effectively use a single cache storage device.

Description

technical field [0001] The invention relates to a shared cache control device, a shared cache control method and an integrated circuit for effectively utilizing cache entries of a cache storage device shared by multiple operating systems or multiple processors. Background technique [0002] As a technical trend of system LSIs in recent years, a multi-core structure in which a plurality of processor cores are mounted is prevailing. In particular, in LSIs for embedded systems, it may be more advantageous to install multiple processor cores of a medium-sized or smaller than one ultra-high-speed processor core from the standpoint of cost and power consumption. In such embedded system LSIs, hierarchical cache storage devices have been gradually adopted in recent years. However, the technique of maintaining data coherency (coherency) among the cache storage devices mounted on the respective processor cores is very complicated. Therefore, in an embedded-oriented system LSI, even ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/12G06F12/08G06F12/10
CPCG06F12/084G06F1/32G06F1/3203G06F1/3246
Inventor 齐藤雅彦
Owner PANASONIC CORP