A sample-and-hold amplifier
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- NXP BV
- Publication Date
- 2011-09-21
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
technical field
[0001] The present invention relates to the field of sample-and-hold amplifiers, and in particular but not exclusively, to a sample-and-hold amplifier having a hold phase of operation and a sample phase of operation, which sample-and-hold amplifier may be used with a time-interleaved analog-to-digital converter. Background technique
[0002] For high-resolution analog-to-digital converters (ADCs), higher sampling rates are the trend. Time interleaving is a common technique to increase the sampling rate, although, for high-resolution ADCs, time interleaving of the front-end sample-and-hold amplifier (SHA) may not be practical due to strict time alignment requirements. "A CMOS 33-mW100-MHz 80-dB SFDR Sample-and-Hold Amplifier" by C-C Hsu and Wu J-T (VLSI CircuitsSymp.Dig., pp. 263-264, 2003) discloses a high-rate High-resolution sample-and-hold amplifier (SHA).
[0003] "A CMOS 15-bit125-MS / s Time-Interleaved ADC With Digital Background Calibration" by Z-M Le...