Method for forming side wall and storage unit formed thereby

Abstract

The invention provides a method for forming a side wall. The method comprises the following steps of: forming the side wall of a gate structure on a semiconductor substrate having the gate structure and a source drain pre-preparation area; etching the formed side wall to form below wide on narrow shape side wall; and heavy doping the source drain pre-preparation area by predetermined ions to form a source drain area and so that the predetermined ions for heavy doping are permeated to the bottom of the side wall. When the method provided by the invention is used in the side wall etching process, the distribution of source drain heavy doping injection ions is adjusted by adjusting appearance of the etched side wall, therefore, the longitudinal electric field in a drain terminal channel can be improved, the substrate current is increased, the writing speed of a floating body effect storage unit is improved, and serious short-channel effect can not be generated so that the performance of devices can be kept.

Description

Technical field

[0001] The present invention relates to the field of semiconductor preparation, in particular to an etching process for forming sidewalls, and the structure of a floating body effect memory cell (Floating Body Cell, FBC) formed by the method. Background technique

[0002] The development of embedded dynamic storage technology has made large-capacity DRAM very popular in the current system-on-chip (SOC). The large-capacity embedded dynamic memory (eDRAM) brings various benefits to the SOC, such as improved bandwidth and reduced power consumption, which can only be realized through the use of embedded technology. In addition to transistors, each memory cell of the traditional embedded dynamic memory (eDRAM) also requires a deep trench capacitor structure. The deep trench of the capacitor makes the height of the memory cell much larger than its width, which makes the manufacturing process difficult. Its manufacturing process is very incompatible with the CMOS VLSI p...

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