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Configurable D latch for chaos computing

A latch and chaotic technology, applied in the direction of electrical components, logic circuits, pulse technology, etc., can solve the problems that cannot be rewired or configured, the circuit structure cannot be rewired or configured, and the function cannot be changed.

Inactive Publication Date: 2014-07-16
SOUTH CHINA UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, traditional D-Latches are static in nature and cannot be rewired or configured during operation.
For example, once a hardware component such as an 8-bit D-type latch is successfully manufactured, its function cannot be changed because its circuit structure cannot be rewired or configured.

Method used

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  • Configurable D latch for chaos computing
  • Configurable D latch for chaos computing
  • Configurable D latch for chaos computing

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0024] Such as figure 1 Shown is a configurable D-latch used for chaotic calculations, including a two-to-one data gating device and a configurable logic gate;

[0025] Said one-of-two data strobe: the input signal is respectively the first input signal and the feedback signal, the control signal is the strobe signal, and the output signal is the gated signal;

[0026] The configurable logic gate: the input signals are the gated signal and the second input signal respectively, the control signals are the control signal Ctra and the control signal Ctrb respectively, and the output signals are the output signal Vout and the output signal NVout respectively;

[0027] The output signal Vout is the input signal of the one-of-two data gate, that is, the feedback signal.

[0028] Such as figure 2 Shown is a block diagram of a configurable logic gate,

[0029] The configurable logic gates include a CMOS NAND gate, a CMOS NOR gate, three CMOS NOT gates, a CMOS XOR gate, a pseudo NM...

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Abstract

The invention discloses a configurable D latch for chaos computing. The configurable D latch for the chaos computing comprises an alternative data strobe device and a configurable logic gate. According to the alternative data strobe device, input signals are a first input signal and a feedback signal respectively, a control signal is a strobe signal, and an output signal is a signal after strobe. According to the configurable logic gate, input signals are a signal after strobe and a second input signal, control signals are a control signal Ctra and a control signal Ctrb respectively, and output signals are an output signal Vout and an out signal NVout. The output signal Vout of the configurable logic gate is the input signal, namely the feedback signal of the alternative data strobe device. By configuration of the two control signals and the other input signal of the configurable logic gate, the D latch can achieve different functions so as to achieve dynamic computing.

Description

technical field [0001] The invention relates to the field of electronic technology and dynamic calculation, in particular to a configurable D latch used for chaotic calculation. Background technique [0002] A latch is a memory cell circuit sensitive to pulse levels, which can change state under the action of a specific input pulse level. Usually, the pulse level has only two states, high and low. When the pulse level is high and effective, if the input pulse level is high, then the output of the latch will follow the input of the latch, if the input pulse level is low, then the output of the latch will remain unchanged. On the contrary, when the pulse level is low effective, if the input pulse level is low, then the output of the latch will follow the input of the latch and change, if the input pulse level is high, then the latch The output will remain unchanged. [0003] The latch is the main module of the arithmetic unit in the microprocessor, and the D latch is its t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0948
Inventor 姜小波黎红源袁群
Owner SOUTH CHINA UNIV OF TECH
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