Reusable logical gate of mixed structure of MOS transistor and single-electron transistor

Abstract

The invention provides a reusable logical gate based on an SET/MOS mixed structure according to a coulomb blockade oscillation effect and multiple-grid input features of the mixed structure of a single-electron transistor and an MOS transistor of a novel nano-electronical appliance. Through bias of an input end and a control end, all two-input logical functions of OR, NOR, AND, NAND, XOR and XNOR can be achieved by a logical unit without changing device parameters of a circuit, and only three PMOS transistors, three NMOS transistors and three SETs are consumed. The reusable logical gate is simple in structure, low in power consumption, high in integration level and high in reconfigurable features, and is expected to be applied to super-large-scale integration circuits with low power consumption and high integration density in future.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a reusable logic gate with a hybrid structure of MOS transistors and single electron transistors. Background technique [0002] In digital circuits, MOS transistors have binary characteristics and work in two states of on and off. The logic functions realized by using MOS transistors need to consume more devices. Due to the limitations of MOS tube functions, it is difficult to greatly reduce the use of MOS tubes by optimizing the performance of MOS tubes. In addition, logic circuits based on MOS transistors have poor programmability, and it is difficult to switch between different logic gates. Therefore, the design method based on MOS transistors is difficult to meet the requirements of the new generation of circuits in terms of power consumption, integration, and reliability. [0003] In recent years, with the introduction of new nanoelectronic devices, it has beco...

AI Technical Summary

Problems solved by technology

Due to the limitations of MOS tube functions, it is difficult to greatly reduce the use of MOS tubes by optimizing the performance of MOS tubes

In addition, logic circuits based on MOS tubes have poor programmability, and it is difficult to convert between different logic gates

Therefore, the design method based on MOS transistors is difficult to meet the requirements of the new generation of circuits in terms of power consumption, integration, reliability, etc.

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