A reconfigurable cache product and method

Abstract

A reconfigurable cache organization structure, which can provide different numbers of path group structure caches according to configurations and store continuous-address instructions or data in the same path group when being applied to the field of processors, thereby facilitating a processor core in acquiring the instructions or data so as to reduce the number of times of label matching.

Description

technical field [0001] The present invention relates to the fields of computers, communications and integrated circuits. Background technique [0002] To improve performance, caches are commonly used in modern processor systems to temporarily store instructions or data in main memory. The address of the instruction or data stored in the cache is generally divided into three parts: the tag (TAG), the index number (index) and the offset within the block (offset). The cache is generally composed of tag memory and data memory, and the two are in one-to-one correspondence. Each storage block of the data memory stores a main memory block (ie, an instruction block or a data block), and the tag memory stores a tag corresponding to the address of the storage block. Depending on the form of organization, the cache usually has three forms: direct map (direct map), fully associative (fully associative) and group associative (way-set associative). [0003] In a direct-mapped cache str...

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Problems solved by technology

Therefore, in the set-associative cache structure, it is difficult to make a balanced choice between cache performance and hardware cost because it is unknown what kind of program will be executed.

[0008] Finally, in each way group of the direct mapping cache structure and the set associative structure, the index numbers of each storage block are continuous, and each index number can only correspond to one storage block, which is not flexible enough

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