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High-performance cache system and method

A memory and instruction memory technology, applied in the computer field, can solve various problems such as cache misses, and achieve the effects of avoiding capacity misses, reducing power consumption, and speeding up

Active Publication Date: 2014-01-15
SHANGHAI XINHAO MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the widening processor / memory speed gap, the current architecture, especially multiple cache misses, has become the most serious bottleneck restricting the performance improvement of modern processors

Method used

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  • High-performance cache system and method

Examples

Experimental program
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Embodiment 800

[0167] In this embodiment, the instruction read buffer 112 is composed of a register set 802, which has the same capacity as an instruction block and contains the current instruction block being executed by the processor. For ease of description, it is assumed that an instruction block has only two instructions, that is, the register bank 802 only includes registers capable of storing two instructions. The case for including more directives is similar.

[0168] In this embodiment, the current instruction block including the instructions to be executed by the processor core 116 will be stored in the register set 802 . Once the instruction to be executed by the processor core is not in the current instruction block, the instruction block where the instruction is located is read from the instruction memory 106 according to the first address pointer 614 of the instruction tracker 114 and stored in the register set 802, and at the same time The instruction information extracted by...

Embodiment 1300

[0223] In this embodiment, the data predictor 1216 includes an extractor 1334, a base address register value change step filter 1332 and an adder 1204. Extractor 1334 includes decoder 1322 and extractors 1324 , 1326 , 1328 . The extractor 1334 examines the instruction 1302 being acquired by the processor core 116, decodes it by the decoder 1322 to obtain the instruction type 1310, and then extracts the target register number 1304 in the register update instruction from the instruction 1302 according to the decoding result, The change amount of the register value 1306 and the base address register number 1308 of the data access instruction. Usually, register numbers, register value changes, etc. in different types of instructions can be located in different positions in the instruction word, so these information can be extracted from the corresponding positions in the instruction word according to the decoding result of the instruction type. In addition, the base address regis...

Embodiment 2040

[0316]In this embodiment, the registers and comparators in the address information matching unit are divided into three matching modules 2052, 2054 and 2056, and each matching module includes at least one register and a corresponding comparator. The address information configuration module 2042 includes a start address memory 2044 , an end address memory 2048 , a decider 2050 , an auto-incrementer 2046 and a selector 2058 . The entries in the start address storage 2044 and the end address storage 2048 correspond one to one, that is, one start address entry corresponds to one end address entry. Such as Figure 20A According to the embodiment, each register in the address information matching unit has an address, and the address can be obtained by mapping a row number or an index address. To determine which of these registers are used to store the instruction row address as an example, assume that there are several registers used to store the row address in the matching modules...

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PUM

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Abstract

The invention discloses a high-performance cache system and method. When applied to the field of processors, the high-performance cache system and method fill instruments or data to a high-speed storage to which a processor core can have direct access before the processor core executes the instruments or has access to the data. The processor core can obtain the needed instruments or data in the high-speed storage almost every time, and the very high cache hit ratio is achieved.

Description

technical field [0001] The invention relates to the fields of computer, communication and integrated circuit. Background technique [0002] Usually, the function of the cache is to copy part of the content in the lower-level memory, so that the content can be quickly accessed by the higher-level memory or the processor core, so as to ensure the continuous operation of the pipeline. [0003] The addressing of the current cache is based on the following method, use the index segment in the address to address the tag in the read tag memory and match the tag segment in the address; use the index segment in the address and the displacement segment in the block to jointly address the read cache in the content. If the tag read from the tag memory is the same as the tag segment in the address, then the content read from the cache is valid, which is called a cache hit. Otherwise, if the tag read from the tag memory is not the same as the tag segment in the address, it is called a c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/32G06F9/34G06F12/0862G06F12/0875G06F12/128
CPCG06F12/0862G06F9/3455G06F9/3804G06F9/3808G06F9/382G06F9/383G06F9/3832Y02D10/00G06F9/3858G06F12/0875G06F12/128G06F2212/452
Inventor 林正浩
Owner SHANGHAI XINHAO MICROELECTRONICS
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