Reconfigurable caching organization structure

Abstract

A reconfigurable cache organization structure, which can provide different numbers of path group structure caches according to configurations and store continuous-address instructions or data in the same path group when being applied to the field of processors, thereby facilitating a processor core in acquiring the instructions or data so as to reduce the number of times of label matching.

Description

technical field [0001] The invention relates to the fields of computer, communication and integrated circuit. Background technique [0002] In order to improve performance, caches are usually used in modern processor systems to temporarily store instructions or data in main memory. The address of an instruction or data stored in a cache is generally divided into three parts: a tag (TAG), an index number (index) and an offset within a block (offset). The cache is generally composed of a tag memory and a data memory, and the two correspond one-to-one. Each storage block of the data storage stores a main storage block (ie, an instruction block or a data block), and the tag storage stores a tag corresponding to the address of the storage block. Depending on the form of organization, there are usually three forms of caching: direct map, fully associative, and way-set associative. [0003] In a direct-mapped cache structure, each main memory block in main memory can only appear...

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Problems solved by technology

Therefore, in the set-associative cache structure, it is difficult to make a balanced choice between cache performance and hardware cost because it is unknown what kind of program will be executed.

[0008] Finally, in each way group of the direct mapping cache structure and the set associative structure, the index numbers of each storage block are continuous, and each index number can only correspond to one storage block, which is not flexible enough

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