A method for optimizing the bonding of stacked cis silicon wafers

Abstract

The invention discloses an optimized stack type CIS silicon wafer bonding method. According to the technical scheme of the invention, the bonding of a stack type CIS logic silicon wafer and a pixel silicon wafer is optimized based on the combination adjustment on the copper-electroplating boundary value between the stack type CIS logic silicon wafer and the pixel silicon wafer and the trimming on the crystal boundary of the pixel silicon wafer. In this way, the height difference phenomenon between the boundary region of the logic silicon wafer and a normal region is relieved. Meanwhile, during the bonding process, the pixel silicon wafer is kept away from the region of the logic silicon wafer with a larger height difference, so that no void defect occurs at the crystal boundary interface of the two silicon wafers during the bonding process. Therefore, the bonding performance between the logic silicon wafer and the pixel silicon wafer is optimized. The machinability of the subsequent silicon wafers is improved. Moreover, the stability of the stack type CIS chip manufacturing process is ensured, and the yield is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit image sensor manufacturing, and more particularly, relates to a method for optimizing the bonding of stacked CIS silicon wafers. Background technique [0002] In the development process of CMOS image sensor (CMOS Image Sensor, CIS), if the evolution from front-illuminated (FSI) CIS to back-illuminated (BSI) CIS is a revolution, then the development of back-illuminated CIS to stacked CIS is a revolution. Great innovation. At present, CIS is developing towards the direction of high resolution, high pixel and multifunctional integration requirements. [0003] The stacked CIS (Ultra-Thin Stacked CMOS Image Sensor) has become an excellent feature due to its flexible manufacturing process brought about by the separation of logic and pixel silicon wafers, low cost, increased available chip area, and multi-functional chips can be integrated together. A high-end product in the cu...

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