fpga logic unit with feedback path
A technology of feedback path and logic unit, applied in the field of FPGA logic unit, to achieve the effect of reducing delay
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Embodiment 1
[0032] In a first exemplary embodiment of the present invention, a logic unit with a feedback path from a register in an upper cascaded structure to a lower level lookup table is provided. Figure 4 It is a schematic structural diagram of an FPGA logic unit with a feedback path from a register in an upper-level cascade structure to a lookup table feedback path in a lower-level cascade structure according to an embodiment of the present invention. like Figure 4 As shown, the FPGA logic unit includes: n-level cascade structure. Among them, the cascade structure of each stage includes: a four-to-one multiplexer, a k-input single-output lookup table, a first two-to-one multiplexer, a register, and a second two-to-one multiplexer, wherein, n≥2.
[0033] In the ith stage cascade structure (1≤i≤n), the connection relationship of each component is as follows: four-to-one multiplexer, its four input terminals are respectively connected to the k input in the i-1th stage cascade struc...
Embodiment 2
[0051] In a second exemplary embodiment of the present invention, there is provided a logic unit with an upper level look-up table to a register feedback path in a lower cascade structure. Figure 5 It is a schematic structural diagram of an FPGA logic unit with a k-input single-output lookup table in the upper-level cascade structure to the register feedback path in the lower-level cascade structure according to the second embodiment of the present invention. like Figure 5 As shown, the FPGA logic unit includes: an n-level cascade structure, where n≥2.
[0052] The structure also remains image 3 All structures, on this basis, add the look-up table output to the register input path (58-1, 58-2, ..., 58-n) in the next cascade structure, this change also causes the register (22-1, 22- 2. The multiplexers (23b-1, 23b-2, . Figure 4 equivalence.
[0053]Wherein, the cascaded structure of each stage includes: a first 3-choice multiplexer, a k-input single-output lookup table,...
Embodiment 3
[0068] In the second exemplary embodiment of the present invention, there is provided a logic unit with a feedback path from an output of an upper cascade structure to a k-input single-output look-up table in a lower cascade structure. Image 6 It is a structural schematic diagram of an FPGA logic unit with a k-input single-output look-up table feedback path from an upper cascade structure output to a lower cascade structure according to Embodiment 3 of the present invention. like Image 6 As shown, the FPGA logic unit includes: an n-level cascade structure, where n≥2.
[0069] like Image 6 As shown, the structure retains image 3 Most of the structure in, only removed the feedback path 24-1,24-2...24-n that the look-up table output to the next level look-up table input, replaced by the total output terminal (23c-1,23c from LE -2...23c-n output terminal) to the feedback path 69-1, 69-2...69-n of the input of the look-up table of the next stage. Since the total output term...
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