FPGA logic unit with feedback path
A logic unit and feedback path technology, applied in the field of FPGA logic unit, to achieve the effect of reducing delay
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0032] In the first exemplary embodiment of the present invention, a logic unit with a feedback path from a register in an upper cascaded structure to a lower-level look-up table is provided. Figure 4 It is a structural schematic diagram of an FPGA logic unit with a feedback path from a register in an upper-level cascaded structure to a look-up table in a lower-level cascaded structure according to an embodiment of the present invention. like Figure 4 As shown, the FPGA logic unit includes: an n-level cascade structure. Wherein, the cascaded structure of each stage includes: four selectors one multiplexer, k input single output lookup table, first two select one multiplexer, register and second two select one multiplexer, wherein, n≥2.
[0033] In the cascade structure of the i-th level (1≤i≤n), the connection relationship of each component is as follows: a four-choice one-to-one multiplexer, and its four input terminals are respectively connected to the k input in the i-1...
Embodiment 2
[0051] In a second exemplary embodiment of the present invention, a logic unit with a feedback path from an upper-level look-up table to a register in a lower cascade structure is provided. Figure 5 It is a structural schematic diagram of an FPGA logic unit with a feedback path from a k-input single-output lookup table in an upper-level cascaded structure to a register feedback path in a lower-level cascaded structure according to Embodiment 2 of the present invention. like Figure 5 As shown, the FPGA logic unit includes: an n-level cascade structure, where n≥2.
[0052] The structure is also preserved image 3 All structures, on this basis, add the lookup table output to the register input path (58-1, 58-2, ..., 58-n) in the next cascaded structure, and this change causes the register (22-1, 22-n) at the same time 2, ..., 22-n) The multiplexer (23b-1, 23b-2, ..., 23b-n) at the input end is increased from 2 inputs to 3 inputs, and the beneficial effect brought is the same ...
Embodiment 3
[0068] In the second exemplary embodiment of the present invention, there is provided a logic unit with a feedback path from an output of an upper cascade structure to a k-input single-output look-up table in a lower cascade structure. Image 6 It is a structural schematic diagram of an FPGA logic unit with a k-input single-output look-up table feedback path from an upper cascade structure output to a lower cascade structure according to Embodiment 3 of the present invention. like Image 6 As shown, the FPGA logic unit includes: an n-level cascade structure, where n≥2.
[0069] like Image 6 As shown, the structure retains image 3 Most of the structures in the structure only remove the feedback path 24-1, 24-2...24-n from the output of the look-up table to the input of the next-level look-up table, and replace it with the total output terminal (23c -1, 23c-2 ... 23c-n output terminal) to the feedback path 69-1, 69-2 ... 69-n of the input of the next-level lookup table. Si...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More