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A test vector generation method and apparatus for a PCIE interface

A technology of test vectors and generating devices, which is applied in the computer field and can solve problems such as heavy workload

Inactive Publication Date: 2018-12-28
JINAN INSPUR HIGH TECH TECH DEV CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Obviously, the manual writing of test vectors leads to a large workload

Method used

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  • A test vector generation method and apparatus for a PCIE interface
  • A test vector generation method and apparatus for a PCIE interface
  • A test vector generation method and apparatus for a PCIE interface

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Embodiment Construction

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection of the present invention. scope.

[0054] Such as figure 1 As shown, the embodiment of the present invention provides a kind of test vector generation method for PCIE interface, can comprise the following steps:

[0055] Step 101: For the current design under test, write a source data package information document, an IO information document and a data source information document.

[00...

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Abstract

The invention provides a test vector generation method and a device for a PCIE interface. The method comprises the following steps: compiling a source data packet information document, an IO information document and a data source information document according to a current design under test; The scripts are generated by running the preset test vectors. According to the IO information document, thefirst number of PCIE design top-level modules are instantiated in the test vectors. A second number of FIFO design top-level modules and a second number of data generation modules are instantiated inthe test vector according to the source packet information document and the data source information document; the data generation module and an FIFO design top-level module, an FIFO design top-levelmodule and a PCIE design top-level module are in signal connection; for the test vector file of the test vector, the input and output interface declarations and internal signal declarations are generated to complete the test vector generation. The scheme can automatically generate test vectors, and can reduce the workload of generating test vectors.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a test vector generation method and device for a PCIE interface. Background technique [0002] PCI-E (PCI-Express) is a general-purpose bus specification, which is advocated and promoted by Intel, and its ultimate design purpose is to replace the bus transmission interface inside the existing computer system, which not only includes the display interface, but also includes Various application interfaces such as CPU, PCI (Peripheral Component Interconnect, peripheral component interconnection standard), HDD (Hard DiskDrive, hard disk drive), Network, etc. have been established. At present, there are more and more developments based on the PCIE interface. Since users customize different protocols in the PCIE bus in different designs, it is necessary to write specific test vectors for each design. [0003] Currently, specific test vectors can be manually written for each design. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/263G06F13/42
CPCG06F11/263G06F13/4221
Inventor 赵鑫鑫姜凯李朋
Owner JINAN INSPUR HIGH TECH TECH DEV CO LTD
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