Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate, the substrate comprises an ineffective region, the surface of the ineffective region has a plurality of first gate structures separated from each other, the substrate on both sides of each first gate structure has a source-drain doping region, and the plurality of first gate structures are arranged along a first direction; a plurality of first conductive layers separated from each other, each of the first conductive layers is located on the surface of one or more of the source-drain doping regions, and the top surface of the first gate structure is lower than the top surface of the first conductive layer; a plurality of first plugs, and the top surface of each portion of the first conductive layer has a first plug; a conductive structure connected to the plurality of first plugs, and the conductive structure is electrically isolated from the first gate structure. The semiconductor structure reduces parasitic resistance while improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of semiconductor manufacturing industry, there are corresponding demands for improving device performance (e.g., increasing processing speed, storage capacity, etc.), extending battery life, and reducing manufacturing costs. In order to meet the above requirements, the semiconductor industry is constantly working towards reducing the size of semiconductor devices, so that modern integrated circuits can include tens of thousands or hundreds of millions of semiconductor structures on a single semiconductor chip.

[0003] Generally, there are conductive lines and conductive plugs in a semiconductor structure, and the conductive lines and conductive plugs are used to form electrical connections with front-end-of-line (FEOL) process components and back-end-of-line (BEOL) process components to achieve functions.

[0004] However, as the size of semiconductor devices continues to shrink, smaller conductive layers and first plugs tend to increase parasitic resistance, resulting in a decrease in the performance of the formed semiconductor structure. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce parasitic resistance and improve the electrical performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes an invalid area, the surface of the invalid area has a plurality of first gate structures separated from each other, the substrate on both sides of each first gate structure has a source-drain doped region, and the plurality of first gate structures are arranged along a first direction; a plurality of first conductive layers separated from each other, each of the first conductive layers is located on the surface of one or more of the source-drain doped regions, and the top surface of the first gate structure is lower than the top surface of the first conductive layer; a plurality of first plugs, and each of the top surfaces of the first conductive layers has a first plug; a conductive structure connected to the plurality of first plugs, and the conductive structure is electrically isolated from the first gate structure.

[0007] Optionally, it also includes: a first dielectric layer located on the surface of the substrate, the first dielectric layer is located on the surface of the source and drain doped regions, the top surface and side wall surface of the first gate structure, and the side wall surface of the first conductive layer; a second dielectric layer located on the surface of the first dielectric layer, and the top surface of the second dielectric layer is flush with the top surface of the first plug; a third dielectric layer located on the surface of the second dielectric layer, the third dielectric layer has a second conductive layer located on the top surfaces of several of the first plugs, and the top surface of the third dielectric layer is flush with the top surface of the second conductive layer.

[0008] Optionally, the conductive structure contacts a plurality of first plug sidewall surfaces, and the conductive structure extends along a first direction.

[0009] Optionally, the top surface of the conductive structure is flush with the top surface of the second dielectric layer.

[0010] Optionally, the first conductive layer includes: a first end and a second end, and the plurality of first plugs are respectively located on the top surface of the first end of each of the first conductive layers.

[0011] Optionally, the conductive structure includes: a plurality of parallel first plugs and parallel second conductive layers, the plurality of parallel first plugs are respectively located on the top surface of the second end of each first conductive layer, and the parallel second conductive layers are located on the top surfaces of the plurality of parallel first plugs.

[0012] Optionally, the conductive structure further includes: a plurality of parallel second plugs and a parallel third conductive layer, the plurality of parallel second plugs are respectively located on the top surface of the second conductive layer and the top surface of the parallel second conductive layer, and the parallel third conductive layer is located on the surfaces of the plurality of parallel second plugs.

[0013] Optionally, the substrate also includes: an effective area adjacent to the invalid area, the surface of the effective area having mutually discrete second gate structures, and a plurality of the second gate structures are arranged along the first direction; the source and drain doped areas are also located in the substrate on both sides of each of the second gate structures; and each of the first conductive layers is also located on the surface of one or more of the source and drain doped areas of the effective area.

[0014] Optionally, when the effective region is located at both sides of the ineffective region, the conductive structure is located above the second gate structure.

[0015] Optionally, the second conductive layer is electrically connected to an external voltage.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming any of the above-mentioned semiconductor structures, including: providing a substrate, the substrate including an invalid area, the surface of the invalid area having a plurality of first gate structures separated from each other, the substrate having source-drain doped areas on both sides of each first gate structure, and the plurality of first gate structures being arranged along a first direction; forming a plurality of first conductive layers separated from each other on the surface of the source-drain doped area, one or more of the surface of the source-drain doped area having a first conductive layer, the plurality of first conductive layers and the plurality of first gate structures being arranged alternately, and the top surface of the first gate structure being lower than the top surface of the first conductive layer, a plurality of first plugs being formed on the top surface of the first conductive layer, and the top surface of each portion of the first conductive layer having a first plug respectively; forming a conductive structure electrically connecting the plurality of first conductive layers, and the conductive structure being electrically isolated from the first gate structure.

[0017] Optionally, it also includes: after forming the first gate structure and the source-drain doped regions and before forming the first plug, forming a first dielectric layer on the surface of the substrate, the first dielectric layer is located on the surface of the source-drain doped regions, the top surface of the first gate structure and the sidewall surface; forming a plurality of the first conductive layers in the first dielectric layer; after forming the first conductive layer, forming a second dielectric layer on the surfaces of the first dielectric layer and the first conductive layer, and the top surface of the second dielectric layer is flush with the top surface of the first plug; forming a third dielectric layer on the surface of the second dielectric layer, the third dielectric layer has a second conductive layer located on the top surfaces of the plurality of the first plugs, and the top surface of the third dielectric layer is flush with the top surface of the second conductive layer.

[0018] Optionally, during the process of forming the first plug, the conductive structure is formed, the conductive structure is in contact with the surface of the side wall of the first plug, and the conductive structure extends along the first direction.

[0019] Optionally, the method for forming the conductive structure and the first plug includes: after forming the second dielectric layer and before forming the third dielectric layer, forming a first mask layer on the surface of the second dielectric layer, and the first mask layer exposes a portion of the surface of the second dielectric layer; using the first mask layer as a mask, etching the second dielectric layer until a portion of the top surface of the first conductive layer is exposed, forming a first opening and a second opening in the second dielectric layer, the first opening exposing the top surface of the first conductive layer, the second opening being located between adjacent first openings, and the first opening and the second opening being connected; forming a first plug in the first opening, and forming a conductive structure in the second opening.

[0020] Optionally, the first conductive layer includes: a first end and a second end, and the first plug is respectively located on the top surface of the first end of the first conductive layer; the formation process of the conductive structure includes: after forming the second dielectric layer and before forming the third dielectric layer, forming parallel first plugs in the second dielectric layer, and the parallel first plugs are respectively located on the top surface of the second end of the first conductive layer; after forming the parallel first plugs, forming a third dielectric layer on the surface of the second dielectric layer and the surface of the parallel first plugs, and forming parallel second conductive layers in the third dielectric layer, and the parallel second conductive layers are located on the top surfaces of several parallel first plugs.

[0021] Optionally, in the process of forming the first plug, the parallel first plug is formed; and in the process of forming the second conductive layer, the parallel second conductive layer is formed.

[0022] Optionally, the formation process of the conductive structure further includes: after forming the parallel second conductive layer, forming a fourth dielectric layer on the surface of the second conductive layer and the surface of the third dielectric layer; forming a plurality of parallel second plugs in the fourth dielectric layer, and the parallel second plugs are respectively located on the top surface of the second conductive layer and the top surface of the parallel second conductive layer; forming a fifth dielectric layer on the surface of the fourth dielectric layer and the surface of the parallel second plugs; forming a parallel third conductive layer in the fifth dielectric layer, and the parallel third conductive layer is located on the plurality of parallel second plugs.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the semiconductor structure provided by the technical solution of the present invention, since the conductive structure electrically connects several first conductive layers, several conductive paths extending in parallel can be formed between the second conductive layer and the first conductive layer. When the second conductive layer is electrically connected to an external source voltage, the several conductive paths can increase the cross-sectional area of ​​the device used to transmit current from the second conductive layer to the invalid area (compared with a single conductive path), which is beneficial to reduce parasitic resistance. At the same time, the conductive structure is electrically isolated from the first gate structure, thereby preventing the first gate structure from being electrically connected to the second conductive layer through the conductive structure, causing the first gate structure to short-circuit. In summary, the semiconductor structure can reduce parasitic resistance while having high electrical performance.

[0025] Furthermore, when the effective area is located on both sides of the invalid area, the conductive structure is located above the second gate structure, so that the conductive structure electrically connects the first conductive layer on the surface of the invalid area on both sides of the effective area, that is, it can reduce the parasitic resistance while not affecting the second gate structure in the effective area, thereby avoiding a short circuit in the second gate structure in the effective area and further improving the electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 and Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0027] Figures 3 to 9 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0028] Figures 10 to 16 is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention;

[0029] Figures 17 to 19 It is a schematic structural diagram of a semiconductor structure in yet another embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, the performance of existing semiconductor structures is poor.

[0031] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figure 1 and Figure 2 It is a structural diagram of a semiconductor structure.

[0032] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 A top view along the F direction, and Figure 1 The conductive layer is omitted in the schematic diagram. Figure 2 yes Figure 1 The schematic cross-sectional structure diagram along the tangent line A-A1 includes: a substrate 100, wherein the substrate 100 includes an adjacent ineffective region I and an effective region II, wherein the surface of the ineffective region I has a first gate structure 111 and a second gate structure 112 separated from each other, and the surface of the effective region II has a third gate structure 113 separated from each other; a first conductive layer 121, a second conductive layer 122, and a third conductive layer 123 separated from each other on the surface of the substrate 100, wherein the first gate structure 111 is located between the first conductive layer 121 and the second conductive layer 122, and the second gate structure 112 is located between the second conductive layer 122 and the third conductive layer 123; between three conductive layers 123; a first plug 131 located on the top surface of the first conductive layer 121; a second plug 132 located on the top surface of the second conductive layer 122; a third plug 133 located on the top surface of the third conductive layer 123; a conductive layer 150 located on the top surfaces of the first plug 131, the second plug 132 and the third plug 133; a conductive structure 140 located on the top surfaces of the first gate structure 111, the second gate structure 112, the first conductive layer 121, the second conductive layer 122 and the third conductive layer 123.

[0033] In the above semiconductor structure, due to the need for circuit connection, the first plug 131, the second plug 132 and the third plug 133 are usually electrically connected to the first voltage through the conductive layer 150, resulting in the first gate structure 111 and the source-drain doped regions (not shown in the figure) in the substrate 100 on both sides of the first gate structure 111 forming an invalid device, and the second gate structure 112 and the source-drain doped regions (not shown in the figure) in the substrate 100 on both sides of the second gate structure 112 also forming an invalid device. Since the conductive structure 140 is electrically connected to the first conductive layer 121, the second conductive layer 122 and the third conductive layer 123, a first conductive path, a second conductive path and a third conductive path extending in parallel are formed between the conductive layer 150 and the second conductive layer 122, or between the conductive layer 150 and the third conductive layer 123. The parallel first conductive path, the second conductive path and the third conductive path increase the cross-sectional area of ​​the effective device formed by the current transmission from the conductive layer 150 to the third gate structure 113 (compared with a single conductive path), thereby reducing the parasitic resistance of the effective device formed by the third gate structure 113.

[0034] However, the conductive structure 140 is not only located on the top surface of the first conductive layer 121, the top surface of the second conductive layer 122, and the top surface of the third conductive layer 123, but also located on the top surface of the first gate structure 111 and the top surface of the second gate structure 112. As a result, the first gate structure 111 is electrically connected to the conductive layer 150, and the second gate structure 112 is electrically connected to the conductive layer 150, so that voltage is applied to the first gate structure 111 and the second gate structure 112, which is likely to cause adverse effects on the first gate structure 111 and the second gate structure 112. For example, when different voltages are applied to the first gate structure 111 or the second gate structure 112 at the same time, the first gate structure 111 or the second gate structure 112 is short-circuited, so that the performance of the formed semiconductor structure is reduced.

[0035] In order to solve the technical problem, the present method embodiment provides a semiconductor structure, including: a substrate, the substrate includes an invalid area, the surface of the invalid area has a plurality of first gate structures separated from each other, the substrate on both sides of each first gate structure has a source-drain doping region, and the plurality of first gate structures are arranged along a first direction; a plurality of first conductive layers separated from each other, each of the first conductive layers is located on the surface of one or more of the source-drain doping regions, and the top surface of the first gate structure is lower than the top surface of the first conductive layer; a plurality of first plugs, and each of the top surfaces of the first conductive layers has a first plug; a conductive structure connected to the plurality of first plugs, and the conductive structure is electrically isolated from the first gate structure. The semiconductor structure reduces parasitic resistance while improving electrical performance.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 3 to 9 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0038] Please refer to Figure 3 , providing a substrate 200, the substrate 200 includes an ineffective area I, the surface of the ineffective area I has a plurality of first gate structures 211 separated from each other, each of the first gate structures 211 has a source-drain doped region 201 in the substrate 200 on both sides, and the plurality of first gate structures 211 are arranged along a first direction X.

[0039] The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0040] In this embodiment, the substrate 200 also includes: an effective area II adjacent to the ineffective area I, the surface of the effective area II has separate second gate structures 212, and a plurality of the second gate structures 212 are arranged along the first direction X; the source and drain doped regions 201 are also located in the substrate 200 on both sides of each of the second gate structures 212.

[0041] It should be noted that, in this embodiment, the effective area II is located on both sides of the ineffective area I. In other embodiments, the effective area is located on one side of the ineffective area, or the ineffective area is located on both sides of the effective area.

[0042] A plurality of first conductive layers separated from each other are formed on the surface of the source-drain doped region, one or more of the source-drain doped region surfaces have a first conductive layer, the plurality of first conductive layers and the plurality of first gate structures are arranged alternately, and the top surface of the first gate structure is lower than the top surface of the first conductive layer. For the specific process of forming the plurality of first conductive layers, please refer to Figure 4 and Figure 5 .

[0043] Please refer to Figure 4 A first dielectric layer 220 is formed on the surface of the substrate 200 , and the first dielectric layer 220 is located on the surface of the source and drain doped regions 201 , the top surface and the sidewall surface of the first gate structure 211 .

[0044] The top surface of the first dielectric layer 220 is higher than the top surface of the first gate structure 211 .

[0045] In this embodiment, the first dielectric layer 220 is also located on the top surface and sidewall surfaces of the second gate structure 212 , and the top surface of the first dielectric layer 220 is higher than the top surface of the second gate structure 212 .

[0046] The first dielectric layer 220 has the following functions: on the one hand, it is used for electrical isolation; on the other hand, it provides support for the subsequent formation of the first conductive layer.

[0047] The material of the first dielectric layer 220 includes oxide, ultra-low-K dielectric material or low-K dielectric material.

[0048] In this embodiment, the material of the first dielectric layer 220 is silicon oxide.

[0049] The process of forming the first dielectric layer 220 includes: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0050] Please refer to Figure 5 , a plurality of first conductive layers 221 are formed in the first dielectric layer 220 .

[0051] The method for forming the first conductive layer 221 includes: forming a second mask layer (not shown in the figure) on the surface of the first dielectric layer 220, wherein the second mask layer exposes a portion of the surface of the first dielectric layer 220; etching the first dielectric layer 220 with the second mask layer as a mask until the surface of the source-drain doped region 201 is exposed, and forming a plurality of third openings (not shown in the figure) in the first dielectric layer 220; and forming the first conductive layer 221 in the third openings, wherein the top surface of the first conductive layer 221 is flush with the top surface of the first dielectric layer 220.

[0052] Specifically, in this embodiment, a plurality of first conductive layers 221 separated from each other are formed on the surface of the source-drain doped region 201 , a surface of the source-drain doped region 201 has a first conductive layer 221 , a plurality of the first conductive layers 221 and a plurality of first gate structures 211 are arranged alternately, and a top surface of the first gate structure 211 is lower than a top surface of the first conductive layer 221 .

[0053] In other embodiments, the surfaces of the plurality of source and drain doped regions have a first conductive layer.

[0054] In this embodiment, a plurality of the first conductive layers 221 and a plurality of the second gate structures 212 are arranged alternately, and the top surface of the second gate structure 212 is lower than the top surface of the first conductive layer 221 .

[0055] Please refer to Figure 6 , a second dielectric layer 230 is formed on the surface of the first dielectric layer 220 and the first conductive layer 221 .

[0056] The second dielectric layer 230 has the following functions: on the one hand, it is used for electrical isolation; on the other hand, it is used to provide support for the subsequent formation of the first plug and the conductive structure.

[0057] The material of the second dielectric layer 230 includes oxide, ultra-low-K dielectric material or low-K dielectric material.

[0058] In this embodiment, the material of the second dielectric layer 230 is silicon oxide.

[0059] The process of forming the second dielectric layer 230 includes: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0060] Please refer to Figure 7 After forming the second dielectric layer 230 , a plurality of first plugs 231 are formed on the top surface of the first conductive layer 221 , and each of the first conductive layers 221 has a first plug 231 on its partial top surface.

[0061] Specifically, the first plug 231 is formed in the second dielectric layer of the ineffective area I, and the top surface of the first plug 231 is flush with the top surface of the second dielectric layer 230 .

[0062] Please continue to refer to Figure 7 , further comprising: forming a conductive structure 232 electrically connecting the plurality of first conductive layers 221 , and the conductive structure 232 is electrically isolated from the first gate structure 211 .

[0063] In this embodiment, the conductive structure 232 is formed during the process of forming the first plug 231 . The conductive structure 232 is in contact with the sidewall surface of the first plug 231 , and the conductive structure 232 extends along the first direction X.

[0064] The method for forming the conductive structure 232 and the first plug 231 includes: forming a first mask layer (not shown in the figure) on the surface of the second dielectric layer 230, and the first mask layer exposes a portion of the surface of the second dielectric layer 230; using the first mask layer as a mask, etching the second dielectric layer 230 until a portion of the top surface of the first conductive layer 221 is exposed, and forming a first opening (not shown in the figure) and a second opening (not shown in the figure) in the second dielectric layer 230, wherein the first opening exposes the top surface of the first conductive layer 221, and the second opening is located between adjacent first openings, and the first opening and the second opening are connected; forming the first plug 231 in the first opening, and forming the conductive structure 232 in the second opening.

[0065] Since the first opening is connected to the second opening, the first plug 231 formed in the first opening is connected to the conductive structure 232 formed in the second opening, and thus the first plug 231 is electrically connected to the conductive structure 232. Furthermore, since the first plug 231 is electrically connected to a plurality of first conductive layers 221, the conductive structure 232 can electrically connect the plurality of first conductive layers 221, so that a plurality of conductive paths extending in parallel can be formed between the second conductive layer and the first conductive layer 221 formed subsequently.

[0066] Please refer to Figure 8 and Fig. 9 , Fig. 9 for Figure 8 Top view along the X direction, Figure 8 for Fig. 9 A schematic cross-sectional view along the tangent line A-A1, and Fig. 9 To omit the schematic diagram of the first dielectric layer 220, the second dielectric layer 230, and the third dielectric layer 240, a conductive structure 232 is formed on the surface of the second dielectric layer 230, and the third dielectric layer 240 has a second conductive layer 241 located on the top surfaces of the first plugs 231, and the top surface of the third dielectric layer 240 is flush with the top surface of the second conductive layer 241.

[0067] The method for forming the second conductive layer 241 includes: forming a third mask layer (not shown in the figure) on the surface of the third dielectric layer 240, wherein the third mask layer exposes a portion of the surface of the third dielectric layer 240; etching the third dielectric layer 240 using the third mask layer as a mask until the surface of the first plug 231 and the surface of the conductive structure 232 are exposed, and forming a fourth opening (not shown in the figure) in the third dielectric layer 240; and forming the second conductive layer 241 in the fourth opening, wherein the top surface of the second conductive layer 241 is flush with the top surface of the third dielectric layer 240.

[0068] It should be noted that, in this embodiment, the external source voltage is connected through the second conductive layer 241, and the second conductive layer 241 is located on the top surface of the first plugs 231. In other embodiments, the external source voltage can also be connected through the Nth conductive layer, and the Nth conductive layer is electrically connected to the first plugs, where N is a natural number greater than 2.

[0069] Since the first plug 231 is electrically connected to the conductive structure 232, and the first plug 231 is electrically connected to a plurality of first conductive layers 221, the conductive structure 232 can electrically connect a plurality of first conductive layers 221. Furthermore, the conductive structure 232 can electrically connect a plurality of first conductive layers 221, so that a plurality of conductive paths extending in parallel can be formed between the second conductive layer 241 and the first conductive layer 231. When the second conductive layer 241 is electrically connected to an external source voltage, the plurality of conductive paths can increase the cross-sectional area of ​​the device for transmitting current from the second conductive layer 241 to the inactive region I (compared with a single conductive path), thereby facilitating the reduction of parasitic resistance. At the same time, the conductive structure 232 is electrically isolated from the first gate structure 211, thereby preventing the first gate structure 211 from being electrically connected to the second conductive layer 241 through the conductive structure 232, resulting in a short circuit in the first gate structure 211. In summary, the semiconductor structure can reduce parasitic resistance while having high electrical performance.

[0070] In other embodiments, when the invalid area is located on both sides of the effective area, the conductive structure can also be located above the second gate structure, so that when the conductive structure electrically connects the first conductive layer on the surface of the invalid area on both sides of the effective area, that is, it can reduce the parasitic resistance while not affecting the second gate structure in the effective area, thereby avoiding a short circuit in the second gate structure in the effective area and further improving the electrical performance.

[0071] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Figure 8 and Fig. 9 , comprising: a substrate 200, the substrate 200 comprising an ineffective region I, the surface of the ineffective region I having a plurality of mutually independent first gate structures 211, the substrate 200 having source-drain doped regions 201 on both sides of each of the first gate structures 211, and the plurality of first gate structures 211 being arranged along a first direction X; a plurality of mutually independent first conductive layers 221, each of the first conductive layers 221 being located on the surface of one or more of the source-drain doped regions 201, and the top surface of the first gate structure 211 being lower than the top surface of the first conductive layer 221; a plurality of first plugs 231, and each of the first conductive layers 221 having a first plug 231 on a portion of its top surface; and a conductive structure 232 connected to the plurality of first plugs 231, and the conductive structure 232 being electrically isolated from the first gate structure 211.

[0072] In this embodiment, the conductive structure 232 contacts the sidewall surfaces of the first plugs 231 , and the conductive structure 232 extends along the first direction X.

[0073] The following is a detailed description with reference to the accompanying drawings.

[0074] The substrate also includes: an effective area II adjacent to the ineffective area I, the surface of the effective area II having mutually discrete second gate structures 212, and a plurality of the second gate structures 212 are arranged along the first direction X; the source-drain doped area 201 is also located in the substrate 200 on both sides of each of the second gate structures 212; and each of the first conductive layers 221 is also located on the surface of one or more of the source-drain doped areas 201 of the effective area II.

[0075] In this embodiment, each of the first conductive layers 221 is located on a surface of a source / drain doped region 201 in the ineffective region I, and each of the first conductive layers 221 is also located on a surface of a source / drain doped region 201 in the effective region I.

[0076] In this embodiment, the active area is located at both sides of the inactive area. In other embodiments, the active area is located at one side of the inactive area, or the inactive area is located at both sides of the active area.

[0077] In other embodiments, when the active region is located at both sides of the inactive region, the conductive structure is also located above the second gate structure.

[0078] The semiconductor structure further includes: a first dielectric layer 220 located on the surface of the substrate 200, the first dielectric layer 220 being located on the surface of the source-drain doped region 201, the top surface and the sidewall surface of the first gate structure 211, and the sidewall surface of the first conductive layer 221; a second dielectric layer 230 located on the surface of the first dielectric layer 220, and the top surface of the second dielectric layer 230 is flush with the top surface of the first plug 231; a third dielectric layer 240 located on the surface of the second dielectric layer 230, the third dielectric layer 240 having a second conductive layer 241 located on the top surfaces of the first plugs 231, and the top surface of the third dielectric layer 240 is flush with the top surface of the second conductive layer 241.

[0079] The top surface of the conductive structure 232 is flush with the top surface of the second dielectric layer 230 .

[0080] In this embodiment, the semiconductor structure is electrically connected to an external voltage through the second conductive layer 241 .

[0081] Since the conductive structure 232 electrically connects several first conductive layers 221, several conductive paths extending in parallel can be formed between the second conductive layer 241 and the first conductive layer 221. When the second conductive layer 241 is electrically connected to an external voltage, the several conductive paths can increase the cross-sectional area of ​​the device for transmitting current from the second conductive layer 241 to the invalid region I (compared with a single conductive path), which is beneficial to reduce parasitic resistance. At the same time, the conductive structure 232 is electrically isolated from the first gate structure 211, thereby preventing the first gate structure 211 from being electrically connected to the second conductive layer 241 through the conductive structure 232, causing a short circuit in the first gate structure 211. In summary, the semiconductor structure can reduce parasitic resistance while having high electrical performance.

[0082] Figures 10 to 16 1 is a schematic diagram of the steps of a method for forming a semiconductor structure in another embodiment of the present invention. The difference between this embodiment and the above embodiment lies in the formation method and structure of the conductive structure. Therefore, this embodiment continues to explain the formation process of the semiconductor structure based on the above embodiment.

[0083] It should be noted that the first conductive layer 221 includes a first end 2211 and a second end 2212 .

[0084] Please Figure 6 Continue to refer to Figures 10 to 12 , Fig.10 for Fig.12 Schematic diagram of the cross section along the A-A1 tangent line. Fig.11 for Fig.12 Schematic diagram of the cross section along the tangent line A2-A3, Fig.12 for Fig.10 A top view along the F direction, and Fig.12 The schematic diagram of the first dielectric layer 220 and the second dielectric layer 230 is omitted. After the second dielectric layer 230 is formed, a plurality of first plugs 331 are formed in the second dielectric layer 230 , and each of the first conductive layers 221 has a first plug 331 on its partial top surface.

[0085] In this embodiment, the first plugs 331 are respectively located on the top surface of the first end 2211 of the first conductive layer 221 on the inactive region I.

[0086] Please continue to refer to Figures 10 to 12 , parallel first plugs 332 are formed in the second dielectric layer 230 , and the parallel first plugs 332 are respectively located on the top surface of the second end 2212 of the first conductive layer 221 .

[0087] In this embodiment, the parallel first plugs 332 are respectively located on the top surface of the first end 2212 of the first conductive layer 221 on the inactive region I.

[0088] In this embodiment, the parallel first plugs 332 are formed during the process of forming the first plugs 331 .

[0089] The method for forming the first plug 331 and the parallel first plug 332 includes: forming a fourth mask layer (not shown in the figure) on the surface of the second dielectric layer 230 and the surface of the first conductive layer 221, wherein the fourth mask layer exposes a portion of the surface of the second dielectric layer 230; using the fourth mask layer as a mask, etching the second dielectric layer 230 until the surface of the first conductive layer 221 is exposed, forming a fifth opening (not shown in the figure) and a sixth opening (not shown in the figure) in the second dielectric layer 230, wherein the bottom of the fifth opening exposes the surface of the first end 2211, and the bottom of the sixth opening exposes the surface of the second end 2212; forming the first plug 331 in the fifth opening, and forming the parallel first plug 332 in the sixth opening, wherein the top surface of the first plug 331 and the top surface of the parallel first plug 332 are flush with the surface of the second dielectric layer 230.

[0090] Please refer to Fig.13 , Fig.13 For Fig.10 Based on the schematic diagram, a third dielectric layer 340 is formed on the surface of the second dielectric layer 230 and parallel to the surface of the first plug 332 .

[0091] In this embodiment, after the first plug 331 and the parallel first plug 332 are formed, the third dielectric layer 340 is formed on the surface of the second dielectric layer 230 and the surfaces of the first plug 331 and the parallel first plug 332 .

[0092] The material and the forming process of the third dielectric layer 340 are the same as those of the third dielectric layer 240 in the above embodiment, and are not described in detail herein.

[0093] Please refer to Figures 14 to 16 , Fig.14 for Fig.16 Schematic diagram of the cross section along the A-A1 tangent line. Fig.15 for Fig.16 Schematic diagram of the cross section along the tangent line A2-A3, Fig.16 for Fig.14 A top view along the F direction, and Fig.16 The schematic diagrams of the first dielectric layer 220 , the second dielectric layer 230 and the third dielectric layer 340 are omitted. A second conductive layer 341 is formed in the third dielectric layer 340 , and the second conductive layer 341 is located on the top surfaces of the first plugs 331 .

[0094] In this embodiment, an external source voltage is connected through the second conductive layer 341 .

[0095] Please continue to refer to Figures 14 to 16 , a parallel second conductive layer 342 is formed in the third dielectric layer 340 , and the parallel second conductive layer 342 is located on the top surface of the plurality of parallel first plugs 332 .

[0096] In this embodiment, the parallel second conductive layer 342 is formed during the process of forming the second conductive layer 341 .

[0097] The parallel first plugs 332 and the parallel second conductive layers 342 form a conductive structure 345 .

[0098] The conductive structure 345 includes parallel first plugs 332 and parallel second conductive layers 342 . The parallel first plugs 332 are located at the second ends 2212 of the first conductive layers 221 . The parallel second conductive layers 242 electrically connect the parallel first plugs 332 , so that the conductive structure 345 can electrically connect the first conductive layers 221 .

[0099] The conductive structure 335 electrically connects several first conductive layers 221, so that several conductive paths extending in parallel can be formed between the second conductive layer 341 and the first conductive layer 231. When the second conductive layer 341 is electrically connected to an external source voltage, the several conductive paths can increase the cross-sectional area of ​​the device for transmitting current from the second conductive layer 341 to the inactive region I (compared with a single conductive path), thereby facilitating the reduction of parasitic resistance. At the same time, the conductive structure 335 is electrically isolated from the first gate structure 211, thereby preventing the first gate structure 211 from being electrically connected to the second conductive layer 241 through the conductive structure 335, causing a short circuit in the first gate structure 211. In summary, the semiconductor structure can reduce parasitic resistance while having high electrical performance.

[0100] In other embodiments, the formation process of the conductive structure further includes: after forming the parallel second conductive layer, forming a fourth dielectric layer on the surface of the second conductive layer and the surface of the third dielectric layer; forming a plurality of parallel second plugs in the fourth dielectric layer, and the parallel second plugs are respectively located on the top surface of the second conductive layer and the top surface of the parallel second conductive layer; forming a fifth dielectric layer on the surface of the fourth dielectric layer and the surface of the parallel second plugs; forming a parallel third conductive layer in the fifth dielectric layer, and the parallel third conductive layer is located on a plurality of the parallel second plugs.

[0101] Accordingly, the embodiment of the present invention also provides a semiconductor structure formed by the above method, please continue to refer to Figures 14 to 16, comprising: a substrate 200, wherein the substrate 200 comprises an ineffective region I, wherein the surface of the ineffective region I comprises a plurality of mutually independent first gate structures 211, wherein the substrate 200 comprises source-drain doped regions 201 on both sides of each of the first gate structures 211, and wherein the plurality of first gate structures 211 are arranged along a first direction X; a plurality of mutually independent first conductive layers 221, wherein each of the first conductive layers 221 is located on the surface of one or more of the source-drain doped regions 201, and wherein the top surface of the first gate structure 211 is lower than the top surface of the first conductive layer 221; a plurality of first plugs 231, wherein each of the first conductive layers 221 has a first plug 331 on a portion of its top surface; and a conductive structure 345 connected to the plurality of first plugs 331, and wherein the conductive structure 345 is electrically isolated from the first gate structure 211.

[0102] In this embodiment, the first conductive layer 221 includes a first end 2211 and a second end 2212 , and the plurality of first plugs 331 are respectively located on the top surface of the first end 2211 of each of the first conductive layers 221 .

[0103] The conductive structure 345 includes: a plurality of parallel first plugs 332 and parallel second conductive layers 342 . The plurality of parallel first plugs 332 are respectively located on the top surface of the second end 2212 of each first conductive layer 241 . The parallel second conductive layers 342 are located on the top surfaces of the plurality of parallel first plugs 332 .

[0104] The following is a detailed description with reference to the accompanying drawings.

[0105] The substrate 200 also includes: an effective area II adjacent to the ineffective area I, the surface of the effective area II has mutually discrete second gate structures 212, and a plurality of the second gate structures 212 are arranged along the first direction X; the source-drain doped area 201 is also located in the substrate 200 on both sides of each of the second gate structures 212; and each of the first conductive layers 221 is also located on the surface of one or more of the source-drain doped areas 201 of the effective area II.

[0106] The semiconductor structure further includes: a first dielectric layer 220 located on the surface of the substrate 200, the first dielectric layer 220 being located on the surface of the source-drain doped region 201, the top surface and the sidewall surface of the first gate structure 211, and the sidewall surface of the first conductive layer 221; a second dielectric layer 230 located on the surface of the first dielectric layer 220, and the top surface of the second dielectric layer 230 is flush with the top surface of the first plug 331; a third dielectric layer 340 located on the surface of the second dielectric layer 230, the third dielectric layer 340 having a second conductive layer 341 located on the top surfaces of the first plugs 231, and the top surface of the third dielectric layer 340 is flush with the top surface of the second conductive layer 341.

[0107] In this embodiment, the parallel first plug 332 is located in the second dielectric layer 230 , and the top surface of the parallel first plug 332 is flush with the surface of the second dielectric layer 230 ; the parallel second conductive layer 342 is located in the third dielectric layer 340 , and the top surface of the parallel second conductive layer 342 is flush with the surface of the third dielectric layer 340 .

[0108] In this embodiment, the semiconductor structure is electrically connected to an external voltage through the second conductive layer 241 .

[0109] The conductive structure 345 includes parallel first plugs 332 and parallel second conductive layers 342 . The parallel first plugs 332 are located at the second ends 2212 of the first conductive layers 221 . The parallel second conductive layers 242 electrically connect the parallel first plugs 332 , so that the conductive structure 345 can electrically connect the first conductive layers 221 .

[0110] Since the conductive structure 345 electrically connects several first conductive layers 221, several conductive paths extending in parallel can be formed between the second conductive layer 341 and the first conductive layer 221. When the second conductive layer 341 is electrically connected to an external source voltage, the several conductive paths can increase the cross-sectional area of ​​the device for transmitting current from the second conductive layer 341 to the inactive region I (compared with a single conductive path), thereby facilitating the reduction of parasitic resistance. At the same time, the conductive structure 345 is electrically isolated from the first gate structure 211, thereby preventing the first gate structure 211 from being electrically connected to the second conductive layer 341 through the conductive structure 345, causing a short circuit in the first gate structure 211. In summary, the semiconductor structure can reduce parasitic resistance while having high electrical performance.

[0111] Figures 17 to 19 It is a schematic structural diagram of a semiconductor structure in yet another embodiment of the present invention.

[0112] Please refer to Figures 17 to 19 , Fig.17 for Fig.19 Schematic diagram of the cross section along the A-A1 tangent line. Fig.18 for Fig.19 Schematic diagram of the cross section along the tangent line A2-A3, Fig.19 for Fig.17 A top view along the F direction, and Fig.19The schematic diagram of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer is omitted. The semiconductor structure includes: a substrate 200, the substrate 200 includes an ineffective area I, and the surface of the ineffective area I has a plurality of first gate structures 211 separated from each other, and the substrate 200 on both sides of each first gate structure 211 has a source-drain doped region 201, and the plurality of first gate structures 211 are arranged along a first direction X; a plurality of first conductive layers 221 separated from each other, each of the first conductive layers 221 is located on the surface of one or more of the source-drain doped regions 201, and the top surface of the first gate structure 211 is lower than the top surface of the first conductive layer 221; a plurality of first plugs 231, and each of the first conductive layers 221 has a first plug 331 on a portion of its top surface; and a conductive structure 445 connected to the plurality of first plugs 331, and the conductive structure 445 is electrically isolated from the first gate structure 211.

[0113] In this embodiment, the first conductive layer 221 includes a first end (not shown in the figure) and a second end 2212 (not shown in the figure), and the first plugs 331 are respectively located on the top surface of the first end 2211 of each of the first conductive layers 221 .

[0114] The conductive structure 445 includes: a plurality of parallel first plugs 332 and parallel second conductive layers 342, wherein the plurality of parallel first plugs 332 are respectively located on the top surface of the second end 2212 of each first conductive layer 241, and the parallel second conductive layer 342 is located on the top surface of the plurality of parallel first plugs 332; a plurality of parallel second plugs 452 and parallel third conductive layers 462, wherein the plurality of parallel second plugs 452 are respectively located on the top surface of the second conductive layer 341 and the surface of the top 342 of the parallel second conductive layer, and the parallel third conductive layer 462 is located on the surfaces of the plurality of parallel second plugs 452.

[0115] The conductive structure 445 can electrically connect the second conductive layer 341 not only through the parallel first plugs 332 and the parallel second conductive layer 342, but also through the parallel second plugs 452 and the parallel third conductive layer 462, thereby further increasing the number of conductive paths extending in parallel between the second conductive layer 341 and the first conductive layer 331. The more conductive paths there are between the second conductive layer and the first conductive layer 221, the more conducive it is to increase the cross-sectional area of ​​the device used to transmit current from the second conductive layer 341 to the inactive region I (compared with a single conductive path), thereby further facilitating the reduction of parasitic resistance.

[0116] The following is a detailed description with reference to the accompanying drawings.

[0117] The substrate 200 also includes: an effective area II adjacent to the ineffective area I, the surface of the effective area II has mutually discrete second gate structures 212, and a plurality of the second gate structures 212 are arranged along the first direction X; the source-drain doped area 201 is also located in the substrate 200 on both sides of each of the second gate structures 212; and each of the first conductive layers 221 is also located on the surface of one or more of the source-drain doped areas 201 of the effective area II.

[0118] The semiconductor structure further includes: a first dielectric layer 220 located on the surface of the substrate 200, the first dielectric layer 220 being located on the surface of the source-drain doped region 201, the top surface and the sidewall surface of the first gate structure 211, and the sidewall surface of the first conductive layer 221; a second dielectric layer 230 located on the surface of the first dielectric layer 220, and the top surface of the second dielectric layer 230 is flush with the top surface of the first plug 331; a third dielectric layer 340 located on the surface of the second dielectric layer 230, and the third dielectric layer 340 has a plurality of second conductive layers located on the top surfaces of the first plug 231. The third dielectric layer 341 is provided with a third dielectric layer 340, and the top surface of the third dielectric layer 340 is flush with the top surface of the second conductive layer 341; a fourth dielectric layer 450 is provided on the surface of the third dielectric layer, and a plurality of parallel second plugs 452 are provided in the fourth dielectric layer 450, and the top surface of the fourth dielectric layer 450 is flush with the top surface of the parallel second plugs 152; a fifth dielectric layer 460 is provided on the surface of the fourth dielectric layer 450, and the fifth dielectric layer 460 has the parallel third conductive layers 462, and the top surface of the sixth dielectric layer 460 is flush with the top surface of the parallel third conductive layers 462.

[0119] In this embodiment, the semiconductor structure is electrically connected to an external voltage through the second conductive layer 241 .

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising an ineffective area, a surface of the ineffective area having a plurality of first gate structures separated from each other, the substrate having source and drain doping regions on both sides of each of the first gate structures, and the plurality of first gate structures are arranged along a first direction; A plurality of mutually independent first conductive layers, a surface of a source-drain doped region has a first conductive layer, and a top surface of the first gate structure is lower than a top surface of the first conductive layer; A plurality of first plugs, wherein each of the top surfaces of the first conductive layer portions has a first plug; A conductive structure connected to all of the first plugs, wherein the conductive structure is electrically isolated from the first gate structure.

2. The semiconductor structure according to claim 1, wherein: Also includes: A first dielectric layer located on the surface of the substrate, wherein the first dielectric layer is located on the surface of the source and drain doped regions, the top surface and sidewall surface of the first gate structure, and the sidewall surface of the first conductive layer; A second dielectric layer is located on the surface of the first dielectric layer, and the top surface of the second dielectric layer is flush with the top surface of the first plug; A third dielectric layer is located on the surface of the second dielectric layer, wherein the third dielectric layer has a second conductive layer located on the top surfaces of the first plugs, and the top surface of the third dielectric layer is flush with the top surface of the second conductive layer.

3. The semiconductor structure according to claim 2, wherein: The conductive structure contacts a plurality of first plug sidewall surfaces and extends along a first direction.

4. The semiconductor structure according to claim 3, characterized in that The top surface of the conductive structure is flush with the top surface of the second dielectric layer.

5. The semiconductor structure according to claim 2, wherein: The first conductive layer includes a first end and a second end, and the plurality of first plugs are respectively located on the top surface of the first end of each of the first conductive layers.

6. The semiconductor structure according to claim 5, characterized in that The conductive structure comprises: a plurality of parallel first plugs and parallel second conductive layers, wherein the plurality of parallel first plugs are respectively located on the top surface of the second end of each first conductive layer, and the parallel second conductive layers are located on the top surfaces of the plurality of parallel first plugs.

7. The semiconductor structure according to claim 6, wherein: The conductive structure further includes: a plurality of parallel second plugs and a parallel third conductive layer, wherein the plurality of parallel second plugs are respectively located on the top surface of the second conductive layer and the top surface of the parallel second conductive layer, and the parallel third conductive layer is located on the surfaces of the plurality of parallel second plugs.

8. The semiconductor structure according to claim 1, wherein: The substrate also includes: an effective area adjacent to the ineffective area, the surface of the effective area having mutually discrete second gate structures, and a plurality of the second gate structures are arranged along a first direction; the source-drain doped areas are also located in the substrate on both sides of each of the second gate structures; and each of the first conductive layers is also located on the surface of one or more of the source-drain doped areas of the effective area.

9. The semiconductor structure according to claim 8, characterized in that When the active region is located at both sides of the inactive region, the conductive structure is located above the second gate structure.

10. The semiconductor structure according to claim 2, wherein: The second conductive layer is electrically connected to an external voltage source.

11. A method for forming a semiconductor structure according to any one of claims 1 to 10, characterized in that: include: Providing a substrate, the substrate comprising an ineffective area, the surface of the ineffective area having a plurality of first gate structures separated from each other, the substrate having source and drain doping regions on both sides of each of the first gate structures, and the plurality of first gate structures being arranged along a first direction; A plurality of first conductive layers separated from each other are formed on the surface of the source-drain doped region, one surface of the source-drain doped region has one first conductive layer, a plurality of the first conductive layers and a plurality of first gate structures are arranged alternately, and a top surface of the first gate structure is lower than a top surface of the first conductive layer; Forming a plurality of first plugs on the top surface of the first conductive layer, and each of the top surfaces of the first conductive layer portions has a first plug; A conductive structure is formed to be electrically connected to all of the first plugs and is electrically isolated from the first gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: After forming the first gate structure and the source-drain doped regions and before forming the first plug, a first dielectric layer is formed on the surface of the substrate, the first dielectric layer being located on the surface of the source-drain doped regions, the top surface and the sidewall surface of the first gate structure; a plurality of the first conductive layers are formed in the first dielectric layer; After forming the first conductive layer, forming a second dielectric layer on the surface of the first dielectric layer and the first conductive layer, and the top surface of the second dielectric layer is flush with the top surface of the first plug; A third dielectric layer is formed on the surface of the second dielectric layer. The third dielectric layer has a second conductive layer located on the top surfaces of the first plugs, and the top surface of the third dielectric layer is flush with the top surface of the second conductive layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the process of forming the first plug, the conductive structure is formed, and the conductive structure is in contact with the side wall surface of the first plug, and the conductive structure extends along the first direction.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the conductive structure and the first plug comprises: after forming the second dielectric layer and before forming the third dielectric layer, forming a first mask layer on the surface of the second dielectric layer, wherein the first mask layer exposes a portion of the surface of the second dielectric layer; using the first mask layer as a mask, etching the second dielectric layer until a portion of the top surface of the first conductive layer is exposed, forming a first opening and a second opening in the second dielectric layer, wherein the first opening exposes the top surface of the first conductive layer, the second opening is located between adjacent first openings, and the first opening and the second opening are connected; forming a first plug in the first opening, and forming a conductive structure in the second opening.

15. The method for forming a semiconductor structure according to claim 12, wherein: The first conductive layer comprises: a first end and a second end, and the first plugs are respectively located on the top surface of the first end of the first conductive layer; the formation process of the conductive structure comprises: after forming the second dielectric layer and before forming the third dielectric layer, forming parallel first plugs in the second dielectric layer, and the parallel first plugs are respectively located on the top surface of the second end of the first conductive layer; after forming the parallel first plugs, forming a third dielectric layer on the surface of the second dielectric layer and the surface of the parallel first plugs, and forming parallel second conductive layers in the third dielectric layer, and the parallel second conductive layers are located on the top surfaces of a plurality of parallel first plugs.

16. The method for forming a semiconductor structure according to claim 15, wherein: In the process of forming the first plug, the parallel first plug is formed; in the process of forming the second conductive layer, the parallel second conductive layer is formed.

17. The method for forming a semiconductor structure according to claim 15, wherein: The formation process of the conductive structure further includes: after forming the parallel second conductive layer, forming a fourth dielectric layer on the surface of the second conductive layer and the surface of the third dielectric layer; forming a plurality of parallel second plugs in the fourth dielectric layer, and the parallel second plugs are respectively located on the top surface of the second conductive layer and the top surface of the parallel second conductive layer; forming a fifth dielectric layer on the surface of the fourth dielectric layer and the surface of the parallel second plugs; forming a parallel third conductive layer in the fifth dielectric layer, and the parallel third conductive layer is located on a plurality of the parallel second plugs.

Images