Design method of parameterized customized transistor layout and chip layout structure

A design method and technology of layout structure, applied in the field of electronic information, can solve the problems of non-optimal area, poor versatility, and failure to consider the layout of layout design, etc., so as to reduce visual fatigue, make layout units concise and clear, and improve layout design efficiency effect

Pending Publication Date: 2021-11-26
珠海昇生微电子有限责任公司
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Problems solved by technology

[0004] 1. Only simple functions can be realized, there are too few parameters that can be adjusted, and the area is not optimal
[0005] 2. The layout in the layout design is not considered, and the versatility is not

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  • Design method of parameterized customized transistor layout and chip layout structure

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[0023] In order to make the objects, technical solutions, and advantages of the present invention more clear, the technical solutions of the embodiments of the present invention will be described in contemplation in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are embodiments of the invention, not all of the embodiments. Based on the embodiments described herein, all other embodiments obtained without the need for creative labor without the need for creative labor.

[0024] See figure 1 A parametric custom transistor layout design method of the present invention, when the basic structure and parameters of the selection transistor, the transistor to generate customized layout unit, includes the following steps:

[0025] First, a step S1, the smallest transistor layout design the basic structure of the transistor unit. Wherein the basic structure of the transistor, to determine all the necessary design level, and can...

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Abstract

The invention provides a design method of a parameterized customized transistor layout. The design method comprises the following steps: designing a minimum transistor layout unit according to a basic structure of a transistor; determining the grid width and the number of grid contact holes according to the channel length, determining the number of active area contact holes according to the channel width, copying the graph according to the number of the parallel units, and determining the copying distance; determining a gate contact hole design rule according to the gate contact hole design parameters; determining an active area contact hole design rule according to the active area contact hole design parameters; and generating a customized layout structure. The invention has flexibility and usability, can meet the requirements of customized layout, and can realize multi-parameter adjustability.

Description

technical field [0001] The invention relates to the field of electronic information technology, in particular to a method for designing a parametric custom transistor layout and a chip layout structure applied to the method. Background technique [0002] In the layout design process of the back-end analog circuit of the integrated circuit, the transistor is the most commonly used basic device, and the transistor layout design is the basic layout unit. The adjustable parameter transistor layout unit in the design package provided by the integrated circuit manufacturer can only simply set some basic parameters such as the channel length and channel width of the transistor. After only adjusting these simple parameters, it cannot be realized according to the layout position of the layout. Customized layout units. As a result, layout design efficiency is greatly reduced. Therefore, there is an urgent need for a flexible, concise, multi-parameter transistor layout design unit fo...

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Application Information

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IPC IPC(8): G06F30/392G06F30/36
CPCG06F30/392G06F30/36
Inventor 朱观禄
Owner 珠海昇生微电子有限责任公司
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