Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate having a fin; forming a pseudo gate structure across the fin on the substrate, and the pseudo gate structure having a second protective layer on the sidewall surface; performing a modification treatment on the second protective layer so that the second protective layer forms a second modified layer; and performing a cleaning process. By selecting a suitable modification treatment, the etching rate of the second modified layer during the cleaning process is within a preset range, that is, the etching rate of the second modified layer by the cleaning process is relatively low, so that the thickness of the sidewall of the pseudo gate structure is reduced to a relatively small extent, so that the angle of the corner area where the fin and the pseudo gate structure meet is relatively small, thereby improving the electrical performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of semiconductor technology, the traditional planar metal-oxide semiconductor field effect transistor, referred to as metal-oxide-semiconductor field-effect transistor (MOSFET), has weakened its ability to control channel current, resulting in serious leakage current. Fin field effect transistor (Fin Field-Effect Transistor) is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewalls of the fin, and source and drain doped regions in the fin on both sides of the gate structure.

[0003] The gate structure is formed by: forming a gate material film covering the fin on a substrate; forming a patterned layer on the surface of the gate material film; using the patterned layer as a mask, etching the gate material film until the substrate surface is exposed to form the gate structure.

[0004] However, the performance of the existing FinFETs needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate has a fin; forming a pseudo gate structure spanning the fin on the substrate, and the side wall surface of the pseudo gate structure has a second protective layer; modifying the second protective layer to form a second modified layer; performing a cleaning process, and the etching rate of the second modified layer by the cleaning process is within a preset range.

[0007] Optionally, the etching rate of the second modified layer by the cleaning process is within a preset range.

[0008] Optionally, the surface of the fin has a first protective layer.

[0009] Optionally, the first protective layer and the second protective layer are porous materials, and the porosity of the second protective layer material is greater than the porosity of the first protective layer material.

[0010] Optionally, the modification treatment further causes the first protective layer to form a first modified layer, and the etching rate of the first modified layer in the cleaning process is within a preset range.

[0011] Optionally, the process for forming the first protective layer includes: an atomic layer deposition process.

[0012] Optionally, the material of the first protective layer includes: silicon oxide.

[0013] Optionally, the material of the second protective layer includes: silicon oxide.

[0014] Optionally, the method for forming the dummy gate structure includes: forming a dummy gate material film covering the top surface and side wall surface of the fin on the substrate; etching the dummy gate material film to form a dummy gate structure across the fin on the substrate.

[0015] Optionally, during the process of etching the dummy gate material film, the second protection layer is formed on the side wall surface of the dummy gate structure.

[0016] Optionally, during the process of etching the dummy gate material film, byproducts are generated on the surface of the dummy gate structure or the surface of the fin.

[0017] Optionally, the modification treatment includes: chemical treatment.

[0018] Optionally, the chemical treatment is a nitriding treatment; the parameters of the nitriding treatment include: the gas introduced includes nitrogen, the flow rate of the nitrogen is 300 standard ml / min to 1000 standard ml / min, the pressure is 10 mTorr to 100 mTorr, the source power is 300 W to 1000 W, and the time is 5 seconds to 30 seconds.

[0019] Optionally, the modification treatment includes: heat treatment.

[0020] Optionally, the heat treatment process includes: rapid thermal annealing; the parameters of the rapid thermal annealing include: a temperature range of 700 degrees Celsius to 900 degrees Celsius, and a time range of 5 seconds to 20 seconds.

[0021] Optionally, the cleaning process includes: a wet etching process; parameters of the wet etching process include: an etching solution includes a dilute hydrofluoric acid solution, and a volume ratio of water to hydrofluoric acid ranges from 90:1 to 110:1.

[0022] Optionally, the method of etching the pseudo gate material film to form a pseudo gate structure across the fin on the substrate includes: forming a patterned layer on the surface of the pseudo gate material film, the patterned layer being used to define the position and size of the pseudo gate structure; using the patterned layer as a mask, etching the pseudo gate material film until the surface of the substrate is exposed, forming the pseudo gate structure on the substrate, and the pseudo gate structure is located on a portion of the top and side wall surfaces of the fin.

[0023] Optionally, the process of etching the pseudo gate material film using the patterned layer as a mask includes: a dry etching process; the parameters of the dry etching process include: etching gases including chlorine, hydrogen bromide, oxygen and nitrogen, the flow rate of the chlorine is 100 standard ml / min to 300 standard ml / min, the flow rate of hydrogen bromide is 100 standard ml / min to 500 standard ml / min, the flow rate of oxygen is 40 standard ml / min to 100 standard ml / min, the flow rate of nitrogen is 40 standard ml / min to 500 standard ml / min, the pressure is 50 mTorr to 120 mTorr, the high-frequency power is 400 W to 700 W, and the low-frequency voltage is 800 V to 1200 V.

[0024] Optionally, the method further includes: after the cleaning process, forming a filling layer on the surface of the fin and the surface of the dummy gate structure.

[0025] Optionally, the filling layer is formed by a process including a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0026] Optionally, the filling layer has a thickness ranging from 5 angstroms to 30 angstroms.

[0027] Optionally, the material of the filling layer is an insulating material; the insulating material includes: silicon nitride, silicon oxide, silicon oxynitride or silicon oxycarbide.

[0028] Optionally, the width of the fin is in a range of 10 nanometers to 15 nanometers.

[0029] Optionally, a distance between adjacent fins ranges from 50 nanometers to 70 nanometers.

[0030] Optionally, the width of the dummy gate structure is 15 nanometers to 20 nanometers.

[0031] Optionally, the spacing between adjacent dummy gate structures ranges from 50 nanometers to 70 nanometers.

[0032] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, comprising: a substrate having a fin portion on the substrate; a gate structure spanning the fin portion on the substrate, and a second modified layer on the sidewall surface of the gate structure.

[0033] Optionally, the surface of the fin has a first modified layer.

[0034] Optionally, the gate structure includes a gate layer, and a material of the gate layer includes: polysilicon or metal.

[0035] Optionally, it also includes: a filling layer located on the surface of the gate structure and the surface of the fin.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] In the method for forming a semiconductor structure provided by the technical solution of the present invention, by modifying the second protective layer, the material of the second protective layer is changed to form a second modified layer. By selecting a suitable modification treatment, the etching rate of the second modified layer during the cleaning process is within a preset range, that is, the etching rate of the second modified layer by the cleaning process is small, so that the dimensional degree of the reduction in the thickness of the sidewall of the pseudo gate structure is small, so that the angle of the corner area where the fin and the pseudo gate structure meet is small, that is, the angle is close to a right angle, which means that the amount of residue located in the corner area is small, thereby improving the electrical performance of the formed semiconductor structure.

[0038] Furthermore, by modifying the first protective layer, the material of the first protective layer is changed to form a first modified layer. By selecting a suitable modification process, the etching rate of the first modified layer during the cleaning process is within a preset range, that is, the etching rate of the first modified layer during the cleaning process is relatively low, so that the sidewall thickness of the fin is reduced to a relatively small extent, so that the angle of the corner area where the fin and the pseudo gate structure meet is relatively small, thereby improving the electrical performance of the formed semiconductor structure.

[0039] Furthermore, after the chemical treatment, the density of the first modified layer and the second modified layer formed are both high, so that the etching rate of the first modified layer and the etching rate of the second modified layer in the cleaning process are both low, so that the angle change of the corner area where the fin and the pseudo gate structure meet is smaller, thereby improving the electrical performance of the formed semiconductor structure.

[0040] Furthermore, through the heat treatment, the density of the second protective layer material is improved to form the second modified layer, so that the etching rate of the second modified layer with higher density in the cleaning process is lower, so that the angle change of the corner area where the fin and the pseudo gate structure meet is smaller, thereby improving the electrical performance of the formed semiconductor structure.

[0041] Furthermore, since some defects will be generated on the surface of the fin and the surface of the pseudo gate structure during the process of removing impurities generated by etching the pseudo gate material film, and at the same time, the cleaning process will aggravate the defects on the surface of the fin and the surface of the pseudo gate structure, a filling layer is formed on the surface of the fin and the side wall surface of the pseudo gate structure, which can fill the defects on the surface of the fin and the surface of the pseudo gate structure, making the side wall morphology of the fin and the side wall morphology of the pseudo gate structure smoother, thereby further making the angle of the corner area where the fin and the pseudo gate structure intersect close to a right angle, thereby improving the electrical performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figures 1 to 5 It is a schematic structural diagram of each step of a method for forming a semiconductor structure;

[0043] Figures 6 to 13 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0044] Figures 14 to 17 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0045] First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. Figures 1 to 5 The present invention is a structural schematic diagram of each step of a method for forming a conventional semiconductor structure.

[0046] Please refer to Figure 1 , providing a substrate 100 , wherein the substrate 100 has a fin 110 , and the surface of the fin 110 has a first protective layer 111 .

[0047] Please refer to Figure 2 , a dummy gate material film 120 is formed on the substrate 100 to cover the top surface and the sidewall surface of the fin 110 .

[0048] Please refer to Figure 3 , the dummy gate material film 120 is etched to form a dummy gate structure 130 across the fin 110 on the substrate 100 , and the sidewall surface of the dummy gate structure 130 has a second protection layer 131 .

[0049] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 The cross-sectional diagram along the A-A1 tangent line direction shows that a cleaning process is used to remove impurities generated by etching the dummy gate material film 120 .

[0050] In the above method, the first protective layer 111 is used to protect the surface of the fin 110, and protect the surface of the fin 110 from being etched in subsequent processes. In the process of etching the pseudo gate material film 120 and forming a pseudo gate structure 130 across the fin 110 on the substrate 100, on the one hand, in order to ensure that the etching process used has good anisotropy and the sidewall of the formed pseudo gate structure 130 can be well perpendicular to the surface of the substrate 100, a second protective layer 131 will be formed on the sidewall surface of the pseudo gate structure 130 during the etching process. The second protective layer 131 is a byproduct generated during the etching of the pseudo gate material film 120, and the material of the second protective layer 131 is a polymer of silicon oxide; on the other hand, etching the pseudo gate material film 120 will also deposit some etching byproducts, organic polymers and other impurities on the surface of the pseudo gate structure 130. The impurities generated by etching the pseudo gate material film 120 are removed through a cleaning process, thereby reducing the impact on the performance of the semiconductor structure.

[0051] Typically, the material of the first protective layer 111 located on the surface of the fin 110 is silicon oxide, and the material of the second protective layer 131 formed during the etching of the pseudo gate material film 120 is silicon oxide. However, since the first protective layer 111 is formed by an atomic layer deposition process, the first protective layer 111 has good compactness to ensure that the first protective layer 111 fully protects the surface of the fin 110. The second protective layer 131 is formed by a polymer formed by the reaction of oxygen in the etching gas introduced during the etching process with silicon elements in the pseudo gate material film 120, and is deposited on the surface of the pseudo gate structure 130. Therefore, the second protective layer 131 has poor compactness. Therefore, in the process of removing the impurities, the etching rate of the second protective layer 131 is relatively high, which may easily cause one side of the corner area where the fin 110 and the pseudo gate structure 130 meet to be concave, and the said side is the side where the side wall of the pseudo gate structure 130 is located, resulting in the angle a of the corner area where the fin 110 and the pseudo gate structure 130 meet to become larger, so that the amount of residue in the corner area is relatively large, thereby reducing the electrical performance of the formed semiconductor structure.

[0052] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein the second protective layer is modified to form a second modified layer; and a cleaning process is performed. By selecting a suitable modification process, the etching rate of the second modified layer during the cleaning process is within a preset range, that is, the etching rate of the second modified layer by the cleaning process is small, so that the thickness of the sidewall of the pseudo gate structure is reduced to a small extent, so that the angle of the corner area at the junction of the fin and the pseudo gate structure changes less, thereby improving the electrical performance of the formed semiconductor structure.

[0053] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Figures 6 to 13 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0055] Please refer to Figure 6 , providing a substrate 200 having a fin 210 thereon.

[0056] In this embodiment, the base 200 and the fin 210 located on the surface of the base 200 are formed by etching an initial substrate. In other embodiments, a fin material layer is formed on the base, and then the fin material layer is patterned to form the fin 210.

[0057] In this embodiment, the material of the substrate 200 and the fin 210 is single crystal silicon. The substrate may also be polycrystalline silicon or amorphous silicon. The substrate material may also be a semiconductor material such as germanium, silicon germanium, gallium arsenide, etc. The substrate may also be a semiconductor-on-insulator structure, which includes an insulator and a semiconductor material layer located on the insulator, wherein the material of the semiconductor material layer includes a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or indium gallium arsenide.

[0058] The width of the fin 210 is in a range of 10 nanometers to 15 nanometers.

[0059] The width refers to a dimension perpendicular to the extending direction of the fin 210 .

[0060] The spacing between adjacent fins 210 ranges from 50 nm to 70 nm.

[0061] The surface of the fin 210 has a first protection layer 211 .

[0062] The first protection layer 211 is used to prevent the fin 210 from being damaged in a subsequent etching process.

[0063] The material of the first protective layer 211 includes silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the first protective layer 211 is silicon oxide.

[0064] The first protective layer 211 is made of porous material.

[0065] The formation process of the first protection layer 211 includes: atomic layer deposition process.

[0066] The atomic layer deposition process is to deposit at a thickness of atomic level, so that the first protective layer 211 formed has high density, that is, low porosity, which is conducive to the first protective layer 211 being able to effectively protect the surface of the fin 210.

[0067] Specifically, the surface of the substrate 200 further has an isolation layer 201 , the top surface of the isolation layer 201 is lower than the top surface of the fin 210 , and the isolation layer 201 covers a portion of the sidewall surface of the fin 210 .

[0068] The isolation layer 201 is used to achieve electrical isolation between different semiconductor devices.

[0069] Next, a dummy gate structure is formed on the substrate 200 across the fin 210, and the sidewall surface of the dummy gate structure has a second protective layer. For a specific method of forming the dummy gate structure, please refer to Figures 7 to 9 .

[0070] Please refer to Figure 7 , a dummy gate material film 220 is formed on the substrate 200 to cover the top surface and the sidewall surface of the fin 210 .

[0071] The dummy gate material film 220 provides material for subsequently forming a dummy gate structure.

[0072] In this embodiment, the dummy gate material film 220 includes: a dummy gate dielectric material film and a dummy gate electrode material film located on the surface of the dummy gate dielectric material film.

[0073] The method for forming the pseudo gate material film 220 includes: forming a pseudo gate dielectric material film (not shown in the figure) on the substrate 200, wherein the pseudo gate dielectric material film covers the surface of the fin 210 and the isolation layer 201; and forming a pseudo gate electrode material film (not shown in the figure) on the surface of the pseudo gate dielectric material film.

[0074] In this embodiment, the material of the dummy gate dielectric material film is silicon oxide, and the material of the dummy gate electrode material film is polysilicon.

[0075] Please refer to Figure 8 and Fig. 9 , Fig. 9 for Figure 8 The cross-sectional schematic diagram along the B-B1 tangent line direction shows that the dummy gate material film 220 is etched to form a dummy gate structure 230 across the fin 210 on the substrate 200 .

[0076] The method for etching the pseudo gate material film 220 to form a pseudo gate structure 230 across the fin 210 on the substrate 200 includes: forming a patterned layer (not shown in the figure) on the surface of the pseudo gate material film 220, and the patterned layer is used to define the position and size of the pseudo gate structure; using the patterned layer as a mask, etching the pseudo gate material film 220 until the surface of the substrate 200 is exposed, forming the pseudo gate structure 230 on the substrate 200, and the pseudo gate structure 230 is located on a portion of the top and side wall surfaces of the fin 210.

[0077] Specifically, the dummy gate material film 220 is etched until the isolation layer 201 and the surface of the fin 210 are exposed.

[0078] The width of the dummy gate structure 230 is 15 nanometers to 20 nanometers.

[0079] The distance between adjacent dummy gate structures 230 ranges from 50 nanometers to 70 nanometers.

[0080] The process of etching the pseudo gate material film 220 using the patterned layer as a mask includes: a dry etching process; the parameters of the dry etching process include: etching gases include chlorine, hydrogen bromide, oxygen and nitrogen, the flow rate of the chlorine is 100 standard ml / min to 300 standard ml / min, the flow rate of hydrogen bromide is 100 standard ml / min to 500 standard ml / min, the flow rate of oxygen is 40 standard ml / min to 100 standard ml / min, the flow rate of nitrogen is 40 standard ml / min to 500 standard ml / min, the pressure is 50 mTorr to 120 mTorr, the high-frequency power is 400 W to 700 W, and the low-frequency voltage is 800 V to 1200 V.

[0081] It should be noted that, during the process of etching the dummy gate material film, the second protection layer 231 is formed on the sidewall surface of the dummy gate structure 230 .

[0082] An included angle b between the sidewall of the dummy gate structure 230 and the sidewall of the fin 210 at a corner region is close to a right angle.

[0083] The material of the second protection layer 231 is silicon oxide.

[0084] In this embodiment, the material of the first protective layer 211 is silicon oxide, the material of the second protective layer 231 is silicon oxide, and the materials of the first protective layer and the second protective layer 231 are porous materials, and the porosity of the second protective layer 231 is greater than the porosity of the first protective layer 211.

[0085] During the etching process of the dummy gate material film 220 , byproducts are generated on the surface of the dummy gate structure 220 or the surface of the fin 210 .

[0086] Please refer to Fig.10 , Fig.10 and Figure 8 The viewing direction is the same as that of the second protective layer 231, and the second protective layer 231 is modified to form a second modified layer 232.

[0087] The modification treatment includes: chemical treatment.

[0088] In this embodiment, the chemical treatment is nitriding treatment; the parameters of the nitriding treatment include: the gas introduced includes nitrogen, the flow rate of nitrogen is 300 standard ml / min to 1000 standard ml / min, the pressure is 10 mTorr to 100 mTorr, the source power is 300 W to 1000 W, and the time is 5 seconds to 30 seconds.

[0089] In this embodiment, the material of the second protective layer 231 is silicon oxide, and the material of the second modified layer 232 formed after the nitridation treatment is silicon oxynitride.

[0090] Through the modification treatment, the second modified layer 232 has a higher density, which is beneficial to reducing the etching rate of the second modified layer 232 in the subsequent cleaning process, thereby ensuring that the etching rate of the second modified layer 232 is within a preset range.

[0091] It should be noted that the modification process also causes the first protective layer 211 to form a first modified layer 212 .

[0092] In this embodiment, the material of the first protective layer 211 is silicon oxide, and the material of the first modified layer 212 formed after the nitridation treatment is silicon oxynitride.

[0093] Through the modification treatment, the first modified layer 212 has a higher density, which is beneficial to lower the etching rate of the first modified layer 212 in the subsequent cleaning process, thereby ensuring that the etching rate of the first modified layer 212 is within a preset range.

[0094] After the chemical treatment, the first modified layer 212 and the second modified layer 232 are formed with high density, so that the etching rate of the first modified layer 212 and the etching rate of the second modified layer 232 in the cleaning process are both low, so that the angle b in the corner area where the fin 210 and the pseudo gate structure 230 meet changes less, thereby improving the electrical performance of the formed semiconductor structure.

[0095] Please refer to Fig.11 and Fig.12 , Fig.12 for Fig.11 Schematic diagram of the cross-section along the B-B1 tangent line, showing the cleaning process.

[0096] The etching rate of the second modified layer 232 by the cleaning process is within a preset range.

[0097] The cleaning process includes: a wet etching process; the parameters of the wet etching process include: the etching solution includes a dilute hydrofluoric acid solution, and the volume ratio of water to hydrofluoric acid ranges from 90:1 to 110:1.

[0098] The cleaning process is used to remove byproducts generated during the formation of the dummy gate structure 230, improve the cleanliness of the surface of the fin 210, the surface of the dummy gate structure 230 and the surface of the substrate 200, thereby improving the performance of the formed semiconductor structure.

[0099] By selecting a suitable modification treatment, the second protective layer 231 is formed into the second modified layer 232. The etching rate of the second modified layer 232 by the cleaning process is within a preset range, and the etching rate of the second modified layer 232 by the cleaning process is small, so that the thickness reduction degree of the second modified layer 232 in the corner area and the second modified layer 232 in the adjacent corner area is small. The dimensional reduction degree of the sidewall thickness of the dummy gate structure 230 is small, so that the angle b of the corner area where the fin 210 and the dummy gate structure 230 intersect is small, that is, the angle is close to a right angle, which means that the amount of residue located in the corner area is small, thereby improving the electrical performance of the formed semiconductor structure.

[0100] In this embodiment, the etching rate of the first modified layer 212 in the cleaning process is within a preset range.

[0101] Similarly, by selecting a suitable modification treatment, the first protective layer 211 is formed into the first modified layer 212. The etching rate of the first modified layer 212 by the cleaning process is within a preset range, and the etching rate of the first modified layer 212 by the cleaning process is small, so that the thickness reduction degree of the first modified layer 212 in the corner area and the first modified layer 212 in the adjacent corner area is small. The dimensional reduction degree of the sidewall thickness of the dummy gate structure 230 is small, so that the angle b of the corner area where the fin 210 and the dummy gate structure 230 intersect is small, that is, the angle b is close to a right angle, which means that the amount of residue located in the corner area is small, thereby improving the electrical performance of the formed semiconductor structure.

[0102] Please refer to Fig.13 , Fig.13 and Fig.11 The viewing direction is the same as that of FIG. 1 . After the cleaning process, a filling layer 240 is formed on the surface of the fin 210 and the surface of the dummy gate structure 230 .

[0103] The formation process of the filling layer 240 includes: a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0104] In this embodiment, the filling layer 240 is formed by an atomic layer deposition process.

[0105] The atomic layer deposition process is to deposit at a thickness of atomic level, which is beneficial for the filling layer 240 to fill the surface defects of the fin 210 and the dummy gate structure 230 and improve the flatness of the surface of the fin 210 and the dummy gate structure 230 .

[0106] The thickness of the filling layer 240 ranges from 5 angstroms to 30 angstroms.

[0107] The filling layer 240 is made of an insulating material; the insulating material includes silicon nitride, silicon oxide, silicon oxynitride or silicon oxycarbide.

[0108] In this embodiment, the material of the filling layer 240 is silicon oxide.

[0109] Since some defects will be generated on the surface of the fin 210 and the surface of the pseudo gate structure 230 during the process of removing the impurities generated by etching the pseudo gate material film 220, and the cleaning process will aggravate the defects on the surface of the fin and the pseudo gate structure, a filling layer 240 is formed on the surface of the fin 210 and the side wall surface of the pseudo gate structure 230 to fill the defects on the surface of the fin 210 and the surface of the pseudo gate structure 230, so that the side wall morphology of the fin 310 and the side wall morphology of the pseudo gate structure 230 are smoother, thereby further making the angle b of the corner area where the fin 210 and the pseudo gate structure 230 intersect close to a right angle, thereby improving the electrical performance of the formed semiconductor structure.

[0110] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please refer to Fig.13 , comprising: a substrate 200 having a fin 210 thereon; a gate structure (not shown in the figure) spanning the fin 210 thereon, and a second modified layer 232 on the sidewall surface of the gate structure.

[0111] In this embodiment, the surface of the fin 210 has a first modified layer 212 .

[0112] The gate structure includes a gate layer, and the material of the gate layer includes: polysilicon or metal.

[0113] In this embodiment, the semiconductor structure further includes: a filling layer 240 located on the surface of the gate structure and the surface of the fin.

[0114] It should be noted that the gate structure is a structure formed by using a gate-last process on the dummy gate structure 230 .

[0115] Figures 14 to 17 1 is a schematic diagram of the formation process of a semiconductor structure of another embodiment of the present invention. The difference between this embodiment and the above embodiment is that the modification process is different. Therefore, the formation process of the semiconductor structure is further described on the basis of the above embodiment. Fig. 9 Continue to refer to Fig.14 .

[0116] Please refer to Fig.14 , the second protective layer 231 is modified so that the second protective layer 231 forms a second modified layer 332 .

[0117] The modification treatment includes: heat treatment.

[0118] In this embodiment, the heat treatment process is rapid thermal annealing; the parameters of the rapid thermal annealing include: a temperature range of 700 degrees Celsius to 900 degrees Celsius, and a time range of 5 seconds to 20 seconds.

[0119] In this embodiment, the material of the first protective layer 211 is silicon oxide, the material of the second protective layer 231 is silicon oxide, and the materials of the first protective layer 211 and the second protective layer 231 are porous materials, and the porosity of the second protective layer 231 is greater than the porosity of the first protective layer 211.

[0120] Through the modification treatment, the porosity of the second modified layer 232 is reduced, that is, the density of the second modified layer 232 is improved, which is beneficial to reducing the etching rate of the second modified layer 232 in the subsequent cleaning process, thereby satisfying that the etching rate of the second modified layer 232 is within a preset range.

[0121] The modification process also causes the first protective layer 211 to form a first modified layer 312 .

[0122] Since the porosity of the first protective layer 211 is relatively small, the porosity of the first modified layer 312 remains unchanged or decreases after the modification treatment.

[0123] Please refer to Fig.15 and 16 , Fig.16 for Fig.15 A cross-sectional schematic diagram along the C-C1 tangent line direction shows a cleaning process, wherein the etching rate of the second modified layer 332 by the cleaning process is within a preset range.

[0124] The cleaning process is the same as the cleaning process in the above embodiment and will not be described again here.

[0125] In this embodiment, the etching rate of the first modified layer 312 in the cleaning process is within a preset range.

[0126] Please refer to Fig.17 After the cleaning process, a filling layer 340 is formed on the surface of the fin 210 and the surface of the dummy gate structure 230 .

[0127] The material and formation process of the filling layer 340 are the same as those of the filling layer 240 in the above embodiment, and will not be described in detail here. Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having a fin thereon; Forming a dummy gate structure across the fin on the substrate, wherein the sidewall surface of the dummy gate structure has a second protective layer; Performing a modification treatment on the second protective layer so that the second protective layer forms a second modified layer, wherein the second modified layer has a greater density than the second protective layer; Perform cleaning process; The modification treatment improves the density of the second protective layer material to form the second modified layer, so that the cleaning process has a low etching rate for the second modified layer with high density, which makes the angle of the corner area where the fin and the pseudo gate structure meet change little, and the angle is close to a right angle, thereby reducing the amount of residue in the corner area.

2. The method for forming a semiconductor structure according to claim 1, wherein: The surface of the fin portion has a first protective layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The first protective layer and the second protective layer are porous materials, and the porosity of the second protective layer material is greater than the porosity of the first protective layer material.

4. The method for forming a semiconductor structure according to claim 2, wherein: The modification treatment also causes the first protective layer to form a first modified layer, and the etching rate of the first modified layer by the cleaning process is within a preset range.

5. The method for forming a semiconductor structure according to claim 2, wherein: The process for forming the first protective layer includes: an atomic layer deposition process.

6. The method for forming a semiconductor structure according to claim 2, wherein: The material of the first protective layer includes silicon oxide.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second protection layer includes silicon oxide.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the dummy gate structure comprises: forming a dummy gate material film covering the top surface and the sidewall surface of the fin on the substrate; etching the dummy gate material film to form a dummy gate structure spanning the fin on the substrate.

9. The method for forming a semiconductor structure according to claim 8, wherein: During the process of etching the dummy gate material film, the second protection layer is formed on the side wall surface of the dummy gate structure.

10. The method for forming a semiconductor structure according to claim 8, wherein: During the etching process of the dummy gate material film, byproducts are generated on the surface of the dummy gate structure or the surface of the fin.

11. The method for forming a semiconductor structure according to claim 1, wherein: The modification treatment includes: chemical treatment.

12. The method for forming a semiconductor structure according to claim 11, wherein: The chemical treatment is nitriding treatment; the parameters of the nitriding treatment include: the gas introduced includes nitrogen, the flow rate of nitrogen is 300 standard ml / min to 1000 standard ml / min, the pressure is 10 mTorr to 100 mTorr, the source power is 300 W to 1000 W, and the time is 5 seconds to 30 seconds.

13. The method for forming a semiconductor structure according to claim 1, wherein: The modification treatment includes: heat treatment.

14. The method for forming a semiconductor structure according to claim 13, wherein: The heat treatment process includes: rapid thermal annealing; the parameters of the rapid thermal annealing include: a temperature range of 700 degrees Celsius to 900 degrees Celsius, and a time range of 5 seconds to 20 seconds.

15. The method for forming a semiconductor structure according to claim 1, wherein: The cleaning process includes: a wet etching process; the parameters of the wet etching process include: the etching solution includes a dilute hydrofluoric acid solution, and the volume ratio of water to hydrofluoric acid ranges from 90:1 to 110:

1.

16. The method for forming a semiconductor structure according to claim 8, wherein: The method of etching the pseudo gate material film to form a pseudo gate structure across the fin on the substrate includes: forming a patterned layer on the surface of the pseudo gate material film, wherein the patterned layer is used to define the position and size of the pseudo gate structure; using the patterned layer as a mask, etching the pseudo gate material film until the substrate surface is exposed, forming the pseudo gate structure on the substrate, and the pseudo gate structure is located on a portion of the top and side wall surfaces of the fin.

17. The method for forming a semiconductor structure according to claim 16, wherein: The process of etching the pseudo gate material film using the patterned layer as a mask includes: a dry etching process; the parameters of the dry etching process include: the etching gas includes chlorine, hydrogen bromide, oxygen and nitrogen, the flow rate of the chlorine is 100 standard ml / min to 300 standard ml / min, the flow rate of hydrogen bromide is 100 standard ml / min to 500 standard ml / min, the flow rate of oxygen is 40 standard ml / min to 100 standard ml / min, the flow rate of nitrogen is 40 standard ml / min to 500 standard ml / min, the pressure is 50 mTorr to 120 mTorr, the high-frequency power is 400 W to 700 W, and the low-frequency voltage is 800 V to 1200 V.

18. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After the cleaning process, a filling layer is formed on the surface of the fin and the surface of the dummy gate structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: The forming process of the filling layer includes: physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process.

20. The method for forming a semiconductor structure according to claim 18, wherein: The thickness of the filling layer ranges from 5 angstroms to 30 angstroms.

21. The method for forming a semiconductor structure according to claim 18, wherein: The material of the filling layer is an insulating material; the insulating material includes: silicon nitride, silicon oxide, silicon oxynitride or silicon oxycarbide.

22. The method for forming a semiconductor structure according to claim 1, wherein: The width of the fin is in a range of 10 nanometers to 15 nanometers.

23. The method for forming a semiconductor structure according to claim 1, wherein: The spacing between adjacent fins ranges from 50 nanometers to 70 nanometers.

24. The method for forming a semiconductor structure according to claim 1, wherein: The width of the dummy gate structure is 15 nanometers to 20 nanometers.

25. The method for forming a semiconductor structure according to claim 1, wherein: The spacing between adjacent dummy gate structures ranges from 50 nanometers to 70 nanometers.

26. A semiconductor structure, characterized in that: The semiconductor structure is obtained by using the method for forming a semiconductor structure according to any one of claims 1 to 25; the semiconductor structure comprises: a substrate having a fin thereon; The substrate is provided with a gate structure crossing the fin, and the sidewall surface of the gate structure is provided with a second modified layer.

27. The semiconductor structure according to claim 26, wherein: The surface of the fin has a first modified layer.

28. The semiconductor structure according to claim 26, wherein: The gate structure includes a gate layer, and the material of the gate layer includes: polysilicon or metal.

29. The semiconductor structure according to claim 26, wherein: Also includes: A filling layer located on the surface of the gate structure and the surface of the fin.

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