Display panel and display device

Abstract

A display panel comprises a virtual driving transistor, a grid electrode of the virtual driving transistor and a virtual common electrode input reference signal, the virtual common electrode is connected with a source electrode of the virtual driving transistor, and a virtual pixel electrode is electrically connected with the source electrode of the virtual driving transistor, which is equivalent to that the virtual pixel electrode accesses the reference signal. Therefore, no parasitic capacitance exists between the virtual pixel electrode and the virtual common electrode, the virtual driving transistor is opened, a reference signal is written into the suspended drain electrode of the virtual driving transistor, the drain electrode and the grid electrode of the virtual driving transistor are both reference signals, and no parasitic capacitance exists between the drain electrode and the grid electrode of the virtual driving transistor. Therefore, the display panel can effectively reduce the load of the peripheral common signal line and improve the recovery speed after the voltage of the reference signal is pulled. The invention further provides a display device comprising the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] The voltage stability of the reference signal loaded on the peripheral common signal line in the liquid crystal display panel is very important. If the voltage of the reference signal cannot be quickly restored after deviation, the display quality will be affected.

[0003] For the virtual sub-pixels at the periphery of the display area, the load of the peripheral common signal line in the virtual pixel driving circuit is relatively large, which reduces the recovery speed of the reference signal voltage after being pulled.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the problem of heavy load on peripheral common signal lines in a virtual pixel driving circuit, and to provide a display panel and a display device.

[0006] According to one aspect of the present disclosure, a display panel is provided, which has a display area and a virtual pixel area, the virtual pixel area is arranged at the periphery of the display area, the display panel includes a virtual pixel driving circuit, the virtual pixel driving circuit is arranged in the virtual pixel area, the virtual pixel driving circuit includes a virtual driving transistor, a virtual pixel electrode and a virtual common electrode, the gate of the virtual driving transistor inputs a reference signal, and the drain of the virtual driving transistor is suspended; the virtual pixel electrode is electrically connected to the source of the virtual driving transistor; the virtual common electrode is connected to the source of the virtual driving transistor, and the virtual common electrode inputs a reference signal.

[0007] In one embodiment of the present invention, a display panel includes a base substrate, a gate layer, an active layer, a source-drain conductive layer, a pixel electrode layer and a common electrode layer, the gate layer includes a virtual gate line, and the virtual gate line includes a virtual gate portion; the active layer includes a virtual active portion, and the orthographic projection of the gate layer on the base substrate overlaps with the orthographic projection of the virtual active portion on the base substrate to form a gate of a virtual driving transistor; the source-drain conductive layer includes a virtual source portion, a virtual drain portion and an internal common signal line, the orthographic projection of the virtual source portion on the base substrate overlaps with the orthographic projection of the virtual active portion on the base substrate to form a source of the virtual driving transistor, the orthographic projection of the virtual drain portion on the base substrate overlaps with the orthographic projection of the virtual active portion on the base substrate to form a drain of the virtual driving transistor, and the internal common signal line is connected to the virtual source portion; the pixel electrode layer includes a virtual pixel electrode, and the virtual pixel electrode is connected to the virtual source portion; the common electrode layer includes a virtual common electrode, and the orthographic projection of the virtual common electrode on the base substrate overlaps with the orthographic projection of the internal common signal line on the base substrate, and the virtual common electrode is connected to the internal common signal line through a first via.

[0008] In one embodiment of the present invention, the common electrode layer further includes a transition portion, and the transition portion is respectively connected to the virtual source portion and the virtual pixel electrode through the second via hole.

[0009] In one embodiment of the present invention, the common electrode layer is arranged on a side of the source and drain conductive layer away from the base substrate, the internal common signal line extends along the column direction, the orthographic projection of the virtual common electrode on the base substrate is a first orthographic projection, and the orthographic projection of the internal common signal line on the base substrate is a second orthographic projection, and the first orthographic projection is away from the edge of the display area and is closer to the display area in the row direction than the second orthographic projection is away from the edge of the display area.

[0010] In one embodiment of the present invention, the common electrode layer also includes a peripheral common signal line, the gate layer also includes a virtual gate signal line, the peripheral common signal line is located at the periphery of the common electrode, the peripheral common signal line includes a first sub-peripheral common signal line and a second sub-peripheral common signal line, the first sub-peripheral common signal line is located in the gate layer, the first sub-peripheral common signal line is connected to the virtual gate wiring, the virtual gate wiring is connected to the virtual gate portion, the second sub-peripheral common signal line is located in the common electrode layer, and the second sub-peripheral common signal line is connected to the virtual common electrode.

[0011] In one embodiment of the present invention, the first sub-peripheral common signal line is connected to the second sub-peripheral common signal line through a third via.

[0012] In one embodiment of the present invention, a first strip opening is provided on the first sub-common signal line, and the first strip opening extends along the column direction. The source-drain conductive layer also includes a data line, and the orthographic projection of the data line on the base substrate overlaps with the orthographic projection of the first strip opening on the base substrate.

[0013] In one embodiment of the present invention, at least two first strip openings are provided on the first sub-common signal line, and the portion between the edges of the two first strip openings located at both ends in the column direction and the edge closest to the first sub-common signal line is the first channel portion, and the portion between the edges of two adjacent first strip openings in the column direction is the second channel portion, and the width of the second channel portion is greater than the width of the first channel portion.

[0014] In one embodiment of the present invention, a second strip opening is provided on the second sub-common signal line, the second strip opening extends along the column direction, and the orthographic projection of the data line on the base substrate overlaps with the orthographic projection of the second strip opening on the base substrate.

[0015] In one embodiment of the present invention, at least two second strip openings are provided on the second sub-common signal line, the portion between the edges of the two second strip openings located at both ends in the column direction and the edge closest to the second sub-common signal line is the third channel portion, and the portion between the edges of two adjacent second strip openings in the column direction is the fourth channel portion, and the width of the fourth channel portion is greater than the width of the third channel portion.

[0016] In one embodiment of the present invention, an orthographic projection of the second strip-shaped opening on the base substrate coincides with an orthographic projection of the first strip-shaped opening on the base substrate.

[0017] In one embodiment of the present invention, the data routing includes a routing portion, the routing portion includes a first data routing segment and a second data routing segment, the width of the second data routing segment is greater than the width of the first data routing segment, the orthographic projection of the first data routing segment on the substrate overlaps with the orthographic projection of the first channel portion and the second channel portion on the substrate, the orthographic projection of the second data routing segment on the substrate overlaps with the orthographic projection of the first strip-shaped opening on the substrate, and a gap exists between an edge of the orthographic projection of the second data routing segment on the substrate and an edge of the orthographic projection of the first strip-shaped opening on the substrate.

[0018] In one embodiment of the present invention, an orthographic projection of the second data routing segment on the substrate overlaps with an orthographic projection of the first channel portion on the substrate.

[0019] In one embodiment of the present invention, the virtual driving transistor includes a first virtual driving transistor and a second virtual driving transistor, the virtual gate line includes a first virtual gate line and a second virtual gate line, the first virtual gate line includes a first virtual gate portion, the second virtual gate line includes a second virtual gate portion, the virtual active portion includes a first virtual active portion and a second virtual active portion, the virtual source portion includes a first virtual source portion and a second virtual source portion, the virtual drain portion includes a first virtual drain portion and a second virtual drain portion, and the orthographic projection of the first virtual gate portion on the substrate overlaps with the orthographic projection of the first virtual active portion on the substrate. A gate of a first virtual driving transistor is formed, a first virtual source portion is connected to the first virtual active portion to form a source of the first virtual driving transistor, a first virtual drain portion is connected to the first virtual active portion to form a drain of the first virtual driving transistor, an orthographic projection of the second virtual gate portion on the substrate overlaps with an orthographic projection of the second virtual active portion on the substrate to form a gate of a second virtual driving transistor, a second virtual source portion is connected to the second virtual active portion to form a source of the second virtual driving transistor, and a second virtual drain portion is connected to the second virtual active portion to form a drain of the second virtual driving transistor.

[0020] In one embodiment of the present invention, the virtual pixel driving circuit includes a first virtual pixel driving circuit and a second virtual pixel driving circuit, the first virtual pixel driving circuit is arranged between two adjacent rows of pixel electrodes, the first virtual pixel driving circuit includes a first virtual driving transistor and a second virtual driving transistor, the second virtual pixel driving circuit is arranged between a peripheral common signal line and a virtual pixel electrode farthest from a display area, and the second virtual pixel driving circuit includes a first virtual driving transistor or a second virtual driving transistor.

[0021] In one embodiment of the present invention, the data routing also includes a first supporting portion, which is connected between adjacent routing portions in the column direction, the width of the first supporting portion in the row direction is greater than the width of the routing portion, and the orthographic projection of the first supporting portion on the substrate does not overlap with the orthographic projection of the virtual gate line on the substrate.

[0022] In one embodiment of the present invention, the data routing also includes a second supporting portion, the second supporting portion is connected between adjacent routing portions in the column direction, a first gap is formed between the orthographic projection of the first virtual gate portion on the substrate substrate and the orthographic projection of the second virtual gate portion on the substrate substrate, the orthographic projection of the first supporting portion on the substrate substrate is arranged in the first gap, a second gap is formed between the orthographic projection of the first virtual gate portion or the second virtual gate portion on the substrate substrate and the orthographic projection of the internal common signal line on the substrate substrate, the orthographic projection of the second supporting portion on the substrate substrate is located in the second gap, and the width of the second supporting portion in the row direction is greater than the width of the first supporting portion.

[0023] According to yet another aspect of the present disclosure, a display device is provided, including the display panel provided by one aspect of the present disclosure.

[0024] The display panel disclosed in the present invention includes a virtual driving transistor, the gate of the virtual driving transistor and the virtual common electrode input reference signals, the virtual common electrode is connected to the source of the virtual driving transistor, and the virtual pixel electrode is electrically connected to the source of the virtual driving transistor, which is equivalent to the virtual pixel electrode being connected to the reference signal, so there is no parasitic capacitance between the virtual pixel electrode and the virtual common electrode, the virtual driving transistor is turned on, and the reference signal is written to the suspended drain of the virtual driving transistor, so the drain and gate of the virtual driving transistor are both reference signals, and there is no parasitic capacitance between the drain and gate of the virtual driving transistor. Therefore, the display panel can effectively reduce the load of the peripheral common signal line and improve the recovery speed of the reference signal after the voltage is pulled.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0027] Figure 1 When a data signal is input to the source of the virtual transistor and a common signal is input to the gate of the virtual driving transistor and the virtual common electrode, a circuit schematic diagram of a virtual pixel driving circuit involved in the related art.

[0028] Figure 2 A planar schematic diagram of a display panel involved in the related art when a data signal is input to a source of a virtual transistor and a common signal is input to a gate of a virtual driving transistor and a virtual common electrode.

[0029] Figure 3 Another planar schematic diagram of a display panel involved in the related art when a data signal is input to a source of a virtual transistor and a common signal is input to a gate of a virtual driving transistor and a virtual common electrode.

[0030] Figure 4 A schematic plan view of a display panel according to an embodiment of the present disclosure when a reference signal is input to a gate electrode and a virtual common electrode of a virtual driving transistor and a reference signal is input to a source electrode of the virtual transistor.

[0031] Figure 5 for Figure 4 A partial schematic diagram of .

[0032] Figure 6 for Figure 4 Another partial schematic diagram of .

[0033] Figure 7 A circuit schematic diagram of a virtual pixel driving circuit according to an embodiment of the present disclosure when a reference signal is input to the gate electrode and the virtual common electrode of the virtual driving transistor and a reference signal is input to the source electrode of the virtual transistor.

[0034] Figure 8 for Figure 4 Another partial schematic diagram of .

[0035] Fig. 9 for Figure 8 A partial enlarged view of area A in the middle.

[0036] Fig.10 It is a schematic plan view of the display panel involved in the embodiment of the present disclosure when the edge of the first orthographic projection is closer to the display area in the row direction than the edge of the second orthographic projection.

[0037] Fig.11 for Fig.10 A partial enlarged view of area B in the middle.

[0038] Fig.12 It is a schematic cross-sectional view of the display panel involved in the embodiment of the present disclosure when the virtual common electrode is broken at the edge of the protective layer.

[0039] Fig.13 It is a cross-sectional schematic diagram of the display panel involved in the embodiment of the present disclosure when the first sub-periphery common signal line is connected with the second sub-periphery common signal line through a via hole.

[0040] Fig.14 It is a plan view schematically showing the orthographic projection of the data wiring involved in the embodiment of the present disclosure on the substrate when the orthographic projection of the first strip-shaped opening on the substrate is within the orthographic projection of the first strip-shaped opening on the substrate.

[0041] Fig.15 It is a plan view schematically showing the orthographic projection of the data wiring involved in the embodiment of the present disclosure on the substrate when the orthographic projection of the second strip-shaped opening on the substrate is within the orthographic projection of the second strip-shaped opening on the substrate.

[0042] Fig.16 This is a schematic diagram showing the distribution of the first strip-shaped openings on the first sub-peripheral common signal line involved in an embodiment of the present disclosure.

[0043] Fig.17 This is a schematic diagram showing the distribution of the second strip-shaped openings on the second sub-peripheral common signal line involved in an embodiment of the present disclosure.

[0044] Fig.18 for Fig.14 A partial schematic diagram of .

[0045] In the figure: 1-base substrate, 2-driving circuit layer, 21-gate layer, 211-gate line, 212-virtual gate portion, 2121-first virtual gate portion, 2122-second virtual gate portion, 213-virtual gate signal line, 214-first sub-peripheral common signal line, 2141-first strip opening, 2142-first channel portion, 2143-second channel portion, 22-active layer, 221-virtual active portion, 2 211-first virtual active portion, 2212-second virtual active portion, 23-source-drain conductive layer, 231-virtual source portion, 2311-first virtual source portion, 2312-second virtual source portion, 232-virtual drain portion, 2321-first virtual drain portion, 2322-second virtual drain portion, 233-data routing, 2331-routing portion, 2332-first data routing segment, 2333-second data routing Segment, 2334-first supporting portion, 2335-second supporting portion, 234-internal common signal line, 3-pixel electrode layer, 31-virtual pixel electrode, 4-common electrode layer, 41-virtual common electrode, 42-transfer portion, 43-second sub-peripheral common signal line, 431-second strip opening, 432-third channel portion, 433-fourth channel portion, 44-connecting line, 5-gate insulating layer, 6-protective layer, 71-first gap, 72-second gap, 8-virtual pixel driving circuit, 81-virtual driving transistor, 811-first virtual driving transistor, 812-second virtual driving transistor, 801-first virtual pixel driving circuit, 802-second virtual pixel driving circuit, 9-display pixel driving circuit, 91-display driving transistor, 10-GOA unit, 11-first via hole, 12-second via hole, 13-third via hole. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0047] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0048] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0049] The voltage stability of the reference signal Vcom loaded on the peripheral common signal line in the liquid crystal display panel is very important. If the voltage of the reference signal Vcom cannot be quickly restored after deviation, it will affect the display quality, such as signal interference, afterimage and other defects. An important factor affecting the rapid recovery of the reference signal Vcom is the load of the peripheral common signal line. Reducing the load of the peripheral common signal line can improve the recovery speed of the reference signal Vcom.

[0050] The display panel has a display area and a virtual pixel area, the virtual pixel area is arranged at the periphery of the display area, the display panel includes a virtual pixel driving circuit 8 and a virtual sub-pixel, the virtual pixel driving circuit 8 is arranged in the virtual pixel area, and the virtual pixel driving circuit 8 drives the virtual sub-pixel. Its main function is to buffer the process, and the virtual sub-pixel is just similar in shape to the display sub-pixel and is not used for picture display, so the setting of the virtual sub-pixel signal is not completely consistent with the display sub-pixel, and the virtual sub-pixel signal is mainly controlled by the virtual pixel driving circuit 8.

[0051] like Figure 1As shown, the virtual pixel driving circuit 8 includes a virtual driving transistor 81, a virtual pixel electrode 31 and a virtual common electrode 41. The gate of the virtual driving transistor 81 and the virtual common electrode 41 input a common signal, the drain of the virtual transistor inputs a data signal Data, the source of the virtual transistor is connected to the virtual pixel electrode 31, and the data signal Data is transmitted from the source of the virtual transistor to the source of the virtual transistor, so the pixel electrode is the data signal Data. Since the data signal Data is different in size from the reference signal Vcom, a first parasitic capacitor is formed between the pixel electrode and the common electrode, and a second parasitic capacitor C2 is formed between the gate and the drain of the virtual driving transistor 81.

[0052] like Figure 2 and Figure 3 As shown, the display panel includes a base substrate 1, a driving circuit layer 2 and a pixel electrode layer 3. The pixel electrode layer 3 and the driving circuit layer 2 are arranged on the same side of the display panel. The driving circuit layer 2 includes a gate layer 21, an active layer 22 and a source-drain conductive layer 23. The gate layer 21 is arranged on one side of the base substrate, the active layer 22 is arranged on the side of the gate layer away from the base substrate 1, and the source-drain conductive layer 23 is arranged on the side of the active layer 22 away from the base substrate 1. The pixel electrode layer 3 can be arranged on the same layer as the virtual gate portion 212. It should be noted that the same-layer arrangement here only means that the gate layer 21 and the pixel electrode layer 3 are both bonded to the same surface of the base substrate 1, that is, the pixel electrode layer 3 and the virtual gate portion 212 are both arranged between the gate insulating layer 5 and the base substrate 1, but the materials of the pixel electrode layer 3 and the gate layer 21 are not the same. Refer to Fig.13 .

[0053] The pixel electrode layer 3 includes a plurality of virtual pixel electrodes 31 arranged in an array, and the gate layer 21 includes a virtual gate line 211, which is disposed between two adjacent rows of virtual pixel electrodes 31. The source-drain conductive layer 23 includes a data wiring 233, and two virtual pixel electrodes 31 are disposed between every two adjacent data wirings 233.

[0054] The virtual gate line 211 also includes a virtual gate portion 212 and a virtual gate signal line 213. The virtual gate signal line 213 is arranged on both sides of the virtual gate portion 212 along the column direction and extends in directions away from each other along the row direction. The active layer 22 includes a virtual active portion 221. The source-drain conductive layer 23 also includes a virtual source portion 231 and a virtual drain portion 232. The orthographic projection of the virtual active portion 221 on the substrate 1 overlaps with the orthographic projection of the virtual gate portion 212 on the substrate 1 to form a gate of the driving transistor. The virtual source portion 231 and the virtual drain portion 232 are connected to the virtual active portion 221 to form a drain of the driving transistor. The end of the virtual source portion 231 that exceeds the virtual active portion 221 is connected to the virtual pixel electrode 31.

[0055] The virtual gate portion 212 is arranged near the data wiring 233. The virtual drain portion 232 is in the shape of a U-shaped structure, the opening of the virtual drain portion 232 of the U-shaped structure is far away from the adjacent data wiring 233, the virtual source portion 231 is in the shape of a straight line, the virtual source portion 231 is surrounded by the virtual drain portion 232, and the virtual drain portion 232 passes through the virtual drain portion 232 in the row direction in a direction away from the data wiring 233. The display panel also includes a common electrode layer 4, which is arranged on a side of the source-drain conductive layer 23 away from the base substrate 1, and the common electrode layer 4 also includes a transition portion 42, which is respectively connected to the virtual source portion 231 and the virtual pixel electrode 31 through the second via 12.

[0056] The virtual source portion 231 is extended along the row direction, the virtual gate signal line 213 is bent along the column direction toward the virtual pixel electrode 31, and a gate compensation portion is provided on the bent portion of the virtual gate signal line 213 to overlap with the virtual source portion 231, so as to compensate for the gate-source capacitance and avoid defective features such as shaking head wrinkles on the display screen when the gate layer 21, the active layer 22 and the source-drain conductive layer 23 are offset.

[0057] The source-drain conductive layer 23 also includes an internal common signal line 234, which is connected to the virtual source portion 231. The internal common signal line 234 extends in the column direction. The common signal line is arranged between two adjacent columns of virtual pixel electrodes 31 and is located on both sides of the data wiring 233. The common electrode layer 4 includes a virtual common electrode 41. The orthographic projection of the virtual common electrode 41 on the base substrate 1 overlaps with the orthographic projection of the internal common signal line 234 on the base substrate 1. The virtual common electrode 41 is connected to the internal common signal line 234 through a first via 11. A connecting line 44 is provided between two adjacent rows of virtual common electrodes 41, and the connecting line 44 may also be connected to the internal common signal line 234 through the first via 11. The common electrode layer 4 also includes a transition portion 42, which is respectively connected to the virtual source portion 231 and the virtual pixel electrode 31 through a second via 12.

[0058] The display panel also includes a peripheral common signal line, which is located at the periphery of the common electrode. The peripheral common signal line includes a first sub-peripheral common signal line 214 and a second sub-peripheral common signal line 43. The first sub-peripheral common signal line 214 is located at the gate layer 21, and the first sub-peripheral common signal line 214 is connected to the virtual gate signal line 213, and the virtual gate signal line 213 is connected to the virtual gate portion 212. The second sub-peripheral common signal line 43 is located at the common electrode layer 4, and the second sub-peripheral common signal line 43 is connected to the virtual common electrode 41.

[0059] The display panel includes a display pixel driving circuit 9 and a display sub-pixel. The display pixel driving circuit 9 is arranged in the display area, and the display pixel driving circuit 9 drives the display sub-pixel. The display pixel driving circuit 9 has a substantially same structure as the virtual pixel driving circuit 8, except that the display pixel driving circuit 9 includes a display driving transistor 91, and the gate of the display driving transistor 91 is connected to the GOA unit 10-GOA, and the gate control signal is input by the GOA unit 10-GOA, which will not be described in detail here.

[0060] A reference signal Vcom can be loaded on the peripheral common signal line, and the reference signal Vcom is transmitted to the virtual gate portion 212 through the first sub-peripheral common signal line 214, and the reference signal Vcom is transmitted to the virtual common electrode 41 through the second sub-peripheral common signal line 43. The data signal Data can be loaded on the data line 233, and the data signal Data is transmitted to the virtual pixel electrode 31 through the data line 233, and the first parasitic capacitance formed between the pixel electrode and the common electrode is introduced into the peripheral common signal line. The second parasitic capacitance C2 formed between the virtual gate portion 212 and the virtual drain portion 232 is also introduced into the peripheral common signal line. The introduction of the above two parasitic capacitances additionally increases the load of the peripheral common signal line, which is not conducive to the recovery of the reference signal Vcom after being pulled.

[0061] Based on this, an embodiment of the present invention provides a display panel. Figure 1 ,as well as Figures 4 to 16 As shown, the display panel has a display area and a virtual pixel area, the virtual pixel area is arranged at the periphery of the display area, the display panel includes a virtual pixel driving circuit 8, the virtual pixel driving circuit 8 is arranged in the virtual pixel area, the virtual pixel driving circuit 8 also includes a virtual driving transistor 81, a virtual pixel electrode 31 and a virtual common electrode 41, the gate of the virtual driving transistor 81 inputs a reference signal Vcom, the drain of the virtual driving transistor 81 is suspended, the virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81; the virtual common electrode 41 is connected to the source of the virtual driving transistor 81, and the virtual common electrode 41 inputs a reference signal Vcom.

[0062] The gate of the virtual driving transistor 81 and the virtual common electrode 41 input the reference signal Vcom, the virtual common electrode 41 is connected to the source of the virtual driving transistor 81, and the virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81, which is equivalent to the virtual pixel electrode 31 being connected to the reference signal Vcom, so there is no parasitic capacitance between the virtual pixel electrode 31 and the virtual common electrode 41, the virtual driving transistor 81 is turned on, and the suspended drain of the virtual driving transistor 81 is written with the reference signal Vcom, so the drain and gate of the virtual driving transistor 81 are both the reference signal Vcom, and there is no parasitic capacitance between the drain and gate of the virtual driving transistor 81. Therefore, the display panel can effectively reduce the load of the peripheral common signal line and improve the recovery speed of the reference signal Vcom after the voltage is pulled.

[0063] The display panel involved in the present invention is described in detail below with reference to specific embodiments.

[0064] like Figure 4 As shown, the virtual driving transistor 81 includes a first virtual driving transistor 811 and a second virtual driving transistor 812, the virtual gate line 211 includes a first virtual gate line 211 and a second virtual gate line 211, the first virtual gate line 211 includes a first virtual gate portion 2121, the second virtual gate line 211 includes a second virtual gate portion 2122, the virtual active portion 221 includes a first virtual active portion 2211 and a second virtual active portion 2212, the virtual source portion 231 includes a first virtual source portion 2311 and a second virtual source portion 2312, the virtual drain portion 232 includes a first virtual drain portion 2321 and a second virtual drain portion 2322, and the orthographic projection of the first virtual gate portion 2121 on the substrate substrate 1 is the same as the orthographic projection of the first virtual active portion 2211 on the substrate substrate 1 The first virtual source portion 2311 is connected to the first virtual active portion 2211 to form the source of the first virtual driving transistor 811, the first virtual drain portion 2321 is connected to the first virtual active portion 2211 to form the drain of the first virtual driving transistor 811, the positive projection of the second virtual gate portion 2122 on the substrate substrate 1 overlaps with the positive projection of the second virtual active portion 2212 on the substrate substrate 1 to form the gate of the second virtual driving transistor 812, the second virtual source portion 2312 is connected to the second virtual active portion 2212 to form the source of the second virtual driving transistor 812, and the second virtual drain portion 2322 is connected to the second virtual active portion 2212 to form the drain of the second virtual driving transistor 812.

[0065] The virtual pixel driving circuit 8 includes a first virtual pixel driving circuit 801 and a second virtual pixel driving circuit 802. The first virtual pixel driving circuit 801 is arranged between two adjacent rows of virtual pixel electrodes 31. The first virtual pixel driving circuit 801 includes a first virtual driving transistor 811 and a second virtual driving transistor 812. The second virtual pixel driving circuit 802 is arranged between the peripheral reference signal Vcom line and the virtual pixel electrode 31 farthest from the display area. The second virtual pixel driving circuit 802 includes a first virtual driving transistor 811 or a second virtual driving transistor 812.

[0066] For the first virtual pixel driving circuit 801, the first virtual gate portion 2121 and the second virtual gate portion 2122 are arranged on both sides of the data wiring 233 and are staggered in the column direction. The virtual gate signal line 213 of the first virtual gate line 211 and the virtual gate signal line 213 of the second virtual gate line 211 are parallel to each other. The first virtual drain portion 2321 and the second virtual drain portion 2322 are connected to the same data wiring 233 and have different orientations in the row direction. The first virtual source portion 2311 and the second virtual source portion 2312 extend in directions away from each other.

[0067] like Figure 5 and Figure 6 As shown, the virtual drain portion 232 is disconnected from the data wiring 233, so that the communication path between the data signal Data and the virtual pixel electrode 31 can be cut off, and the internal common signal line 234 is connected to the virtual source portion 231, so that the reference signal Vcom is transmitted to the virtual pixel electrode 31 through the virtual source portion 231, thereby forming a virtual pixel driving circuit 8 as shown in the figure. Figure 7 As shown, the gate of the virtual driving transistor 81 inputs the reference signal Vcom, the drain of the virtual driving transistor 81 is suspended, the virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81, the virtual common electrode 41 is connected to the source of the virtual driving transistor 81, and the virtual common electrode 41 inputs the reference signal Vcom.

[0068] See also Figure 1 The display panel also includes a peripheral common signal line, which is located at the periphery of the common electrode. The peripheral common signal line includes a first sub-peripheral common signal line 214 and a second sub-peripheral common signal line 43. The first sub-peripheral common signal line 214 is located at the gate layer 21. The gate layer 21 also includes a virtual gate signal line 213. The first sub-peripheral common signal line 214 is connected to the virtual gate signal line 213. The virtual gate signal line 213 is connected to the virtual gate portion 212. The second sub-peripheral common signal line 43 is located at the common electrode layer 4, and the second sub-peripheral common signal line 43 is connected to the virtual common electrode 41.

[0069] A reference signal Vcom can be loaded on the peripheral common signal line. The reference signal Vcom is transmitted to the virtual gate portion 212 through the first sub-peripheral common signal line 214. The reference signal Vcom is transmitted to the virtual common electrode 41 through the second sub-peripheral common signal line 43. The virtual common electrode 41 is then transmitted to the internal common signal line 234. The internal common signal line 234 is then transmitted to the source of the virtual driving transistor 81. The virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81, which is equivalent to the virtual pixel electrode 31 being connected to the reference signal Vcom. Therefore, there is no parasitic capacitance between the virtual pixel electrode 31 and the virtual common electrode 41.

[0070] When the virtual driving transistor 81 is an n-type transistor, the drain of the virtual driving transistor 81 is suspended, that is, the voltage loaded on the drain of the virtual driving transistor 81 is equal to 0V, and the gate of the virtual driving transistor 81 is connected to the reference signal Vcom, which is usually greater than or equal to 0V. At this time, Vgs is greater than or equal to 0V, so Vth needs to be less than 0V to satisfy Vgs>Vth, and the virtual driving transistor 81 is equivalent to being turned on. The suspended drain of the virtual driving transistor 81 is written with the reference signal Vcom, so the drain and gate of the virtual driving transistor 81 are both the reference signal Vcom, and there is no parasitic capacitance between the drain and gate of the virtual driving transistor 81.

[0071] In other embodiments, the virtual driving transistor 81 may also be a p-type transistor. When the virtual driving transistor 81 is a p-type transistor, the drain of the virtual driving transistor 81 is connected to the reference signal Vcom, and the gate of the virtual driving transistor 81 is connected to the reference signal Vcom. At this time, Vgs is equal to or greater than 0V, which satisfies Vgs<Vth, and the virtual driving transistor 81 can also be turned on.

[0072] See again Figure 4 The data wiring 233 also includes a first supporting portion 2334 and a second supporting portion 2335. The first supporting portion 2334 and the second supporting portion 2335 are connected between adjacent wiring portions 2331 in the column direction. The width of the first supporting portion 2334 in the row direction is greater than the width of the wiring portion 2331. A first gap 71 is formed between the orthographic projection of the first virtual gate portion 2121 on the substrate 1 and the orthographic projection of the second virtual gate portion 2122 on the substrate 1. The orthographic projection of the first supporting portion 2334 on the substrate 1 is arranged in the first gap 71.

[0073] A second gap 72 is formed between the orthographic projection of the first virtual gate portion 2121 or the second virtual gate portion 2122 on the substrate 1 and the orthographic projection of the internal common signal line 234 on the substrate 1, and the orthographic projection of the second support portion 2335 on the substrate 1 is located in the second gap 72. Since a virtual gate line 211 of the second virtual pixel driving circuit 802 is removed, the width of the second gap 72 is greater than the width of the first gap 71. Therefore, the width of the second support portion 2335 in the row direction is greater than the width of the first support portion 2334. The second gap 72 of the second support portion 2335 is filled to replace the supporting function of the other virtual gate line 211 removed at the outermost edge as much as possible, thereby preventing the first virtual pixel driving circuit 801 and the display pixel driving circuit 9 from having a support difference, and avoiding the virtual pixel area from having a step difference in this area and the display area, resulting in light leakage and redness.

[0074] The orthographic projections of the first supporting portion 2334 and the second supporting portion 2335 on the base substrate 1 do not overlap with the orthographic projections of the virtual gate line 211 on the base substrate 1. Figure 8 and Fig. 9 As shown, the distance between the orthographic projection of the first support portion 2334 on the substrate substrate 1 and the orthographic projection of the first virtual gate portion 2121 on the substrate substrate 1 is a, a≥(a1^2+a2^2+b1^2+b2^2)^0.5, wherein a1 is the position deviation value of the gate layer 21, a2 is the width fluctuation value of the gate line 211, b1 is the position deviation value of the source-drain conductive layer 23, and b2 is the width fluctuation value of the data line 233.

[0075] like Figures 10 to 12 As shown, a gate insulating layer 5 is provided between the gate layer 21 and the source-drain conductive layer 23, and a protective layer 6 is provided between the source-drain conductive layer 23 and the common electrode layer 4, and the protective layer 6 covers the data wiring 233 and the gate insulating layer 5. The internal common signal line 234 extends along the column direction, the orthographic projection of the virtual common electrode 41 on the base substrate 1 is the first orthographic projection, and the orthographic projection of the internal common signal line 234 on the base substrate 1 is the second orthographic projection. In order to avoid the virtual common electrode 41 from breaking at the edge of the protective layer 6, the edge of the first orthographic projection is set to be closer to the display area in the row direction than the edge of the second orthographic projection. It can be understood that the edge of the virtual common electrode 41 does not exceed the edge of the internal common signal line 234, which can avoid the virtual common electrode 41 from breaking at the edge of the protective layer 6, thereby avoiding partial suspension of the virtual common electrode 41. Fig.12 As shown, when the edge of the first orthographic projection is farther from the display area in the row direction than the edge of the second orthographic projection, the virtual common electrode 41 is broken at the edge of the protective layer 6 .

[0076] like Fig.13As shown, the first sub-peripheral common signal line 214 is connected to the second sub-peripheral common signal line 43 through the third via 13. By connecting the first sub-peripheral common signal line 214 and the second sub-peripheral common signal line 43 in parallel, the resistance of the peripheral common signal line can be reduced.

[0077] like Figures 14 to 17 As shown, a first strip opening 2141 is provided on the first sub-common signal line, a second strip opening 431 is provided on the second sub-common signal line, the first strip opening 2141 and the second strip opening 431 extend along the column direction, and the orthographic projection of the data line 233 on the base substrate 1 overlaps with the orthographic projection of the first strip opening 2141 and the second strip opening 431 on the base substrate 1, which can reduce the parasitic capacitance between the peripheral common signal line and the data line 233. In this embodiment, the orthographic projection of the data line 233 on the base substrate 1 is within the orthographic projection of the first strip opening 2141 and the second strip opening 431 on the base substrate 1.

[0078] The orthographic projection of the second strip opening 431 on the base substrate 1 coincides with the orthographic projection of the first strip opening 2141 on the base substrate 1, that is, the first strip opening 2141 and the second strip opening 431 are the same in shape, size and position, and the first strip opening 2141 and the second strip opening 431 can be formed by the same mask. In other embodiments, the orthographic projection of the second strip opening 431 on the base substrate 1 may not coincide with the orthographic projection of the first strip opening 2141 on the base substrate 1, as long as the orthographic projection of the data wiring 233 on the base substrate 1 is within the orthographic projection of the first strip opening 2141 and the second strip opening 431 on the base substrate 1, so that the parasitic capacitance between the peripheral common signal line and the data wiring 233 can also be reduced.

[0079] Two first strip openings 2141 are provided on the first sub-common signal line, and the portion between the edges of the two first strip openings 2141 at both ends in the column direction and the edge closest to the first sub-common signal line is a first channel portion 2142, and the portion between the edges of two adjacent first strip openings 2141 in the column direction is a second channel portion 2143, and the width of the second channel portion 2143 is greater than the width of the first channel portion 2142. Two second strip openings 431 are provided on the second sub-common signal line, and the portion between the edges of the two second strip openings 431 at both ends in the column direction and the edge closest to the second sub-common signal line is a third channel portion 432, and the portion between the edges of two adjacent second strip openings 431 in the column direction is a fourth channel portion 433, and the width of the fourth channel portion 433 is greater than the width of the third channel portion 432.

[0080] The width w1 of the first channel portion 2142 and the third channel portion 432 is small, and the width w2 of the second channel portion 2143 and the fourth channel portion 433 is large. The first channel portion 2142 and the third channel portion 432 have a larger resistance than the second channel portion 2143 and the fourth channel portion 433. If there is a large static electricity passing through the peripheral common signal line, it is preferentially released in the first channel portion 2142 and the third channel portion 432, and the second channel portion 2143 and the fourth channel portion 433 can still be turned on. In this embodiment, w1≥minimum process line width, w2=5w1. In other embodiments, the width w2 of the second channel portion 2143 and the fourth channel portion 433 can also be adjusted to w2>5w1 or w2<5w1.

[0081] like Fig.18 As shown, the data routing line 233 includes a routing line portion 2331, and the routing line portion 2331 includes a first data routing line segment 2332 and a second data routing line segment 2333. The width of the second data routing line segment 2333 is greater than the width of the first data routing line segment 2332. The orthographic projection of the first data routing line segment 2332 on the substrate substrate 1 overlaps with the orthographic projection of the first channel portion 2142 and the second channel portion 2143 on the substrate substrate 1. The orthographic projection of the second data routing line segment 2333 on the substrate substrate 1 overlaps with the orthographic projection of the first strip-shaped opening 2141 on the substrate substrate 1. The width of the first data routing line segment 2332 is set to be smaller in order to reduce the overlapping area of ​​the data routing line 233 and the peripheral common signal line, so as to further reduce the parasitic capacitance between the data routing line 233 and the peripheral common signal line. The minimum width of the first data routing line segment 2332 is greater than or equal to the minimum process line width.

[0082] There is a gap between the edge of the orthographic projection of the second data wiring segment 2333 on the base substrate 1 and the edge of the orthographic projection of the first strip-shaped opening 2141 on the base substrate 1. The distance along the row direction between the orthographic projection of the first strip-shaped opening 2141 on the base substrate 1 and the data wiring 233 is d1, d1≥(a1^2+a2^2+b1^2+b2^2)^0.5, wherein a1 is the position deviation value of the gate layer 21, a2 is the width fluctuation value of the gate line 211, b1 is the position deviation value of the source-drain conductive layer 23, and b2 is the width fluctuation value of the data wiring 233.

[0083] The orthographic projection of the second data routing segment 2333 on the substrate 1 partially overlaps with the orthographic projection of the first channel portion 2142 on the substrate 1. The overlapping width of the orthographic projection of the second data routing segment 2333 on the substrate 1 and the orthographic projection of the first channel portion 2142 on the substrate 1 may be d2, d2 ≥ (a1^2+a2^2+b1^2+b2^2)^0.5, and the thinning process is performed at a distance d2 from the edge of the first strip opening 2141 along the first direction, in order to prevent the data routing 233 from being broken at the overlapping position with the first strip opening 2141.

[0084] The display panel does not have parasitic capacitance between the virtual pixel electrode 31 and the virtual common electrode 41, and does not have parasitic capacitance between the drain and the gate of the virtual driving transistor 81, and can reduce the parasitic capacitance between the data wiring 233 and the peripheral common signal line. Therefore, it can effectively reduce the load of the peripheral common signal line and improve the recovery speed of the reference signal Vcom after the voltage is pulled.

[0085] The present disclosure also provides a display device, which may include the display panel mentioned in the present disclosure. The specific structure and beneficial effects of the display device can refer to the display panel, which has been described in detail above, so it will not be repeated here.

[0086] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art may make corresponding supplements according to the specific use requirements of the display device, which will not be repeated here.

[0087] The display device can be a traditional electronic device, such as a mobile phone, a computer, a television, and a camcorder, or it can be an emerging wearable device, such as a virtual reality device and an augmented reality device, which are not listed here one by one.

[0088] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel comprising a display area and a virtual pixel area, wherein the virtual pixel area is arranged outside the display area, wherein: The display panel includes a dummy pixel driving circuit, which is provided in the dummy pixel area, and the dummy pixel driving circuit includes: a dummy driving transistor, wherein a gate of the dummy driving transistor inputs a reference signal, and a drain of the dummy driving transistor is suspended; a virtual pixel electrode electrically connected to the source electrode of the virtual driving transistor; A virtual common electrode is connected to the source of the virtual driving transistor, and the virtual common electrode inputs the reference signal.

2. The display panel according to claim 1, wherein: The display panel includes: substrate; a gate layer, the gate layer including a dummy gate line, the dummy gate line including a dummy gate portion; an active layer, the active layer including a dummy active portion, an orthographic projection of the gate layer on the base substrate overlapping with an orthographic projection of the dummy active portion on the base substrate, forming a gate of the dummy driving transistor; a source-drain conductive layer, the source-drain conductive layer comprising a dummy source portion, a dummy drain portion, and an internal common signal line, the orthographic projection of the dummy source portion on the base substrate overlapping with the orthographic projection of the dummy active portion on the base substrate forming the source of the dummy drive transistor, the orthographic projection of the dummy drain portion on the base substrate overlapping with the orthographic projection of the dummy active portion on the base substrate forming the drain of the dummy drive transistor, and the internal common signal line connected to the dummy source portion; a pixel electrode layer, comprising the dummy pixel electrode, wherein the dummy pixel electrode is connected to the dummy source portion; A common electrode layer includes the virtual common electrode, the orthographic projection of the virtual common electrode on the base substrate overlaps with the orthographic projection of the internal common signal line on the base substrate, and the virtual common electrode is connected to the internal common signal line through a first via.

3. The display panel according to claim 2, wherein: The common electrode layer further includes a transition portion, and the transition portion is connected to the virtual source portion and the virtual pixel electrode respectively through a second via hole.

4. The display panel according to claim 2, wherein: The common electrode layer is arranged on a side of the source-drain conductive layer away from the base substrate, the internal common signal line extends along the column direction, the orthographic projection of the virtual common electrode on the base substrate is a first orthographic projection, and the orthographic projection of the internal common signal line on the base substrate is a second orthographic projection. The first orthographic projection is away from the edge of the display area and is closer to the display area in the row direction than the second orthographic projection is away from the edge of the display area.

5. The display panel according to claim 4, wherein: The common electrode layer also includes a peripheral common signal line, which is located at the periphery of the common electrode. The peripheral common signal line includes a first sub-peripheral common signal line and a second sub-peripheral common signal line. The first sub-peripheral common signal line is located at the gate layer. The virtual gate line also includes a virtual gate signal line. The first sub-peripheral common signal line is connected to the virtual gate signal line. The virtual gate signal line is connected to the virtual gate portion. The second sub-peripheral common signal line is located at the common electrode layer. The second sub-peripheral common signal line is connected to the virtual common electrode.

6. The display panel according to claim 5, wherein: The first sub-peripheral common signal line is connected to the second sub-peripheral common signal line through a third via.

7. The display panel according to claim 6, wherein: A first strip-shaped opening is provided on the first sub-common signal line, and the first strip-shaped opening extends along the column direction. The source-drain conductive layer also includes a data line, and the orthographic projection of the data line on the base substrate overlaps with the orthographic projection of the first strip-shaped opening on the base substrate.

8. The display panel according to claim 7, wherein: At least two first strip-shaped openings are provided on the first sub-common signal line, and the portion between the edges of the two first strip-shaped openings at both ends in the column direction and the nearest edge of the first sub-common signal line is a first channel portion, and the portion between the edges of two adjacent first strip-shaped openings in the column direction is a second channel portion, and the width of the second channel portion is greater than that of the first channel portion.

9. The display panel according to claim 8, wherein: A second strip-shaped opening is provided on the second sub-common signal line, and the second strip-shaped opening extends along a column direction. The orthographic projection of the data line on the base substrate overlaps with the orthographic projection of the second strip-shaped opening on the base substrate.

10. The display panel according to claim 9, wherein: At least two second strip-shaped openings are provided on the second sub-common signal line, and the portion between the edges of the two second strip-shaped openings at both ends in the column direction and the nearest edge of the second sub-common signal line is the third channel portion, and the portion between the edges of two adjacent second strip-shaped openings in the column direction is the fourth channel portion, and the width of the fourth channel portion is greater than that of the third channel portion.

11. The display panel according to claim 10, wherein: The orthographic projection of the second strip-shaped opening on the base substrate coincides with the orthographic projection of the first strip-shaped opening on the base substrate.

12. The display panel according to claim 8, wherein The data routing includes a routing portion, which includes a first data routing segment and a second data routing segment. The width of the second data routing segment is greater than the width of the first data routing segment. The orthographic projection of the first data routing segment on the base substrate overlaps with the orthographic projections of the first channel portion and the second channel portion on the base substrate. The orthographic projection of the second data routing segment on the base substrate overlaps with the orthographic projection of the first strip-shaped opening on the base substrate. A gap is provided between an edge of the orthographic projection of the second data routing segment on the base substrate and an edge of the orthographic projection of the first strip-shaped opening on the base substrate.

13. The display panel according to claim 12, wherein: An orthographic projection of the second data routing segment on the base substrate partially overlaps with an orthographic projection of the first channel portion on the base substrate.

14. The display panel according to claim 12, wherein: The dummy driving transistor includes a first dummy driving transistor and a second dummy driving transistor, the dummy gate line includes a first dummy gate line and a second dummy gate line, the first dummy gate line includes a first dummy gate portion, the second dummy gate line includes a second dummy gate portion, the dummy active portion includes a first dummy active portion and a second dummy active portion, the dummy source portion includes a first dummy source portion and a second dummy source portion, the dummy drain portion includes a first dummy drain portion and a second dummy drain portion, the orthographic projection of the first dummy gate portion on the base substrate overlaps with the orthographic projection of the first dummy active portion on the base substrate, forming the first dummy driving transistor. The first virtual source portion is connected to the first virtual active portion to form the source of the first virtual driving transistor, the first virtual drain portion is connected to the first virtual active portion to form the drain of the first virtual driving transistor, the orthographic projection of the second virtual gate portion on the base substrate overlaps with the orthographic projection of the second virtual active portion on the base substrate to form the gate of the second virtual driving transistor, the second virtual source portion is connected to the second virtual active portion to form the source of the second virtual driving transistor, and the second virtual drain portion is connected to the second virtual active portion to form the drain of the second virtual driving transistor.

15. The display panel according to claim 14, wherein: The virtual pixel driving circuit includes a first virtual pixel driving circuit and a second virtual pixel driving circuit, the first virtual pixel driving circuit is arranged between two adjacent rows of pixel electrodes, the first virtual pixel driving circuit includes a first virtual driving transistor and a second virtual driving transistor, the second virtual pixel driving circuit is arranged between the peripheral common signal line and the virtual pixel electrode farthest from the display area, and the second virtual pixel driving circuit includes a first virtual driving transistor or a second virtual driving transistor.

16. The display panel according to claim 15, wherein: The data routing line also includes a first supporting portion, which is connected between adjacent routing portions in the column direction. The width of the first supporting portion in the row direction is greater than the width of the routing portion. The orthographic projection of the first supporting portion on the base substrate does not overlap with the orthographic projection of the virtual gate line on the base substrate.

17. The display panel according to claim 16, wherein: The data routing also includes a second supporting portion, which is connected between adjacent routing portions in the column direction. A first gap is formed between the orthographic projection of the first virtual gate portion on the base substrate and the orthographic projection of the second virtual gate portion on the base substrate. The orthographic projection of the first supporting portion on the base substrate is arranged within the first gap. A second gap is formed between the orthographic projection of the first virtual gate portion or the second virtual gate portion on the base substrate and the orthographic projection of the internal common signal line on the base substrate. The orthographic projection of the second supporting portion on the base substrate is located within the second gap. In the row direction, the width of the second supporting portion is greater than the width of the first supporting portion.

18. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 17.

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