Delta-Sigma modulator

Abstract

The invention discloses a Delta-Sigma modulator. The Delta-Sigma modulator comprises a first integration module, a second integration module, a third integration module, an accumulation module and a comparator module, the first integral module, the second integral module and the third integral module are connected with the comparator module through the accumulation module; the circuit structures of the first in-phase input structure and the first inverted input structure are the same; the first in-phase input structure comprises a first resistor, a first capacitor, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch. The method can improve the linearity. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a Delta-Sigma modulator. Background Art

[0002] Analog-to-digital converter (ADC) is an important analog circuit. Its function is to convert external analog signals into binary digital codes according to certain rules. Different types of ADCs have different precision and speed, so their application fields are also different. For designers, how to achieve high-performance ADC has always been a difficult problem.

[0003] Today's single-type ADCs include pipeline, successive approximation (SAR), flash, Delta-Sigma, etc. Among various ADC architectures, discrete time (DT) Delta-Sigma ADC is the most suitable type for achieving high precision in the low-frequency applications mentioned above.

[0004] Delta-Sigma ADC consists of two parts: Delta-Sigma modulator and digital decimation filter. It uses oversampling and noise shaping technology to modulate the low-speed analog input signal into a high-speed digital bit stream, and then completes the frequency reduction filtering operation through the digital filter to obtain a high-precision digital output signal. How to make the analog circuit part of the ADC, the Delta-Sigma modulator, work in a lower voltage environment while maintaining good performance has become one of the key research issues in academia and industry.

[0005] In the related art, in order to make the ADC present good performance, the Delta-Sigma modulator in the designed ADC adopts complementary switches to improve the switch linearity. However, the improvement is limited and cannot meet the high-precision requirements of the ADC. The Delta-Sigma modulator can also adopt clock boost technology and bootstrap switches, which can effectively enhance the switch linearity by generating a higher voltage level, but requires additional hardware overhead. Therefore, a new Delta-Sigma modulator is urgently needed. Summary of the invention

[0006] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0007] To this end, an object of an embodiment of the present application is to provide a Delta-Sigma modulator, which can improve linearity.

[0008] In order to achieve the above technical objectives, the technical solution adopted by the embodiment of the present application includes: a Delta-Sigma modulator, including a first integration module, a second integration module, a third integration module, an accumulation module and a comparator module; the first integration module, the second integration module and the third integration module are connected to the comparator module through the accumulation module; wherein the first integration module includes a first in-phase input structure, a first inverting input structure, a first switch, an input chopper, a first transconductance amplifier, an output chopper, a first feedback capacitor and a second feedback capacitor; the first in-phase input structure is connected to the first inverting input structure through the first switch; one end of the first feedback capacitor and the first in-phase input structure are connected to the in-phase input end of the first transconductance amplifier through the input chopper; one end of the second feedback capacitor and the first inverting input structure are connected to the inverting input end of the first transconductance amplifier through the input chopper; the first feedback capacitor The other end of the capacitor is connected to the inverting output end of the first transconductance amplifier through the output chopper; the other end of the second feedback capacitor is connected to the non-inverting output end of the first transconductance amplifier through the output chopper; the first non-inverting input structure has the same circuit structure as the first inverting input structure; the first non-inverting input structure includes a first resistor, a first capacitor, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch; one end of the first resistor is connected to the differential input signal, and the other end of the first resistor is connected to the input chopper through the second switch; one end of the first capacitor is connected to the common mode level through the third switch, the other end of the first capacitor is connected to the common mode level through the fourth switch, the other end of the first capacitor is connected to the first reference voltage through the sixth switch, the other end of the first capacitor is connected to the second reference voltage through the seventh switch, and one end of the first capacitor is connected to the input chopper through the third switch.

[0009] In addition, the method for outputting arbitrary orthogonal pulse frequency division according to the above embodiment of the present invention may also have the following additional technical features:

[0010] Further, in an embodiment of the present application, the accumulation module includes a first accumulation sub-circuit to an eighth accumulation sub-circuit; the first accumulation sub-circuit, the third accumulation sub-circuit, the fifth accumulation sub-circuit and the seventh accumulation sub-circuit are connected in parallel to the comparator module; the second accumulation sub-circuit, the fourth accumulation sub-circuit, the sixth accumulation sub-circuit and the eighth accumulation sub-circuit are connected in parallel to the comparator module; the first accumulation sub-circuit and the second accumulation sub-circuit are connected to the differential input signal, the third accumulation sub-circuit and the fourth accumulation sub-circuit are connected to two output ends of the first integration module; the fifth accumulation sub-circuit and the sixth accumulation sub-circuit are connected to two output ends of the second integration module; the seventh accumulation sub-circuit and the eighth accumulation sub-circuit are connected to two output ends of the second integration module.

[0011] Furthermore, in an embodiment of the present application, the first accumulation sub-circuit, the second accumulation sub-circuit, the third accumulation sub-circuit, the fourth accumulation sub-circuit, the fifth accumulation sub-circuit, the sixth accumulation sub-circuit, the seventh accumulation sub-circuit and the eighth accumulation sub-circuit have the same structure; each accumulation sub-circuit includes a second capacitor, an eighth switch and a ninth switch; one end of the eighth switch serves as an input end of each accumulation sub-circuit, the other end of the eighth switch is connected to one end of the second capacitor, and one end of the second capacitor is connected to the common mode level through the ninth switch; the other end of the second capacitor serves as an output end of each accumulation sub-circuit.

[0012] Furthermore, in an embodiment of the present application, the modulator includes a first regulating switch and a second regulating switch; the first accumulator sub-circuit, the third accumulator sub-circuit, the fifth accumulator sub-circuit and the seventh accumulator sub-circuit are connected in parallel and connected to the common mode level through the first regulating switch; the second accumulator sub-circuit, the fourth accumulator sub-circuit, the sixth accumulator sub-circuit and the eighth accumulator sub-circuit are connected in parallel and connected to the common mode level through the second regulating switch.

[0013] Furthermore, in the embodiment of the present application, the second switch, the fourth switch, the first regulating switch and the second regulating switch are switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%.

[0014] Further, in an embodiment of the present application, the second integration module includes a second transconductance amplifier, a second non-inverting input structure, a second inverting input structure, a third feedback capacitor and a fourth feedback capacitor; the second non-inverting input structure is connected to the non-inverting input terminal of the second transconductance amplifier; the second inverting input structure is connected to the inverting input terminal of the second transconductance amplifier; one end of the third feedback capacitor is connected to the non-inverting input terminal of the second transconductance amplifier; the other end of the third feedback capacitor is connected to the inverting output terminal of the second transconductance amplifier; one end of the fourth feedback capacitor is connected to the inverting input terminal of the second transconductance amplifier; the other end of the fourth feedback capacitor is connected to the non-inverting output terminal of the second transconductance amplifier.

[0015] Further, in the embodiment of the present application, the third integration module includes a third transconductance amplifier, a third in-phase input structure, a third inverting input structure, a fifth feedback capacitor and a sixth feedback capacitor;

[0016] The third non-inverting input structure is connected to the non-inverting input terminal of the third transconductance amplifier; the third inverting input structure is connected to the inverting input terminal of the third transconductance amplifier; one end of the fifth feedback capacitor is connected to the non-inverting input terminal of the third transconductance amplifier; the other end of the fifth feedback capacitor is connected to the inverting output terminal of the third transconductance amplifier; one end of the sixth feedback capacitor is connected to the inverting input terminal of the third transconductance amplifier; the other end of the sixth feedback capacitor is connected to the non-inverting output terminal of the third transconductance amplifier.

[0017] Further, in the embodiment of the present application, the third in-phase input structure, the third inverting input structure, the second in-phase input structure and the second inverting input structure are the same, and any one of the input structures includes a third capacitor, a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch;

[0018] One end of the tenth switch serves as the input end of the input structure, the other end of the tenth switch is connected to one end of the third capacitor, and the common mode level is connected to one end of the third capacitor through the eleventh switch; the other end of the third capacitor is connected to one end of the thirteenth switch, and the common mode level is connected to the other end of the third capacitor through the twelfth switch; the other end of the thirteenth switch serves as the input end of the input structure.

[0019] Furthermore, in an embodiment of the present application, the comparator module includes a comparator and a fourteenth switch; the output end of the comparator is the output end of the Delta-Sigma modulator; the first integration module, the second integration module and the third integration module are connected to the fourteenth switch through the accumulation module; the fourteenth switch is connected to the comparator.

[0020] Furthermore, in an embodiment of the present application, the first switch, the thirteenth switch, and the fourteenth switch are switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 90%; the twelfth switch is a switch modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%.

[0021] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0022] The present application is a Delta-Sigma modulator composed of a first integration module, a second integration module, a third integration module, an accumulation module and a comparator module. The Delta-Sigma modulator has a first integration module composed of a first in-phase input structure, a first inverting input structure, a first switch, an input chopper, a first transconductance amplifier, an output chopper, a first feedback capacitor and a second feedback capacitor, and a first in-phase input structure composed of a first resistor, a first capacitor, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch to replace the traditional Delta-Sigma modulator. The in-phase input structure of the present application can improve the linearity of the Delta-Sigma modulator, improve the defect of generating large voltage spikes and reduce thermal noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the circuit structure of a Delta-Sigma modulator in a specific embodiment of the present invention;

[0024] Figure 2 Schematic diagram of a switch control waveform of a Delta-Sigma modulator in a specific embodiment of the present invention;

[0025] Figure 3 A schematic diagram of the circuit structure of another Delta-Sigma modulator in a specific embodiment of the present invention;

[0026] Figure 4 A schematic diagram of the structure of a Delta-Sigma modulator in the related art;

[0027] Figure 5 It is a schematic diagram of a transconductance amplifier OTA1 in a first-stage integrator in a specific embodiment of the present invention;

[0028] Figure 6 It is a circuit structure schematic diagram of a first-stage common-mode feedback circuit in a specific embodiment of the present invention;

[0029] Figure 7Schematic diagram of the circuit structure of the second-stage common-mode feedback circuit in a specific embodiment of the present invention;

[0030] Figure 8 It is an equivalent circuit diagram when the first-stage integrator is used as an SC integrator in a specific embodiment of the present invention;

[0031] Fig. 9 FIG. 4 is an equivalent circuit diagram of a first-stage integrator when the RC integrator operates in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings to illustrate the principle and process of the Delta-Sigma modulator in the embodiments of the present invention.

[0033] Reference Figure 1 , the present invention provides a Delta-Sigma modulator.

[0034] The Delta-Sigma modulator may include a first integration module, a second integration module, a third integration module, an accumulation module and a comparator module; the first integration module, the second integration module and the third integration module are connected to the comparator module through the accumulation module.

[0035] The first integration module includes a first in-phase input structure, a first inverting input structure, a first switch S1, an input chopper X1, a first transconductance amplifier OTP1, an output chopper X2, a first feedback capacitor C4a and a second feedback capacitor C4b; the first in-phase input structure is connected to the first inverting input structure through the first switch S1; one end of the first feedback capacitor C4a and the first in-phase input structure are connected to the in-phase input terminal of the first transconductance amplifier OTP1 through the input chopper X1; one end of the second feedback capacitor C4b and the first inverting input structure are connected to the inverting input terminal of the first transconductance amplifier OTP1 through the input chopper X1; the other end of the first feedback capacitor C4a is connected to the inverting output terminal of the first transconductance amplifier OTP1 through the output chopper X2; the other end of the second feedback capacitor C4b is connected to the in-phase output terminal of the first transconductance amplifier OTP1 through the output chopper X2;

[0036] The circuit structure of the first non-inverting input structure is the same as that of the first inverting input structure;

[0037] Reference Figure 1 , the first in-phase input structure includes a first resistor R1a, a first capacitor C1a, a second switch S2a, a third switch S3a, a fourth switch S4a, a fifth switch S5a, a sixth switch S6a and a seventh switch S7a;

[0038] Reference Figure 1, one end of the first resistor R1a is connected to the differential input signal V inn The other end of the first resistor R1a is connected to the input chopper through the second switch S2a; one end of the first capacitor C1a is connected to the common mode level V through the third switch S3a. cm The other end of the first capacitor C1a is connected to the common mode voltage V through the fourth switch S4a. cm The other end of the first capacitor C1a is connected to the first reference voltage through the sixth switch S6a, the other end of the first capacitor C1a is connected to the second reference voltage through the seventh switch S7a, and one end of the first capacitor C1a is connected to the input chopper X1 through the third switch S3a.

[0039] Similarly, refer to Figure 1 , the first inverting input structure includes a first resistor R1b, a first capacitor C1b, a second switch S2b, a third switch S3b, a fourth switch S4b, a fifth switch S5b, a sixth switch S6b and a seventh switch S7b;

[0040] One end of the first resistor R1b is connected to the differential input signal V inp The other end of the first resistor R1b is connected to the input chopper through the second switch S2b; one end of the first capacitor C1b is connected to the common mode level through the third switch S3b, the other end of the first capacitor C1b is connected to the common mode level through the fourth switch S4b, the other end of the first capacitor C1b is connected to the first reference voltage through the sixth switch S6b, the other end of the first capacitor C1b is connected to the second reference voltage through the seventh switch S7b, and one end of the first capacitor C1b is connected to the input chopper X1 through the third switch S3b.

[0041] It can be understood that the input chopper X1 and the output chopper X2 both have a non-inverting input terminal and an inverting input terminal, and have a non-inverting input terminal and an inverting output terminal. The input chopper X1 does not change the positive and negative phases of the signal input to the input chopper X1, and the output chopper X2 does not change the positive and negative phases of the signal input to the output chopper X2.

[0042] Further, refer to Figure 1 In some feasible embodiments of the present application, the accumulation module includes the first accumulation subcircuit to the eighth accumulation subcircuit; the first accumulation subcircuit, the third accumulation subcircuit, the fifth accumulation subcircuit and the seventh accumulation subcircuit are connected in parallel to the comparator module; the second accumulation subcircuit, the fourth accumulation subcircuit, the sixth accumulation subcircuit and the eighth accumulation subcircuit are connected in parallel to the comparator module; the first accumulation subcircuit and the second accumulation subcircuit are connected to the differential input signal. Specifically, the first accumulation subcircuit is connected to the positive signal V of the differential input signal. inp Connect the second accumulator circuit to the negative signal V of the differential input signal innThe third accumulator subcircuit and the fourth accumulator subcircuit are connected to two output ends of the first integration module. Specifically, the third accumulator subcircuit is connected to the negative signal of the first integration module, and the fourth accumulator subcircuit is connected to the negative signal of the first integration module. The fifth accumulator subcircuit and the sixth accumulator subcircuit are connected to two output ends of the second integration module. Specifically, the fifth accumulator subcircuit is connected to the negative signal of the second integration module, and the sixth accumulator subcircuit is connected to the negative signal of the second integration module. The seventh accumulator subcircuit and the eighth accumulator subcircuit are connected to two output ends of the second integration module, specifically, the seventh accumulator subcircuit is connected to the negative signal of the third integration module, and the eighth accumulator subcircuit is connected to the negative signal of the third integration module.

[0043] Further, in some feasible embodiments of the present application, the first accumulating subcircuit, the second accumulating subcircuit, the third accumulating subcircuit, the fourth accumulating subcircuit, the fifth accumulating subcircuit, the sixth accumulating subcircuit, the seventh accumulating subcircuit and the eighth accumulating subcircuit have the same structure;

[0044] Each accumulation sub-circuit includes a second capacitor, an eighth switch and a ninth switch; one end of the eighth switch serves as the input end of each accumulation sub-circuit, the other end of the eighth switch is connected to one end of the second capacitor, one end of the second capacitor is connected to the common mode level through the ninth switch; the other end of the second capacitor serves as the output end of each accumulation sub-circuit.

[0045] Specifically, the first accumulation sub-circuit includes a second capacitor C2a, an eighth switch S8a and a ninth switch S9a; one end of the eighth switch S8a serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8a is connected to one end of the second capacitor C2a, and one end of the second capacitor C2a is connected to the common mode level through the ninth switch S9a; the other end of the second capacitor C2a serves as the output end of the first accumulation sub-circuit.

[0046] Specifically, the second accumulation sub-circuit includes a second capacitor C2b, an eighth switch S8b and a ninth switch S9b; one end of the eighth switch S8b serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8b is connected to one end of the second capacitor C2b, and one end of the second capacitor C2b is connected to the common mode level through the ninth switch S9b; the other end of the second capacitor C2b serves as the output end of the second accumulation sub-circuit.

[0047] Specifically, the third accumulation sub-circuit includes a second capacitor C2c, an eighth switch S8c and a ninth switch S9c; one end of the eighth switch S8c serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8c is connected to one end of the second capacitor C2c, and one end of the second capacitor C2c is connected to the common mode level through the ninth switch S9c; the other end of the second capacitor C2c serves as the output end of the third accumulation sub-circuit.

[0048] Specifically, the fourth accumulation sub-circuit includes a second capacitor C2d, an eighth switch S8d and a ninth switch S9d; one end of the eighth switch S8d serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8d is connected to one end of the second capacitor C2d, and one end of the second capacitor C2d is connected to the common mode level through the ninth switch S9d; the other end of the second capacitor C2d serves as the output end of the fourth accumulation sub-circuit.

[0049] Specifically, the fifth accumulation sub-circuit includes a second capacitor C2e, an eighth switch S8e and a ninth switch S9e; one end of the eighth switch S8e serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8e is connected to one end of the second capacitor C2e, and one end of the second capacitor C2e is connected to the common mode level through the ninth switch S9e; the other end of the second capacitor C2e serves as the output end of the fifth accumulation sub-circuit.

[0050] Specifically, the sixth accumulation sub-circuit includes a second capacitor C2f, an eighth switch S8f and a ninth switch S9f; one end of the eighth switch S8f serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8f is connected to one end of the second capacitor C2f, and one end of the second capacitor C2f is connected to the common mode level through the ninth switch S9f; the other end of the second capacitor C2f serves as the output end of the sixth accumulation sub-circuit.

[0051] Specifically, the seventh accumulation sub-circuit includes a second capacitor C2g, an eighth switch S8g and a ninth switch S9g; one end of the eighth switch S8g serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8g is connected to one end of the second capacitor C2g, and one end of the second capacitor C2g is connected to the common mode level through the ninth switch S9g; the other end of the second capacitor C2g serves as the output end of the seventh accumulation sub-circuit.

[0052] Specifically, the eighth accumulation sub-circuit includes a second capacitor C2h, an eighth switch S8h and a ninth switch S9h; one end of the eighth switch S8h serves as the input end of each accumulation sub-circuit, the other end of the eighth switch S8h is connected to one end of the second capacitor C2h, and one end of the second capacitor C2h is connected to the common mode level through the ninth switch S9h; the other end of the second capacitor C2h serves as the output end of the eighth accumulation sub-circuit.

[0053] Further, in some feasible embodiments of the present application, the modulator includes a first regulating switch S15a and a second regulating switch S15b; the first accumulating sub-circuit, the third accumulating sub-circuit, the fifth accumulating sub-circuit and the seventh accumulating sub-circuit are connected in parallel through the first regulating switch S15a and the common mode level V cmThe second accumulating sub-circuit, the fourth accumulating sub-circuit, the sixth accumulating sub-circuit and the eighth accumulating sub-circuit are connected in parallel through the second regulating switch S15b and the common mode level V cm connect.

[0054] Further, refer to Figure 1 as well as Figure 2 In some feasible embodiments of the present application, the second switch, the fourth switch, the first regulating switch and the second regulating switch are switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%. Specifically, Figure 1 In the figure, each switch is modulated by a continuous waveform signal, wherein switches labeled P1 and P1D have control waveforms with a duty cycle of 10%, and switches labeled P2 and P2D have control waveforms with a duty cycle of 90%.

[0055] Further, refer to Figure 1 In some feasible embodiments of the present application, the second integration module includes a second transconductance amplifier OTP2, a second non-inverting input structure, a second inverting input structure, a third feedback capacitor C5a and a fourth feedback capacitor C5b; the second non-inverting input structure is connected to the non-inverting input terminal of the second transconductance amplifier OTP2; the second inverting input structure is connected to the inverting input terminal of the second transconductance amplifier OTP2; one end of the third feedback capacitor C5a is connected to the non-inverting input terminal of the second transconductance amplifier OTP2; the other end of the third feedback capacitor C5a is connected to the inverting output terminal of the second transconductance amplifier OTP2; one end of the fourth feedback capacitor C5b is connected to the inverting input terminal of the second transconductance amplifier OTP2; the other end of the fourth feedback capacitor C5b is connected to the non-inverting output terminal of the second transconductance amplifier OTP2.

[0056] Further, refer to Figure 1 In some feasible embodiments of the present application, the third integration module includes a third transconductance amplifier OTP3, a third non-inverting input structure, a third inverting input structure, a fifth feedback capacitor C5c and a sixth feedback capacitor C5d.

[0057] The third non-inverting input structure is connected to the non-inverting input terminal of the third transconductance amplifier OTP3; the third inverting input structure is connected to the inverting input terminal of the third transconductance amplifier OTP3; one end of the fifth feedback capacitor C5c is connected to the non-inverting input terminal of the third transconductance amplifier OTP3; the other end of the fifth feedback capacitor C5c is connected to the inverting output terminal of the third transconductance amplifier OTP3; one end of the sixth feedback capacitor C5d is connected to the inverting input terminal of the third transconductance amplifier OTP3; the other end of the sixth feedback capacitor C5d is connected to the non-inverting output terminal of the third transconductance amplifier OTP3.

[0058] Further, in some feasible embodiments of the present application, the third in-phase input structure, the third in-phase input structure, the second in-phase input structure and the second in-phase input structure are the same.

[0059] Specifically, refer to Figure 1 , the second in-phase input structure includes a third capacitor C3a, a tenth switch S10a, an eleventh switch S11a, a twelfth switch S12a and a thirteenth switch S13a. In the second in-phase input structure, one end of the tenth switch S10a serves as an input end of the input structure, the other end of the tenth switch S10a is connected to one end of the third capacitor C3a, and the common mode level is connected to one end of the third capacitor C3a through the eleventh switch S11a; the other end of the third capacitor C3a is connected to one end of the thirteenth switch S13a, and the common mode level is connected to the other end of the third capacitor C3a through the twelfth switch S12a; the other end of the thirteenth switch S13a serves as an input end of the input structure.

[0060] Reference Figure 1 , the second inverting input structure includes a third capacitor C3b, a tenth switch S10b, an eleventh switch S11b, a twelfth switch S12b and a thirteenth switch S13b. In the second inverting input structure, one end of the tenth switch S10b serves as the input end of the input structure, the other end of the tenth switch S10b is connected to one end of the third capacitor C3b, and the common mode level is connected to one end of the third capacitor C3b through the eleventh switch S11b; the other end of the third capacitor C3b is connected to one end of the thirteenth switch S13b, and the common mode level is connected to the other end of the third capacitor C3b through the twelfth switch S12b; the other end of the thirteenth switch S13b serves as the input end of the input structure.

[0061] Reference Figure 1 The third in-phase input structure includes a third capacitor C3c, a tenth switch S10c, an eleventh switch S11c, a twelfth switch S12c and a thirteenth switch S13c. In the third in-phase input structure, one end of the tenth switch S10c serves as an input end of the input structure, the other end of the tenth switch S10c is connected to one end of the third capacitor C3c, and the common mode level is connected to one end of the third capacitor C3c through the eleventh switch S11c; the other end of the third capacitor C3c is connected to one end of the thirteenth switch S13c, and the common mode level is connected to the other end of the third capacitor C3c through the twelfth switch S12c; the other end of the thirteenth switch S13c serves as an input end of the input structure.

[0062] Reference Figure 1, the third inverting input structure includes a third capacitor C3d, a tenth switch S10d, an eleventh switch S11d, a twelfth switch S12d and a thirteenth switch S13d. In the third inverting input structure, one end of the tenth switch S10d serves as the input end of the input structure, the other end of the tenth switch S10d is connected to one end of the third capacitor C3d, and the common mode level is connected to one end of the third capacitor C3d through the eleventh switch S11d; the other end of the third capacitor C3d is connected to one end of the thirteenth switch S13d, and the common mode level is connected to the other end of the third capacitor C3d through the twelfth switch S12d; the other end of the thirteenth switch S13d serves as the input end of the input structure.

[0063] Further, in some feasible embodiments of the present application, the comparator module includes a comparator M1 and two fourteenth switches. The two fourteenth switches are S14a and S14b; the output end of the comparator M1 is the output end of the Delta-Sigma modulator; the first integration module, the second integration module and the third integration module are connected to the fourteenth switches through the accumulation module; and the fourteenth switch is connected to the comparator.

[0064] Further, in some feasible embodiments of the present application, the first switch, the thirteenth switch and the fourteenth switch are switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 90%; the twelfth switch is a switch modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%. Specifically, Figure 1 In the figure, each switch is modulated by a continuous waveform signal, wherein switches labeled P1 and P1D have control waveforms with a duty cycle of 10%, and switches labeled P2 and P2D have control waveforms with a duty cycle of 90%.

[0065] The specific calculation principle of this application is explained below with reference to the accompanying drawings:

[0066] The internal circuit of the Delta-Sigma modulator of the present application includes: a three-stage integrator and a comparator. The power supply voltage is 1.5V, Vrefp is 1.5V, V refn is 0V, V cm is 0.75V. For a 1kHz bandwidth, the sampling clock frequency FS is set to 256kHz and the oversampling ratio (OSR) is 128. The entire Delta-Sigma ADC is Figure 3 shown.

[0067] The detailed internal structure of the Delta-Sigma modulator is as follows Figure 3 As shown, it includes three-stage integrators and a subsequent comparator. Since the fully differential circuit structure has the advantages of improving the common mode rejection ratio and eliminating even harmonics, the modulator is implemented using a fully differential structure.

[0068] The modulator proposed in this embodiment adopts a third-order integrator cascade feedforward (CIFF) structure. It uses a one-bit quantizer to ensure excellent linearity of the DAC. The coefficients are selected so that the out-of-band gain (OBG) of the noise transfer function (NTF) is limited to 1.42 to ensure system stability.

[0069] Conventional technology uses low-voltage power supplies for analog and digital circuits to simplify power management and reduce power consumption and area. However, the use of switched capacitors (SCs) faces significant challenges under low-voltage power supply conditions.

[0070] Conventional technology uses complementary switches to improve switch linearity, but the improvement is limited and cannot meet high-precision requirements. Clock boost technology and bootstrap switches can effectively enhance switch linearity by generating higher voltage levels, but require additional hardware overhead.

[0071] Replacing the input switched capacitor integrator with the resistor integrator in the related art is a straightforward solution, such as Figure 4 However, due to the large voltage spikes generated at the input nodes of the OTA during the switched capacitor integrator operation, the continuous time (CT) integration of the input signal is disturbed, R I Considerable thermal noise is also introduced.

[0072] In order to solve the above problems, this embodiment proposes a low-voltage design based on a hybrid switch integrator, which effectively improves linearity without the need for bootstrap switches or clock boost technology. In addition, a timing with a non-50% duty cycle is proposed. This timing extends the integration time of the SC integrator, thereby relaxing the requirements for the OTA. At the same time, it reduces the resistance value in the resistor-capacitor (RC) integrator and reduces the thermal noise introduced by the integration resistor. In order to adapt to this timing, a corresponding adjustable Miller compensation two-stage A / AB class OTA design is proposed.

[0073] Use Figure 3 The circuit level implementation shown and Figure 2 The timing diagram shown implements a two-phase non-overlapping clock scheme to mitigate channel charge injection effects.

[0074] Figure 3In the circuit in, the first integrator adopts a hybrid switch integrator. During P1, the input signal is integrated by the RC integrator. At this time, the integration resistor RI remains at a fixed value (195kΩ), thus eliminating the nonlinearity caused by the switch conductance. In the P2 phase, the feedback signal of the DAC is integrated by the SC integrator, avoiding the sensitivity of clock jitter associated with the continuous-time Delta-Sigma modulator. The operation of the RC integrator and the SC integrator is separated by a switch, enabling them to operate in different phases. This avoids the influence of the voltage spike generated during the operation of the SC integrator on the integration of the input signal.

[0075] In the low frequency band, the 1 / f noise of the OTA limits the accuracy of the ADC. In order to suppress the low frequency noise, a chopper technique is used in the first integrator with a chopping frequency of Fs / 2. The DC offset and 1 / f noise of the OTA are modulated to the high frequency band and then filtered out by the digital filter.

[0076] For the hybrid switched integrator structure, the value of the integrator resistor RI is given by (1):

[0077]

[0078] Tint, in represents the time during each sampling period that the input signal is integrated by the RC integrator. Assume that the duty cycle of phase P1 is x and the sampling period is T S , then R I The value of should be determined as follows:

[0079]

[0080] As shown in (2), it can be observed that the smaller the duty cycle x, the smaller the R I The smaller the value of . Therefore, the baseband thermal noise power introduced by RI in the first integrator is:

[0081]

[0082] Assume that the on-resistance of S1 in the first integrator is Ron S1 =a*R I , then the thermal noise introduced by the switch is:

[0083]

[0084] Where k is the Boltzmann constant and T is the absolute temperature

[0085] C S1 The introduced KT / C noise is:

[0086]

[0087] Therefore, the total baseband thermal noise power introduced by the first integrator is:

[0088]

[0089] In R I =195kΩ and Ron S1 In the range of about 200Ω to 900Ω, parameter a = Ron S1 / R I It is estimated to be in the range of 0.1% to 0.4%. Therefore, the thermal noise and nonlinearity introduced by switch S1 are practically negligible.

[0090] From (6), it can be seen that by effectively increasing the sampling capacitor CS1, the thermal noise can be reduced. However, this comes at the expense of increasing the equivalent load capacitance of the integrator OTA, which requires more power consumption. In addition, reducing the duty cycle of the P1 phase also helps to minimize the overall thermal noise. Therefore, we propose a timing with a non-50% duty cycle, such as Figure 2 As shown, the duty cycle of P1 is 0.1 and the duty cycle of P2 is 0.9, which can reduce the thermal noise introduced by RI by 90% compared with the continuous-time integrator.

[0091] The DC gain, slew rate (SR), unity gain bandwidth (UGB), and output swing of the first-stage integrator OTA limit the overall accuracy of the modulator. Therefore, the design of the first-stage integrator OTA uses a two-stage A / AB class OTA to achieve the necessary output swing and gain, such as Figure 5 As shown in Figure 2. Since the second stage operates in Class AB mode, the slew rate limitation only applies to the first stage. In addition, due to the push-pull operation in the second stage, it exhibits twice the rectification efficiency of the Class A stage. For the same non-dominant pole, the output branch current can be approximated to half of the current used in the two-stage Class A circuit. The common-mode feedback circuit of the first and second stages of the OTA is shown in Figure 2. Figure 6 and Figure 7 They stabilize the first stage common-mode output voltage at V b2 , to establish the quiescent current required by the second stage and to stabilize the common-mode output voltage of the second stage at V cm Since the requirements on the OTA of the second and third integrators are relaxed, they are designed as simple and identical single-stage OTAs.

[0092] The increase in the duty cycle of the P2 phase means an increase in the integration time of the SC integrator within each sampling period. Therefore, the requirements for SR and UGB of OTA1 become relaxed. However, for the RC integrator, due to the decrease in RI, the UGB of the RC integrator (UGB = 1 / (RI*CI1)) increases. In order to ensure that the pole introduced by the finite UGB of OTA1 has a negligible impact on the system, the UGB of OTA 1 needs to be significantly higher than the UGB of the RC integrator. Therefore, when converting from an SC integrator to an RC integrator, the challenge becomes how to achieve higher speed without incurring additional power consumption. This problem is solved in this design by effectively utilizing the different equivalent load capacitances between the RC and SC integrators.

[0093] Figure 8 Shows the equivalent circuit diagram when the first-stage integrator is used as an SC integrator.

[0094] Fig. 9 represents an equivalent circuit diagram of the first stage integrator when the RC integrator operates.

[0095] exist Figure 8 In this case, the equivalent load capacitance is:

[0096] C LE,SC =C L1 +C I1 / / (C S1 +C P1 ) (7)

[0097] exist Fig. 9 In this case, the equivalent load capacitance is:

[0098] C LE,RC =C L2 +C I1 / / C P2 (8)

[0099] In the SC integrator, to mitigate KT / C noise, the sampling capacitor CS1 (2pF) and the integrator capacitor CI1 (10pF) are designed to be larger compared to the other parasitic capacitors CP1 and CP2 and the load capacitors CL1 and CL 2. Therefore, CLE,RC is significantly smaller than CLE,SC. Therefore, when converting from the SC integrator to the RC integrator, the lowest non-dominant pole of the OTA shifts from 2gm1 / CLE,SC to a much larger value of 2gm1 / CLE,RC. This feature allows greater adjustability of the Miller compensation capacitor, allowing it to be significantly reduced in the RC integration mode while still meeting the phase margin requirement. Figure 5 The specific circuit implementation is shown in FIG. 1 , where the Miller capacitor is configured in an adjustable mode. When the RC integrator is effective, switches SW1 and SW2 are turned off, and the Miller capacitor C M，RC =C M0In the case of SC integrator operation, switches SW1 and SW2 are closed and the Miller capacitor C M，SC =C M0 +N×C M0 =(N+1)C M0 =(N+1)C M，RC .

[0100] When the SC integrator is running, the UGB and SR of OTA are as follows:

[0101]

[0102] When the RC integrator is running, the UGB and SR of the OTA are as follows:

[0103]

[0104] During SC integration, the UGB and SR of the OTA are increased N-fold without changing the size, structure, or power consumption of the OTA.

[0105] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0106] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0107] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A Delta-Sigma modulator, characterized in that: include: A first integration module, a second integration module, a third integration module, an accumulation module and a comparator module; The first integration module, the second integration module and the third integration module are connected to the comparator module through the accumulation module; The first integration module includes a first non-inverting input structure, a first inverting input structure, a first switch, an input chopper, a first transconductance amplifier, an output chopper, a first feedback capacitor and a second feedback capacitor; the first non-inverting input structure is connected to the first inverting input structure through the first switch; One end of the first feedback capacitor and the first in-phase input structure are connected to the in-phase input end of the first transconductance amplifier through the input chopper; One end of the second feedback capacitor and the first inverting input structure are connected to the inverting input end of the first transconductance amplifier through the input chopper; The other end of the first feedback capacitor is connected to the inverting output end of the first transconductance amplifier through the output chopper; the other end of the second feedback capacitor is connected to the non-inverting output end of the first transconductance amplifier through the output chopper; The circuit structure of the first in-phase input structure is the same as that of the first inverting input structure; The first in-phase input structure includes a first resistor, a first capacitor, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch; One end of the first resistor is connected to the differential input signal, and the other end of the first resistor is connected to the input chopper through the second switch; one end of the first capacitor is connected to the common mode level through the third switch, the other end of the first capacitor is connected to the common mode level through the fourth switch, the other end of the first capacitor is connected to the first reference voltage through the sixth switch, the other end of the first capacitor is connected to the second reference voltage through the seventh switch, and one end of the first capacitor is connected to the input chopper through the third switch.

2. A Delta-Sigma modulator according to claim 1, characterized in that: The accumulation module includes the first accumulation sub-circuit to the eighth accumulation sub-circuit; the first accumulation sub-circuit, the third accumulation sub-circuit, the fifth accumulation sub-circuit and the seventh accumulation sub-circuit are connected in parallel to the comparator module; the second accumulation sub-circuit, the fourth accumulation sub-circuit, the sixth accumulation sub-circuit and the eighth accumulation sub-circuit are connected in parallel to the comparator module; the first accumulation sub-circuit and the second accumulation sub-circuit are connected to the differential input signal, the third accumulation sub-circuit and the fourth accumulation sub-circuit are connected to the two output ends of the first integration module; the fifth accumulation sub-circuit and the sixth accumulation sub-circuit are connected to the two output ends of the second integration module; the seventh accumulation sub-circuit and the eighth accumulation sub-circuit are connected to the two output ends of the second integration module.

3. A Delta-Sigma modulator according to claim 2, characterized in that: The first accumulation sub-circuit, the second accumulation sub-circuit, the third accumulation sub-circuit, the fourth accumulation sub-circuit, the fifth accumulation sub-circuit, the sixth accumulation sub-circuit, the seventh accumulation sub-circuit and the eighth accumulation sub-circuit have the same structure; each accumulation sub-circuit includes a second capacitor, an eighth switch and a ninth switch; one end of the eighth switch serves as an input end of each accumulation sub-circuit, the other end of the eighth switch is connected to one end of the second capacitor, and one end of the second capacitor is connected to the common mode level through the ninth switch; the other end of the second capacitor serves as an output end of each accumulation sub-circuit.

4. A Delta-Sigma modulator according to claim 3, characterized in that: The modulator includes a first regulating switch and a second regulating switch; the first accumulator sub-circuit, the third accumulator sub-circuit, the fifth accumulator sub-circuit and the seventh accumulator sub-circuit are connected in parallel and connected to the common mode level through the first regulating switch; the second accumulator sub-circuit, the fourth accumulator sub-circuit, the sixth accumulator sub-circuit and the eighth accumulator sub-circuit are connected in parallel and connected to the common mode level through the second regulating switch.

5. A Delta-Sigma modulator according to claim 4, characterized in that: The second switch, the fourth switch, the first regulating switch and the second regulating switch are switches modulated by a signal of a continuous waveform, wherein a duty cycle of the signal is equal to 10%.

6. A Delta-Sigma modulator according to claim 1, characterized in that: The second integration module includes a second transconductance amplifier, a second non-inverting input structure, a second inverting input structure, a third feedback capacitor and a fourth feedback capacitor; the second non-inverting input structure is connected to the non-inverting input terminal of the second transconductance amplifier; the second inverting input structure is connected to the inverting input terminal of the second transconductance amplifier; One end of the third feedback capacitor is connected to the non-inverting input end of the second transconductance amplifier; the other end of the third feedback capacitor is connected to the inverting output end of the second transconductance amplifier; one end of the fourth feedback capacitor is connected to the inverting input end of the second transconductance amplifier; The other end of the fourth feedback capacitor is connected to the non-inverting output end of the second transconductance amplifier.

7. A Delta-Sigma modulator according to claim 6, characterized in that: The third integration module includes a third transconductance amplifier, a third in-phase input structure, a third inverting input structure, a fifth feedback capacitor and a sixth feedback capacitor; The third in-phase input structure is connected to the in-phase input terminal of the third transconductance amplifier; the third inverting input structure is connected to the inverting input terminal of the third transconductance amplifier; one end of the fifth feedback capacitor is connected to the in-phase input terminal of the third transconductance amplifier; the other end of the fifth feedback capacitor is connected to the inverting output terminal of the third transconductance amplifier; one end of the sixth feedback capacitor is connected to the inverting input terminal of the third transconductance amplifier; The other end of the sixth feedback capacitor is connected to the in-phase output end of the third transconductance amplifier.

8. A Delta-Sigma modulator according to claim 7, characterized in that: The third in-phase input structure, the third inverting input structure, the second in-phase input structure and the second inverting input structure are the same, and any one of the input structures includes a third capacitor, a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch; One end of the tenth switch serves as the input end of the input structure, the other end of the tenth switch is connected to one end of the third capacitor, and the common mode level is connected to one end of the third capacitor through the eleventh switch; the other end of the third capacitor is connected to one end of the thirteenth switch, and the common mode level is connected to the other end of the third capacitor through the twelfth switch; the other end of the thirteenth switch serves as the input end of the input structure.

9. A Delta-Sigma modulator according to claim 8, characterized in that: The comparator module includes a comparator and a fourteenth switch; the output end of the comparator is the output end of the Delta-Sigma modulator; the first integration module, the second integration module and the third integration module are connected to the fourteenth switch through the accumulation module; the fourteenth switch is connected to the comparator.

10. A Delta-Sigma modulator according to claim 9, characterized in that: The first switch, the thirteenth switch and the fourteenth switch are switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 90%; the twelfth switch is a switch modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%.

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