Double-sided Topcon photovoltaic cell, preparation method thereof and photovoltaic module
By preparing high and low doped doped polysilicon layer and microalkali texture treatment in double-sided Topcon photovoltaic cells, the problems of parasitic light absorption and high dark current density during front metal recombination are solved, and the efficiency of photovoltaic cells is improved and Fill factor.
Patent Information
- Application Number
- CN202411182833.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-01-14
AI Technical Summary
The double-sided Topcon photovoltaic cells have problems of parasitic light absorption and high dark current density during the front and metal recombination process, which limits their efficiency improvement.
By preparing a passivation contact structure on the front and back of the silicon wafer, a high and low doped doped polysilicon layer is set up, and combined with a silicon oxide mask and a microalkali texture treatment, a selectively doped polysilicon passivation contact structure is formed to reduce the polysilicon layer's Parasitic light absorption and improves ohmic contact.
The photoelectric energy conversion efficiency of photovoltaic cells is improved, parasitic absorption is reduced, and the filling factor and battery efficiency are improved without affecting the passivation contact characteristics.
Smart Images
Figure CN119317244A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of photovoltaic cell technology, and in particular to a double-sided Topcon photovoltaic cell and a preparation method thereof, and a photovoltaic module. Background Art
[0002] Due to the continuous development of photovoltaic technology, the manufacturing technology cost of photovoltaic cells is constantly decreasing, and the market competition is more intense. High-quality and low-cost photovoltaic cells are the main factors to improve competitiveness. TOPCon (Tunnel Oxide Passivated Contact) cell is a new type of passivated contact cell. The cell achieves passivation by coating an ultra-thin silicon oxide layer on the surface of the cell silicon substrate and doping polysilicon. Its structure can achieve excellent surface passivation and selective collection of carriers, making double-sided Topcon photovoltaic cells the future technology route for the new generation of N-type silicon wafers.
[0003] Although bifacial Topcon photovoltaic cells have excellent passivation performance and high open circuit voltage Uoc, their efficiency potential is limited by the front compound and metal compound. The P-poly structure can greatly reduce the metal compound on the front while maintaining the front contact resistivity, but the use of thick polysilicon on the front of the solar cell will cause significant current loss due to parasitic light absorption. On the other hand, thinning the polysilicon on the front surface will increase the risk of metal paste burn-through during the metallization process, resulting in a higher dark current density J0, thus limiting the further improvement of the efficiency of bifacial Topcon photovoltaic cells. Summary of the invention
[0004] The purpose of the present application is to provide a double-sided Topcon photovoltaic cell. The double-sided Topcon photovoltaic cell provided in the present application can achieve good contact while reducing the parasitic absorption of Poly Si and the absorption of free carriers, thereby improving the photoelectric energy conversion efficiency of the double-sided Topcon photovoltaic cell.
[0005] The first aspect of the present application provides a double-sided Topcon photovoltaic cell, including a silicon wafer, the silicon wafer including a relative front side and a back side, the front side of the silicon wafer being divided into a gate line region and a non-gate line region, the non-gate line region of the front side of the silicon wafer being sequentially provided with a front tunneling oxide layer, a first front doped polysilicon layer, a first aluminum oxide layer and a first front anti-reflection film layer; the gate line region of the front side of the silicon wafer being sequentially provided with a front tunneling oxide layer, a first front doped polysilicon layer, an oxidation barrier layer, a second front doped polysilicon layer, a second aluminum oxide layer and a second front anti-reflection film layer, the doping type of the first front doped polysilicon layer and the second front doped polysilicon layer is P type; the doping concentration of the second front doped polysilicon layer is greater than the doping concentration of the first front doped polysilicon layer; the back side of the silicon wafer being sequentially provided with a back tunneling oxide layer, a back doped polysilicon layer and a back anti-reflection film layer; the doping type of the back doped polysilicon layer is N type.
[0006] In an optional manner, the thickness of the front tunneling oxide layer is greater than the thickness of the oxidation barrier layer;
[0007] In an optional manner, the thickness of the first front doped polysilicon layer is less than the thickness of the second front doped polysilicon layer;
[0008] Preferably, the thickness of the front tunneling oxide layer is 1.5-5 nm, and the thickness of the oxidation barrier layer is 1-2 nm;
[0009] Preferably, the thickness of the first front doped polysilicon layer is 20-60 nm, and the thickness of the second front doped polysilicon layer is 50-200 nm.
[0010] In an optional manner, the thickness of the first aluminum oxide layer and the second aluminum oxide layer is 4-10 nm;
[0011] In an optional manner, the thickness of the first front anti-reflection film layer and the second anti-reflection film layer is 65-90 nm;
[0012] In an optional manner, the thickness of the back anti-reflection film layer is 70-100 nm;
[0013] In an optional manner, the thickness of the back tunneling oxide layer is 1 nm-5 nm;
[0014] In an optional manner, the thickness of the back-doped polysilicon layer is 80-160 nm.
[0015] In an optional manner, the doping concentration of the first front doped polysilicon layer is 5-9×10 18 atom / cm 3 ; The doping concentration of the second front doped polysilicon layer is 3-6×10 19 atom / cm 3 .
[0016] In an optional manner, the front side of the silicon wafer is composed of a tower base and a pyramid structure;
[0017] Preferably, the height of the pyramid is 300-400 nm, the size of the base is 3-6 μm, and the reflectivity is 27-29%.
[0018] The second aspect of the present application provides a method for preparing the photovoltaic cell of the first aspect of the present application, comprising the following steps:
[0019] Step 101: Select a silicon wafer and perform double-sided polishing on the silicon wafer;
[0020] Step 102: depositing a back tunneling oxide layer and a back intrinsic amorphous silicon layer in sequence on the surface of the silicon wafer;
[0021] Step 103: performing high-temperature phosphorus diffusion so that the back intrinsic amorphous silicon layer forms a back doped polysilicon layer;
[0022] Step 104: removing the wrap-around plating on the front and side surfaces of the silicon wafer, and then performing surface treatment on the front surface of the silicon wafer;
[0023] Step 105: depositing a front tunneling oxide layer, a front intrinsic amorphous silicon layer, an oxidation barrier layer and a front doped amorphous silicon layer in sequence on the surface of the silicon wafer;
[0024] Step 106: forming a silicon oxide mask on the front side of the silicon wafer; the pattern of the mask is the same as the pattern of the gate line on the front side of the silicon wafer; the silicon oxide film completely covers the gate line area;
[0025] Step 107: etching the front side of the silicon wafer to remove the oxidation barrier layer in the non-gate line area and the front doped amorphous silicon layer and silicon oxide mask;
[0026] Step 108: performing high-temperature boron diffusion so that the front intrinsic amorphous silicon layer and the front doped amorphous silicon layer are formed into a first front doped polysilicon layer and a second front doped polysilicon layer respectively;
[0027] Step 109: removing the wrap-around plating on the front and back sides of the silicon wafer;
[0028] Step 110: depositing an aluminum oxide layer on the front side of the silicon wafer;
[0029] Step 111: depositing anti-reflection film layers on the front side and the back side of the silicon wafer respectively;
[0030] Step 112: Prepare a front electrode and a back electrode on the gate line region on the front side of the silicon wafer and on the back side of the silicon wafer, respectively.
[0031] In an optional manner, the thickness of the silicon oxide mask is 5-7 nm;
[0032] In an optional manner, the width of the silicon oxide mask is 2-4 times the width of the gate line on the front side of the silicon wafer.
[0033] In an optional manner, step 104: removing the wrap-around plating on the front and side surfaces of the silicon wafer, and then performing a micro-alkali texturing treatment on the front surface of the silicon wafer, so that a surface consisting of a tower base and a pyramid structure is formed on the front surface of the silicon wafer;
[0034] Preferably, a NaOH solution is used for slight alkaline texturing treatment;
[0035] More preferably, the mass concentration of NaOH in the NaOH solution is 1-3%, and the mass concentration of the additive is 1%-3%; the additive NaOH is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter.
[0036] In an optional manner, in step 107, the etching solution is a NaOH solution and an HF solution; the back intrinsic amorphous silicon layer and the front intrinsic amorphous silicon layer are removed by using the NaOH solution; and the silicon oxide mask and the oxidation barrier layer are removed by using the HF solution;
[0037] Preferably, the mass concentration of the NaOH solution is 1-3%; the volume concentration of the HF solution is 15-50%.
[0038] Preferably, the mass concentration of the NaOH solution is 1-3%; the volume concentration of the HF solution is 15-50%.
[0039] The third aspect of the present application provides a photovoltaic module, comprising the double-sided Topcon photovoltaic cell of the first aspect of the present application or the photovoltaic cell prepared in the second aspect of the present application.
[0040] Compared with the prior art, this application:
[0041] (1) The double-sided Topcon photovoltaic cell prepared in the present application has passivation contact structures prepared on the front and back sides respectively, and by establishing a selectively doped polysilicon passivation contact structure, a high- and low-doped doped polysilicon layer structure is set in the selectively doped polysilicon area, which improves the passivation effect of the front surface of the cell while minimizing the parasitic light absorption of the polysilicon layer and ensuring good contact performance, thereby improving the electrical performance of the photovoltaic cell.
[0042] (2) The present application adopts the method of pre-doping an intrinsic amorphous silicon layer (i.e., a front-side doped amorphous silicon layer) in combination with a silicon oxide mask. During high-temperature boron diffusion, in addition to the diffusion source introduced, the front-side doped amorphous silicon layer can be used as a doping source to dope the front-side intrinsic amorphous silicon layer, thereby forming a high- and low-doped doped polysilicon layer structure.
[0043] (3) The front surface morphology formed by the micro-alkaline texturing treatment provided by the present invention has both local polishing and local micro-texturing, which can improve the ohmic contact and enhance the fill factor without affecting the passivation contact characteristics; and the micro-alkaline texturing sample has a significant fill factor advantage at a shorter thermal oxidation time, matching the front SiOx / p+ polysilicon passivation contact structure, further increasing the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0045] Figure 1 A schematic diagram showing an embodiment of the passivation layer structure of a double-sided Topcon photovoltaic cell of the present application.
[0046] Reference numerals:
[0047] 10-silicon wafer; 111-front tunneling oxide layer; 112-oxidation blocking layer; 121-first front doped polysilicon layer; 122-second front doped polysilicon layer; 131-first aluminum oxide layer; 132-second aluminum oxide layer; 141-first front anti-reflection film layer; 142-second front anti-reflection film layer; 15-back tunneling oxide layer; 16-back doped polysilicon layer; 17-back anti-reflection film layer. DETAILED DESCRIPTION
[0048] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0049] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.
[0050] The first aspect of the present application provides a double-sided Topcon photovoltaic cell, such as Figure 1 As shown, the photovoltaic cell comprises:
[0051] The silicon wafer 10 is an N-type single crystal silicon wafer, which refers to a silicon wafer obtained by squaring, chamfering, slicing, cleaning and sorting a crystal rod grown by the Czochralski method.
[0052] The silicon wafer 10 includes a relative front side and a back side. After the silicon wafer is prepared into a photovoltaic cell, it will be prepared into a photovoltaic module. The photovoltaic module needs to have one side mainly used to face the sun and absorb sunlight. The side facing the sunlight is generally used as the front side; the other side opposite to the front side is called the back side.
[0053] The front side of the silicon wafer 10 is divided into a gate line area and a non-gate line area. Electrodes are required in photovoltaic cells to collect and transmit current. Electrodes are generally called gate lines. Gate lines are divided into main gate lines and secondary gate lines. Compared with main gate lines, secondary gate lines are more numerous and narrower in width. In some cells, main gate lines may not be set. The gate line area of this application refers to the area where the secondary gate lines printed later are located; the non-gate line area of this application refers to the area where the secondary gate lines will not be prepared later.
[0054] The non-gate line area on the front side of the silicon wafer 10 is sequentially provided with a front tunneling oxide layer 111, a first front doped polysilicon layer 121, a first aluminum oxide layer 131 and a first front anti-reflection film layer 141; the gate line area on the front side of the silicon wafer is sequentially provided with a front tunneling oxide layer 111, a first front doped polysilicon layer 121, an oxidation barrier layer 112, a second front doped polysilicon layer 122, a second aluminum oxide layer 132 and a second front anti-reflection film layer 142; the doping type of the first front doped polysilicon layer 121 and the second front doped polysilicon layer 122 is P type; the doping concentration of the second front doped polysilicon layer 122 is greater than the doping concentration of the first front doped polysilicon layer 121;
[0055] The back side of the silicon wafer 10 is provided with a back side tunneling oxide layer 15 , a back side doped polysilicon layer 16 and a back side anti-reflection film layer 17 in sequence; the doping type of the back side doped polysilicon layer is N type.
[0056] By preparing a passivation contact structure on the front and back sides of a photovoltaic cell, and forming a high- and low-doped doped polysilicon layer structure in the gate line area on the front side of the photovoltaic cell, the doping concentration of the first front doped polysilicon layer 121 is greater than the doping concentration of the second front doped polysilicon layer 122; and an oxidation blocking layer 112 is arranged between the first front doped polysilicon layer 121 and the second front doped polysilicon layer 122, and the high-concentration and low-concentration doped polysilicon layers form high and low potential barriers to improve the carrier transmission efficiency. In addition, by selectively doping the polysilicon layer in the area, that is, only arranging the oxidation blocking layer 112 and the second front doped polysilicon layer 122 in the gate line area, the parasitic light absorption of the polysilicon layer can be reduced, so that more light can enter the battery, thereby increasing the photoelectric conversion efficiency of the battery.
[0057] In an optional manner, the thickness of the front tunneling oxide layer is greater than the thickness of the oxidation barrier layer; in some specific embodiments, the thickness of the front tunneling oxide layer is 1.5-5nm, for example, 1.5nm, 2nm, 3nm, 4nm, 5nm. The thickness of the oxidation barrier layer is 1-2nm, for example, 1nm, 1.5nm or 2nm. The thickness of the oxidation barrier layer cannot be too thin, otherwise it cannot block the corrosion from the interface. The thickness of the oxidation barrier layer cannot be too thick, otherwise it will completely block the boron from entering the front amorphous silicon layer, affecting the barrier effect and doping effect.
[0058] In an optional manner, the thickness of the second front doped polysilicon layer is greater than that of the first front doped polysilicon layer; in some specific embodiments, the thickness of the first front doped polysilicon layer is 20-60nm; for example, it can be 20nm, 22nm, 24nm, 25nm, 26nm, 28nm, 29nm, 30nm, 32nm, 35nm, 40nm, 45nm, 50nm, 55nm or 60nm. The thickness of the second front doped polysilicon layer is 50-200nm; for example, it can be 50nm, 53nm, 55nm, 57nm, 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm, 80nm, 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm, 190nm, 195nm or 200nm. Too thick a front-side doped polysilicon layer will increase parasitic absorption. By selectively setting the doped polysilicon layer, two layers of doped polysilicon layers are set in the gate line area to prevent burn-through during printing, and a thinner first front-side doped polysilicon layer is set in the non-gate line area, thereby effectively reducing parasitic absorption.
[0059] In an optional manner, the thickness of the first aluminum oxide layer and the second aluminum oxide layer is 4-10 nm; for example, it can be 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.
[0060] In an optional manner, the thickness of the first front anti-reflection film layer and the second anti-reflection film layer is 65-90nm; for example, it can be 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm, 80nm, 81nm, 85nm or 90nm.
[0061] In an optional manner, the thickness of the back anti-reflection film layer is 70-100 nm; for example, it can be 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, 81 nm, 85 nm, 90 nm, 95 nm or 100 nm.
[0062] In an optional manner, the thickness of the back tunneling oxide layer is 1-5 nm; for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.
[0063] In one optional embodiment, the thickness of the back-doped polysilicon layer is 80-160nm; for example, it can be 80nm, 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm or 160nm.
[0064] In an optional manner, the doping concentration of the first front doped polysilicon layer is 5-9×10 18 atom / cm 3 ; For example, it can be 5×10 18 atom / cm 3 , 6×10 18 atom / cm 3 ,7×10 18 atom / cm 3 , 8×10 18 atom / cm 3 or ×10 18 atom / cm 3 ; The doping concentration of the second front doped polysilicon layer is 3-6×10 19 atom / cm 3 , for example, it can be 3×10 19 atom / cm 3 , 4×10 19 atom / cm 3 , 5×1019 atom / cm 3 or 6×10 19 atom / cm 3 .
[0065] In an optional manner, the front side of the silicon wafer is composed of a tower base and a pyramid structure; the tower base and the pyramid structure are surface morphologies formed by local polishing and local micro-texturing; by preparing this local polishing and local micro-texturing surface morphology on the front side of the silicon wafer, a front tunneling layer is deposited on this structure, thereby improving the ohmic contact and increasing the filling factor without affecting the passivation contact characteristics, and the slightly alkaline textured sample has a significant filling factor advantage at a shorter thermal oxidation time, matching the front SiOx / p+ polysilicon passivation contact structure, further increasing the photoelectric conversion efficiency of the battery.
[0066] Preferably, the pyramid height is 300-400nm, for example, 300nm, 350nm or 400nm; the base size is 3-6μm, for example, 3μm, 4μm, 5μm or 6μm; the reflectivity is 27-29%, for example, 27%, 28% or 29%.
[0067] The pyramid structure refers to a surface morphology structure similar to a pyramid, and the tower base structure refers to the surface morphology structure after the top of the pyramid structure is cut off. In some specific embodiments, the pyramid structure can be formed by laser etching, mechanical method or plasma etching. In some specific embodiments, the tower base structure can be formed by alkali polishing.
[0068] The second aspect of the present application provides a method for preparing a photovoltaic cell, comprising the following steps:
[0069] Step 101: Select a silicon wafer and perform double-sided polishing on the silicon wafer;
[0070] In this step, the silicon wafer is an N-type single crystal silicon wafer, which refers to a silicon wafer obtained by squaring, chamfering, slicing, cleaning and sorting a crystal rod grown by the Czochralski method.
[0071] The silicon wafer includes a front side and a back side opposite to each other. Both sides of the silicon wafer, i.e., the front side and the back side, are polished so that a tower base structure is formed on the surface of the silicon wafer, thereby enabling the deposition of a passivation layer. In some specific embodiments, the alkali polishing is performed using an aqueous solution containing a NaOH solution and an additive. The additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a degassing agent, or a promoter.
[0072] Step 102: depositing a back tunneling oxide layer and a back intrinsic amorphous silicon layer on the surface of the silicon wafer in sequence;
[0073] In this step, a back tunneling oxide layer and a back intrinsic amorphous silicon layer are deposited on the surface (front, back and side) of the silicon wafer; for example, LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma-Enhanced Chemical Vapour Deposition) can be used.
[0074] In some optional embodiments, the deposition thickness of the back tunneling oxide layer is 1-5 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.
[0075] In some optional embodiments, the thickness of the back intrinsic amorphous silicon layer is 80-160 nm; for example, it can be 80nm, 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm or 160nm.
[0076] In some optional methods, the LPCVD method is used to deposit the back tunneling oxide layer and the back intrinsic amorphous silicon layer; in some specific embodiments, the process parameters are: oxygen flow rate is 30000-50000sccm; SiH4 flow rate is 100-1000sccm; deposition temperature is 550-650°C, and deposition time is 110-200 minutes.
[0077] Step 103: performing high temperature phosphorus diffusion so that the intrinsic amorphous silicon layer on the back side of the silicon wafer forms a back side doped polysilicon layer;
[0078] In this step, the back intrinsic amorphous silicon layer is formed into a back doped polysilicon layer through high-temperature phosphorus diffusion; the doping type of the doped polysilicon layer is N-type, and the high-temperature diffusion can be processed by diffusion using POCL3 gas.
[0079] In some optional methods, a tubular thermal diffusion device is used to perform high-temperature phosphorus diffusion at high temperature, POCL3 is used as a reaction gas, the flow rate of POCL3 is 1000-2000sccm, the processing temperature is 750-950°C, and the processing time is 70-100 minutes.
[0080] Step 104: removing the wrap-around plating on the front and side surfaces of the silicon wafer, and then performing surface treatment on the front surface of the silicon wafer;
[0081] In this step, due to the previous steps, passivation layers (back tunneling oxide layer and back doped polysilicon layer) are prepared on the front, back and side of the silicon wafer. In the case where only the structure of the passivation layer on the back of the silicon wafer needs to be retained, the wrap-around plating on the front and back of the silicon wafer (i.e., the passivation layers on the front and back) needs to be removed. The wrap-around plating is generally removed by HF, and the PSG layer (phosphosilicate glass layer) is retained;
[0082] In some optional methods, in a wet process, a HF solution with a volume concentration of 20-50% is used to remove the wrap-around plating on the front and back sides of the silicon wafer.
[0083] After removing the wrap-around plating on the front and back sides of the silicon wafer, the front side of the silicon wafer is surface treated. In some optional methods, a NaOH solution may be used for the surface treatment to form a pyramid structure and / or a tower base structure on the surface.
[0084] In some optional manners, step 104: removing the wrap-around plating on the front and side surfaces of the silicon wafer, and then performing a slight alkali texturing treatment on the front surface of the silicon wafer, so that a surface consisting of a tower base and a pyramid structure is formed on the front surface of the silicon wafer;
[0085] In some optional methods, a NaOH solution is used for a slightly alkaline texturing treatment; wherein the mass concentration of NaOH in the NaOH solution is 1-3%, and the mass concentration of the additive is 1%-3%; the additive NaOH is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter. The formation of the SiOx / p+ polysilicon passivation contact structure is significantly affected by the surface morphology, which not only affects the contact resistance, but also affects the passivation effect and the photoelectric conversion efficiency. In the present application, a slightly alkaline texturing treatment is performed on the front side of the silicon wafer by using a NaoH solution, so that the morphology of the silicon wafer surface includes a pyramid and a tower base structure, thereby effectively improving the passivation effect, improving the contact resistance, and improving the photoelectric conversion efficiency.
[0086] Step 105: depositing a front tunneling oxide layer, a front intrinsic amorphous silicon layer, an oxidation barrier layer and a front doped amorphous silicon layer on the surface of the silicon wafer in sequence;
[0087] In this step, a front tunneling oxide layer, a front intrinsic amorphous silicon layer, an oxidation barrier layer and a front doped amorphous silicon layer are deposited on the surface (front, back and side) of the silicon wafer; for example, LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma-Enhanced Chemical Vapour Deposition) can be used.
[0088] In some optional embodiments, the thickness of the front doped amorphous silicon layer is greater than the thickness of the front intrinsic amorphous silicon layer;
[0089] In some optional embodiments, the thickness of the front intrinsic amorphous silicon layer is 20-60 nm; for example, it can be 20 nm, 22 nm, 24 nm, 25 nm, 26 nm, 28 nm, 29 nm, 30 nm, 32 nm, 35 nm, 40 nm, 45 nm or 50 nm.
[0090] In some optional embodiments, the thickness of the front doped amorphous silicon layer is 50-200nm; for example, it can be 50nm, 53nm, 55nm, 57nm, 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm, 80nm, 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm, 190nm, 195nm or 200nm.
[0091] In some optional embodiments, the thickness of the front tunneling oxide layer is 1.5-5 nm, for example, 1.5 nm, 2 nm, 3 nm, 4 nm, or 5 nm.
[0092] The thickness of the oxidation barrier layer is 1-2 nm, for example, 1 nm, 1.5 nm or 2 nm.
[0093] In some optional methods, the LPCVD method is used for deposition; in some specific embodiments, the process parameters are: oxygen flow rate is 20000-50000 cssm; SiH4 flow rate is 400-1500 sccm; deposition temperature is 550-650°C, deposition time is 110-200 minutes; boron source gas flow rate is 300-1800 sccm, and the boron source is BCL3.
[0094] Step 106: forming a silicon oxide mask on the front side of the silicon wafer; the pattern of the silicon oxide mask is the same as the pattern of the gate line on the front side of the silicon wafer; the silicon oxide film completely covers the gate line area;
[0095] In this step, a silicon oxide mask is formed on the front side of the silicon wafer, and the mask covers the gate line area, so as to facilitate the subsequent preparation of the selective polysilicon layer.
[0096] In an optional manner, the thickness of the silicon oxide mask is 5-7 nm; for example, it can be 5 nm, 6 nm or 7 nm.
[0097] In an optional manner, the width of the silicon oxide mask is 2-4 times the width of the gate line on the front side of the silicon wafer; for example, it can be 2 times, 2.5 times, 3 times, 3.5 times or 4 times.
[0098] In an optional manner, a laser is used to prepare a silicon oxide mask;
[0099] In a specific embodiment, the laser process parameters are: laser power is 3-6W, and laser scanning speed is 300-500mm / s.
[0100] Step 107: etching the front side of the silicon wafer to remove the silicon oxide mask and the oxide barrier layer in the non-gate line area and the front doped amorphous silicon layer;
[0101] In this step, the silicon oxide mask and the oxidation barrier layer in the non-gate line area and the front doped amorphous silicon layer are removed by etching, thereby preparing the oxidation barrier layer in the gate line area and the front doped amorphous silicon layer.
[0102] Due to the existence of the silicon oxide mask, when alkaline etching is performed on the silicon wafer with the silicon oxide mask, the area protected by the mask will not be corroded and damaged, while the front doped amorphous silicon layer in the area without mask protection will be corroded in the alkaline solution; due to the existence of the oxidation barrier layer, the corrosion at the interface of the oxide layer will be slowed down or even stopped, and the front intrinsic amorphous silicon layer will not be corroded. At this time, a structure with different thickness differences is formed on the front side of the silicon wafer, that is, the front doped amorphous silicon layer in the mask protection area and the front intrinsic amorphous silicon layer have different thickness differences; then, the silicon oxide mask and the oxide layer in the non-gate line area are removed by etching with an acidic solution.
[0103] In a specific embodiment, the etching solution is NaOH solution and HF solution; the front doped amorphous silicon layer is removed by using NaOH solution; the silicon oxide mask and the oxidation barrier layer are removed by using HF solution;
[0104] Specifically, NaOH solution is first used to remove the front doped amorphous silicon layer in the back and front non-silicon oxide mask areas (that is, the front non-gate line areas); then HF solution is used to remove the oxide barrier layer on the back, the oxide barrier layer on the front non-gate line areas, and the silicon oxide mask.
[0105] Preferably, the mass concentration of the NaOH solution is 30%-60%; the volume concentration of the HF solution is 25-55%.
[0106] Step 108: performing high-temperature boron diffusion so that the front intrinsic amorphous silicon layer and the front doped amorphous silicon layer are respectively formed into a first front doped polysilicon layer and a second front doped polysilicon layer;
[0107] In this step, the front intrinsic amorphous silicon layer and the front doped amorphous silicon layer are respectively formed into a first front doped polysilicon layer and a second front doped polysilicon layer by high temperature boron diffusion.
[0108] Due to the presence of doping in the front doped amorphous silicon layer, during the high-temperature diffusion process, in addition to the introduced doping source, it itself also serves as a doping source to dope the front intrinsic amorphous silicon layer, and finally forms a doped polysilicon layer with different doping concentrations.
[0109] In an optional method, a tubular thermal diffusion device is used for high-temperature diffusion at high temperature, BCL3 is used as the reaction gas, N2 is used as the protective gas, the processing time is 120-180 minutes, the processing temperature is 800-950°C, and the BCL3 flow rate is 300-800sccm.
[0110] Step 109: removing the wrap-around plating on the front and back sides of the silicon wafer;
[0111] In this step, the BSG layer formed on the front side of the silicon wafer and the wrap-around plating on the back side of the silicon wafer in the previous step are removed.
[0112] In an optional manner, HF combined with NaOH solution is used to remove the wrap-around plating;
[0113] Specifically, HF solution is first used to remove the BSG on the back or edge, and then NaOH solution is used to remove the second front-doped polysilicon layer formed by the front-doped amorphous silicon layer on the back; HF solution is used to remove the front BSG layer and the wrap-around and PSG layers formed by the front tunnel oxide layer on the back.
[0114] In a specific embodiment, the volume concentration of the HF solution is 20-50%;
[0115] In a specific embodiment, the mass concentration of the NaOH solution is 1%-3%.
[0116] Step 110: depositing an aluminum oxide layer on the front side of the silicon wafer;
[0117] In this step, an aluminum oxide layer is prepared on the front side of the silicon wafer to improve the passivation and impurity gettering effects on the surface of the silicon wafer; due to the previous preparation of the selective passivation layer, the thickness of the non-gate line area and the gate line area on the front side of the silicon wafer are different, so a first aluminum oxide layer is formed in the non-gate line area on the front side of the silicon wafer; and a second aluminum oxide layer is formed in the gate line area on the front side of the silicon wafer.
[0118] In an optional manner, ALD is used to prepare the aluminum oxide layer, with trimethylaluminum (TMA) as the aluminum source and vaporized water (H2O) or gaseous oxygen (O2) as the oxygen (O) source, two or more chemical vapor precursors are alternately introduced into the reaction chamber, and react on the surface of the substrate to form an aluminum oxide layer.
[0119] In an optional manner, the thickness of the first aluminum oxide layer and the second aluminum oxide layer is 4-8 nm; for example, it can be 4 nm, 5 nm, 6 nm, 7 nm or 8 nm.
[0120] Step 111: depositing anti-reflection film layers on the front side and the back side of the silicon wafer respectively;
[0121] In this step, anti-reflection film layers are prepared on the front and back sides of the silicon wafer; due to the previous preparation of the selective passivation layer, the thickness of the non-gate line area and the gate line area on the front side of the silicon wafer are different, so a first front anti-reflection film layer is formed in the non-gate line area on the front side of the silicon wafer; and a front anti-reflection film layer is formed in the gate line area on the front side of the silicon wafer.
[0122] In an optional manner, PECVD is used to prepare the anti-reflection film layer.
[0123] In an optional manner, the back anti-reflection film layer includes at least one of SiNx and SiOx.
[0124] In an optional embodiment, the thickness of the first front anti-reflection film layer and the second anti-reflection film layer is 60-95nm; for example, it can be 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm, 80nm, 81nm, 85nm, 90nm or 95nm.
[0125] In an optional manner, the thickness of the back anti-reflection film layer is 60-95 nm, for example, 60 nm, 62 nm, 64 nm, 65 nm, 66 nm, 68 nm, 69 nm, 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, 81 nm, 85 nm, 90 nm or 95 nm.
[0126] Step 112: Prepare a front electrode and a back electrode on the gate line regions of the front side and the back side of the silicon wafer respectively.
[0127] In this step, electrodes are prepared on the front and back sides of the silicon wafer. The electrodes are screen-printed, and the main grid and the auxiliary grid are printed on the front and back sides of the silicon wafer. After sintering and light injection, the electrodes are fixed on the surface of the cell to obtain the final product, the double-sided Topcon photovoltaic cell.
[0128] A third aspect of the present application provides a photovoltaic assembly, comprising the photovoltaic cell of the first aspect of the present application or the photovoltaic cell prepared by the third aspect of the present application.
[0129] The following describes in detail the preparation method of the double-sided Topcon photovoltaic cell disclosed in the first aspect and the photovoltaic cell disclosed in the second aspect of the present application with several specific embodiments. It is worth noting that the following description is only an exemplary description and not a specific limitation of the invention.
[0130] Example 1
[0131] Step 1: Select an N-type single crystal silicon wafer with a resistivity of 0.5 to 2.5 Ω·cm, a size of 182×182 mm, and a thickness of 130 μm, and polish both sides of the N-type single crystal silicon wafer with a NaOH aqueous solution;
[0132] Step 2: using LPCVD to sequentially deposit a back tunneling oxide layer and a back intrinsic amorphous silicon layer on the surface of the silicon wafer;
[0133] The deposition temperature is 590° C., the oxygen flow rate is 40,000 sccm for 900 seconds, and the SiH4 flow rate is 900 sccm for 120 minutes.
[0134] Step 3: Use a tubular thermal diffusion device to perform high-temperature diffusion at high temperature, use POCL3 as the reaction gas, the gas flow rate is 1500sccm, the processing temperature is 850°C, and the processing time is 90 minutes.
[0135] Step 4: Use wet equipment to remove the wrap-around plating on the front and back sides of the silicon wafer in a 40% volume concentration HF solution; then use NaOH solution to perform a micro-alkaline texturing treatment on the front side of the silicon wafer to form a surface morphology with local polishing and local micro-texture; wherein the mass concentration of NaOH is 1.5%, the mass concentration of the additive is 1.5%, and the back side PSG layer is retained with a thickness of 30-80nm.
[0136] Step 5: LPCVD is used to deposit the front tunneling oxide layer, the front intrinsic amorphous silicon layer, the oxidation barrier layer and the front doped amorphous silicon layer on the surface of the silicon wafer; wherein the oxygen flow rate is 40000sccm; the SiH4 flow rate is 800sccm; the deposition temperature is 630°C, and the deposition time is 1500 minutes. The boron source gas flow rate is 900sccm, and the boron source is BCL3.
[0137] Step 6: Use a 355nm nanosecond ultraviolet laser to oxidize the front side of the silicon wafer to form a silicon oxide mask in the gate line area. The pattern of the silicon oxide mask is the same as the pattern of the gate line on the front side of the silicon wafer; the thickness of the silicon oxide mask is 5nm, and the width of the silicon oxide mask is twice the width of the gate line; wherein, the laser power is controlled at 5W, and the laser scanning control speed is controlled at 400mm / s.
[0138] Step 7: Use a NaOH solution with a mass concentration of 40% to remove the front doped amorphous silicon layer on the back and front non-silicon oxide mask areas of the silicon wafer; then use an HF solution with a volume concentration of 35% to remove the oxide barrier layer on the back, the oxide barrier layer on the front non-silicon oxide mask area, and the silicon oxide mask.
[0139] Step 8: Use a tubular thermal diffusion device to perform high-temperature diffusion at high temperature, use BCL3 as the reaction gas, N2 as the protective gas, the processing time is 160 minutes, the processing temperature is 950°C, and the boron source flow rate is 700sccm.
[0140] Step 9: Use a cleaning machine to remove all BSG on the back and around the edge by floating on water (the back side contacts the acid solution) in a 35% by volume HF solution, and then use a 1-3% by mass concentration NaOH solution to clean and remove the doped polysilicon layer on the back side formed by the front doped amorphous silicon layer; the cleaning temperature is 65°C; finally, use a 35% by volume HF solution to remove the front BSG layer, the back oxide layer formed by the front tunnel oxide layer, and the back PSG layer.
[0141] Step 10: Prepare an aluminum oxide layer on the front side of the silicon wafer; form a first aluminum oxide layer in the non-gate line area on the front side of the silicon wafer; and form a second aluminum oxide layer in the gate line area on the front side of the silicon wafer.
[0142] Step 11: prepare anti-reflection film layers on the front and back sides of the silicon wafer; form a first front anti-reflection film layer in the non-gate line area on the front side of the silicon wafer; form a front anti-reflection film layer in the gate line area on the front side of the silicon wafer; and form a back anti-reflection film layer on the back side of the silicon wafer.
[0143] Step 12: Prepare a front electrode on the front side of the silicon wafer, and prepare a back electrode on the back side of the silicon wafer.
[0144] Through the above steps, a finished double-sided Topcon double-sided battery is prepared, wherein Figure 1As shown, the photovoltaic cell includes a silicon wafer 10, and a front tunneling oxide layer 111, a first front doped polysilicon layer 121, a first aluminum oxide layer 131 and a first front silicon nitride layer 141 are sequentially arranged on the non-gate line area on the front side of the silicon wafer 10; a front tunneling oxide layer 111, a first front doped polysilicon layer 121, an oxidation barrier layer 112, a second front doped polysilicon layer 122, a second aluminum oxide layer 132, a second front silicon nitride layer 142 and a front electrode (not shown) are sequentially arranged on the gate line area on the front side of the silicon wafer 10, and a back tunneling oxide layer 15, a back doped The polysilicon layer 16, the back silicon nitride layer 17 and the back electrode (not shown in the figure); wherein the thickness of the front tunneling oxide layer is 3.5 nm, and the thickness of the oxidation barrier layer is 1.1 nm; the thickness of the first front doped polysilicon layer is 45 nm; the thickness of the second front doped polysilicon layer is 124 nm; the thickness of the first aluminum oxide layer and the second aluminum oxide layer is 5 nm; the doping element of the first front doped polysilicon layer and the second front doped polysilicon layer is boron; the doping type of the first front doped polysilicon layer and the second front doped polysilicon layer is P type; the doping concentration of the second front doped polysilicon layer is 7×10 19 atom / cm 3 The doping concentration of the first front doped polysilicon layer is 6×10 18 atom / cm 3 ; The thickness of the back tunneling oxide layer is 1.5nm; The thickness of the back doped polysilicon layer is 60nm; The doping type of the back doped polysilicon layer is N-type, the doping element of the back doped polysilicon layer is phosphorus, and the doping concentration of the back doped polysilicon layer is 3×10 20 atom / cm 3 ; The thickness of the first front silicon nitride layer and the second silicon nitride layer is 75nm; the thickness of the back silicon nitride layer is 80nm.
[0145] Use a battery efficiency tester to test the electrical performance of photovoltaic cells.
[0146] Comparative Example 1
[0147] Step 1: Select an N-type single crystal silicon wafer with a resistivity of 0.5-2.5Ω·cm, a size of 182×182mm, and a thickness of 130μm, and use a KOH solution to texture the silicon wafer;
[0148] Step 2: Use a tubular thermal diffusion device to perform boron doping on the silicon wafer after the texturing treatment. The treatment time is 35 minutes, and then selective laser doping is performed. The surface BSG (borosilicate glass) is used as a local laser heavy doping source. Through the local thermal effect of the laser, the atoms in the BSG diffuse rapidly into the silicon wafer for a second time to form a local heavy doping area. The laser power is 43W, the laser frequency is 380kH, and the resistance value after selective laser doping is 86Ω;
[0149] Step 3: using a tubular annealing device, the silicon wafer obtained above was subjected to oxidation annealing treatment at 1050° C. for 2 h, the annealing gas atmosphere was oxygen, and the square resistance of the silicon wafer obtained after annealing was 243Ω;
[0150] Step 4: Use a cleaning machine to remove all BSG on the back and edge by floating in a 35% volume concentration HF solution (the back side contacts the acid solution); and polish the silicon wafer with a NaOH aqueous solution.
[0151] Step 5: Deposit a tunnel oxide layer and an intrinsic amorphous silicon layer on the back of the silicon wafer by LPCVD; then dope the intrinsic amorphous silicon layer with phosphorus to form N + Polysilicon layer; the temperature of phosphorus diffusion is 913℃;
[0152] Step 6: Use RCA to remove BPSG, BSG, PSG on the front side of the silicon wafer and remove the N+ layer on the front and edge of the phosphorus diffusion; RCA cleaning is divided into pre-pickling and post-pickling, the pre-pickling solution is a 4.0% HF aqueous solution with a cleaning time of 240 seconds, and the post-pickling solution is a 15% HF aqueous solution with a cleaning time of 100 seconds.
[0153] Step 7: Preparing an aluminum oxide layer on the front side of the silicon wafer;
[0154] Step 8: using PEVCD to prepare a front anti-reflection film layer and a back anti-reflection film layer on the front and back of the silicon wafer;
[0155] Step 9: Prepare a front electrode on the front side of the silicon wafer and prepare a back electrode on the back side of the silicon wafer.
[0156] Through the above steps, a Topcon photovoltaic cell is prepared, wherein the photovoltaic cell comprises a silicon wafer, the front side of the silicon wafer comprises a P+ emitter and a P++ emitter in the gate line region, an aluminum oxide layer, a front anti-reflection film layer and a front electrode; the back side of the silicon wafer comprises a back anti-reflection film layer and a back electrode; wherein the thickness of the tunneling oxide layer is 1.6 nm, the thickness of the doped polycrystalline silicon layer is 154 nm; the thickness of the aluminum oxide layer is 6.3 nm; the thickness of the front anti-reflection film layer is 78 nm; the thickness of the back anti-reflection film layer is 83 nm; the doping element of the doped polycrystalline silicon layer is phosphorus, and the doping concentration of the doped polycrystalline silicon layer is 3×10 20 atom / cm 3 .
[0157] Use a battery efficiency tester to test the electrical performance of photovoltaic cells.
[0158] The following table shows the electrical performance data of Examples 1-3 and Comparative Example 1. It can be seen from the table that, compared with Comparative Example 1, the efficiency value of the battery cell of Example 1 is increased by nearly 0.3%, which is a significant improvement in efficiency.
[0159] Table 1 Electrical performance data of Example 1 and Comparative Example 1
[0160] Eta / % Uoc / V Isc / A FF / % Example 1 26.09 0.7329 14.19 84.65 Comparative Example 1 25.81 0.7303 13.93 84.36
[0161] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other changes to the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0162] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A double-sided Topcon photovoltaic cell, characterized in that: It includes a silicon wafer, which includes a relative front side and back side, the front side of the silicon wafer is divided into a gate line area and a non-gate line area, the non-gate line area of the front side of the silicon wafer is sequentially provided with a front tunneling oxide layer, a first front doped polysilicon layer, a first aluminum oxide layer and a first front anti-reflection film layer; the gate line area of the front side of the silicon wafer is sequentially provided with a front tunneling oxide layer, a first front doped polysilicon layer, an oxidation barrier layer, a second front doped polysilicon layer, a second aluminum oxide layer and a second front anti-reflection film layer, the doping types of the first front doped polysilicon layer and the second front doped polysilicon layer are P type; the doping concentration of the second front doped polysilicon layer is greater than the doping concentration of the first front doped polysilicon layer; the back side of the silicon wafer is sequentially provided with a back tunneling oxide layer, a back doped polysilicon layer and a back anti-reflection film layer; the doping type of the back doped polysilicon layer is N type.
2. The photovoltaic cell according to claim 1, characterized in that The thickness of the front tunneling oxide layer is greater than the thickness of the oxidation barrier layer; and / or the thickness of the first front doped polysilicon layer is less than the thickness of the second front doped polysilicon layer; Preferably, The thickness of the front tunneling oxide layer is 1.5-5 nm, the thickness of the oxidation barrier layer is 1-2 nm, and / or the thickness of the first front doped polysilicon layer is 20-60 nm, and the thickness of the second front doped polysilicon layer is 50-200 nm.
3. The photovoltaic cell according to claim 1, characterized in that The thickness of the first aluminum oxide layer and the second aluminum oxide layer is 4-10nm; and / or, the thickness of the first front anti-reflection film layer and the second anti-reflection film layer is 65-90nm; and / or, the thickness of the back anti-reflection film layer is 70-100nm; and / or, the thickness of the back tunneling oxide layer is 1nm-5nm; and / or, the thickness of the back doped polysilicon layer is 80-160nm.
4. The photovoltaic cell according to claim 1, characterized in that The doping concentration of the first front doped polysilicon layer is 5-9×10 18 atom / cm 3 The doping concentration of the second front doped polysilicon layer is 2-6×10 19 atom / cm 3 .
5. The photovoltaic cell according to claim 1, characterized in that: The front side of the silicon wafer is composed of a tower base and a pyramid structure; Preferably, the height of the pyramid is 300-400 nm; the size of the pyramid base is 3-6 μm, and the reflectivity is 27-29%.
6. A method for preparing the photovoltaic cell of claims 1-5, characterized in that: The following steps are involved: Step 101: Select a silicon wafer and perform double-sided polishing on the silicon wafer; Step 102: depositing a back tunneling oxide layer and a back intrinsic amorphous silicon layer in sequence on the surface of the silicon wafer; Step 103: performing high-temperature phosphorus diffusion so that the back intrinsic amorphous silicon layer forms a back doped polysilicon layer; Step 104: removing the wrap-around plating on the front and side surfaces of the silicon wafer, and then performing surface treatment on the front surface of the silicon wafer; Step 105: depositing a front tunneling oxide layer, a front intrinsic amorphous silicon layer, an oxidation barrier layer and a front doped amorphous silicon layer in sequence on the surface of the silicon wafer; Step 106: forming a silicon oxide mask on the front side of the silicon wafer; the pattern of the mask is the same as the pattern of the gate lines on the front side of the silicon wafer; The silicon oxide film completely covers the gate line area; Step 107: etching the front side of the silicon wafer; For removing the oxidation barrier layer and the front doped amorphous silicon layer and the silicon oxide mask in the non-gate line area; Step 108: performing high-temperature boron diffusion so that the front intrinsic amorphous silicon layer and the front doped amorphous silicon layer are formed into a first front doped polysilicon layer and a second front doped polysilicon layer respectively; Step 109: removing the wrap-around plating on the front and back sides of the silicon wafer; Step 110: depositing an aluminum oxide layer on the front side of the silicon wafer; Step 111: depositing anti-reflection film layers on the front side and the back side of the silicon wafer respectively; Step 112: Prepare a front electrode and a back electrode on the gate line region on the front side of the silicon wafer and on the back side of the silicon wafer, respectively.
7. The method for preparing a photovoltaic cell according to claim 6, characterized in that: The thickness of the silicon oxide mask is 5-7 nm; and / or the width of the silicon oxide mask is 2-4 times the width of the gate line on the front side of the silicon wafer.
8. The method for preparing a photovoltaic cell according to claim 6, characterized in that: Step 104: removing the wrap-around plating on the front and side surfaces of the silicon wafer, and then performing a micro-alkali texturing treatment on the front surface of the silicon wafer, so that a surface consisting of a tower base and a pyramid structure is formed on the front surface of the silicon wafer; Preferably, a NaOH solution is used for slight alkaline texturing treatment; More preferably, the mass concentration of NaOH in the NaOH solution is 1-3%, and the mass concentration of the additive is 1%-3%; the additive NaOH is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter.
9. The method for preparing a photovoltaic cell according to claim 6, characterized in that: In step 107, the etching solution is a NaOH solution and an HF solution; the NaOH solution is used to remove the back intrinsic amorphous silicon layer and the front intrinsic amorphous silicon layer; Using HF solution to remove the silicon oxide mask and the oxide barrier layer; Preferably, the mass concentration of the NaOH solution is 1-3%; and the volume concentration of the HF solution is 15-50%.
10. A photovoltaic module, characterized in that: It includes the double-sided Topcon photovoltaic cell described in claims 1-5 or the double-sided Topcon photovoltaic cell prepared by the preparation method described in claims 6-9.