Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which not only exposes the top of a dummy gate, but also can generate a load effect that the top of a second dummy gate in a long channel element region is higher than the top of a first dummy gate in a short channel element region after chemical mechanical polishing is carried out on an interlayer dielectric layer. When the deposited metal gate material is subjected to chemical mechanical polishing, the first metal gate in the short channel element region can keep the height of the original dummy gate by utilizing the load effect generated by the previous polishing and the reverse complementary effect of the polishing; and the top of the second metal gate of the long-channel element region is not higher than the top of the first metal gate of the short-channel element region, so that the effect of reducing or eliminating the load effect between the metal gates of the short-channel element region and the long-channel element region is finally achieved, and the electrical property and the yield of the device are integrally improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] As device size continues to shrink to 45nm and below, in order to improve gate leakage current, the high-k metal gate (HKMG) process has become the mainstream advanced process to replace the traditional silicon dioxide gate dielectric and polysilicon gate (Poly Gate). The current mainstream HKMG process of 28nm and below technology nodes generally uses the last metal gate (i.e., Gate last) method to form a high-k metal gate, and will manufacture a long channel (LC) gate structure and a short channel (SC) gate structure on the same substrate.

[0003] However, the current metal gate last method will produce serious loading effect (i.e., gate height difference) between the long channel gate structure and the short channel gate structure, and the formed metal gate and the surrounding dielectric layer surface are prone to scratch defects, affecting the electrical properties and yield of the device. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can eliminate or improve the load effect between the metal gates of the short channel component region and the long channel component region, and ultimately improve the electrical properties and yield.

[0005] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0006] Forming a plurality of dummy gates on a substrate and depositing an interlayer dielectric layer on the substrate, wherein the dummy gate formed on the short channel component region of the substrate is a first dummy gate, and the dummy gate formed on the long channel component region of the substrate is a second dummy gate, the gate length of the first dummy gate is shorter than the gate length of the second dummy gate, and the interlayer dielectric layer buries each dummy gate;

[0007] Chemically mechanically polishing the interlayer dielectric layer until the top surface of each of the dummy gates is exposed and the top of the interlayer dielectric layer in the long channel component region is higher than the top of the interlayer dielectric layer in the short channel component region;

[0008] Selectively etching and removing each dummy gate to form a first gate groove at the position of the first dummy gate and a second gate groove at the position of the second dummy gate;

[0009] Depositing a metal gate material, wherein the metal gate material fills each of the first gate groove and the second gate groove and buries the interlayer dielectric layer therein;

[0010] The metal gate material is chemically mechanically polished until the top surface of the interlayer dielectric layer in the short channel component area is exposed to form a first metal gate filled in the first gate groove and a second metal gate filled in the second gate groove, and the top of the interlayer dielectric layer in the long channel component area is not higher than the top of the interlayer dielectric layer in the short channel component area.

[0011] Optionally, the step of forming a plurality of dummy gates on a substrate and burying an interlayer dielectric layer of the dummy gates includes:

[0012] Depositing a silicon dioxide layer, a polysilicon layer and a hard mask layer in sequence on the substrate;

[0013] Patterning the hard mask layer by photolithography combined with etching process;

[0014] Using the hard mask layer as a mask, sequentially etching the polysilicon layer and the silicon dioxide layer to form the dummy gate including the polysilicon layer and the silicon dioxide layer;

[0015] forming a sidewall spacer on the sidewall of the dummy gate;

[0016] An etch stop layer and the interlayer dielectric layer are sequentially deposited on the substrate, and the interlayer dielectric layer fills the space between the dummy gates.

[0017] Optionally, when each dummy gate is selectively etched and removed, only the polysilicon layer is removed, or the polysilicon layer and the silicon dioxide layer thereunder are removed together.

[0018] Optionally, after forming the sidewall spacer and before depositing the interlayer dielectric layer, source and drain regions are further formed in the substrate at both sides of the dummy gate.

[0019] Optionally, during the process of selectively etching and removing each dummy gate, the top of the interlayer dielectric layer in the long channel element region is kept higher than the top of the interlayer dielectric layer in the short channel region.

[0020] Optionally, after each dummy gate is removed by selective etching, the height difference between the top of the interlayer dielectric layer in the long channel element region and the top of the interlayer dielectric layer in the short channel region is reduced.

[0021] Optionally, after forming the first gate groove and the second gate groove and before depositing the metal gate material, a high-K dielectric layer having a dielectric constant K higher than that of silicon dioxide is first deposited in the first gate groove and the second gate groove.

[0022] Optionally, the polishing liquid used in chemical mechanical polishing of the metal gate material has a selectivity ratio of more than 50:1 for the metal gate material and the interlayer dielectric layer.

[0023] Optionally, after chemical mechanical polishing of the metal gate material, the depth of the gate groove in the short channel device region remains unchanged, and the top of the second metal gate is lower than the top of the first metal gate by a required height difference.

[0024] Optionally, the process time of chemical mechanical polishing the interlayer dielectric layer, the process time of selectively etching and removing each dummy gate, and the process time of chemical mechanical polishing the metal gate material are interrelated.

[0025] Optionally, the manufacturing method further includes increasing the process time of chemical mechanical polishing the interlayer dielectric layer, reducing the process time of selectively etching and removing each dummy gate and the process time of chemical mechanical polishing the metal gate material.

[0026] Compared with the prior art, the technical solution of the present invention not only exposes the top of the pseudo gate after chemical mechanical polishing (i.e., ILD0-CMP) of the interlayer dielectric layer, but also achieves a load effect in which the top of the second pseudo gate in the long channel component area is higher than the top of the first pseudo gate in the short channel component area. Furthermore, when chemical mechanical polishing (i.e., MG-CMP) is performed on the deposited metal gate material, the previous load effect and the reverse complementary effect of this polishing are utilized, so that not only the height of the original pseudo gate can be maintained for the first metal gate in the short channel component area, but also the top of the second metal gate in the long channel component area can be made not higher than the top of the first metal gate in the short channel component area, thereby ultimately achieving the effect of reducing or eliminating the load effect between the metal gates in the short channel component area and the long channel component area, thereby improving the electrical properties and yield of the device as a whole.

[0027] In addition, compared with the prior art, the technical solution of the present invention essentially controls the process time of chemical mechanical polishing of the interlayer dielectric layer to be relatively increased, and the process time of chemical mechanical polishing of the deposited metal gate material to be relatively shortened (i.e., ILD0-CMP requires more polishing, while MG-CMP requires less polishing). Therefore, the scratch defects on the surface of the metal gate and the interlayer dielectric layer can be significantly reduced, thereby further improving the electrical properties and yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0029] Figure 1The present invention is a schematic diagram of a device cross-sectional structure in an existing method for manufacturing a semiconductor device.

[0030] Figure 2 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Figure 3 yes Figure 2 A schematic diagram of a device cross-sectional structure in a method for manufacturing a semiconductor device is shown. DETAILED DESCRIPTION

[0032] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] Please refer to Figure 1 , the process of manufacturing semiconductor devices using the metal gate last process currently includes the following steps:

[0034] First, please refer to Figure 1 In (A), a plurality of dummy gates 101 are formed on the substrate 100 through a series of processes including thermal oxidation, polysilicon deposition, silicon nitride 102 deposition, silicon oxide 103 deposition, photolithography and etching. The gate length of the dummy gates 101 formed on the short channel component region SC of the substrate 100 is shorter, and the gate length of the dummy gates 101 formed on the long channel component region LC of the substrate 100 is longer.

[0035] Next, please refer to Figure 1 In (A), after forming the spacer 104 on the sidewall of the dummy gate 101 , an interlayer dielectric layer 105 ( ILD0 ) is deposited. The interlayer dielectric layer 105 can fill the space between the dummy gates 101 .

[0036] Afterwards, please refer to Figure 1 In (B), the interlayer dielectric layer 105 is subjected to chemical mechanical polishing (ILD0-CMP). The purpose of this polishing is to remove the silicon nitride 102 and silicon oxide 103 on the top surface of the pseudo gate 101, exposing the top surface of the pseudo gate 102. The overall height reduction of the film layer is mainly the stacking thickness of the silicon nitride 102, silicon oxide 103 and the interlayer dielectric layer 105 on the top surface of the pseudo gate 101. After the polishing, the load effect between the short channel component area SC and the long channel component area LC is not obvious, that is, the top height difference between the pseudo gate 101 in the short channel component area SC and the pseudo gate 101 in the long channel component area LC is not obvious. However, due to the small amount of polishing, there may be residual silicon nitride 102.

[0037] Then, please refer to Figure 1 In (C), the dummy gate 101 (Dummy polyremove, DPR) is etched away by a selective etching process to form a gate groove 106. The process time of this step is usually long, and a break through (BT) time (equivalent to the over-etching time) is usually added after the removal of the dummy gate 101 to eliminate the residual silicon nitride 102 and ensure that the dummy gate 101 is completely removed and the gate groove 106 is completely opened. However, since the process time of this step is too long, the interlayer dielectric layer 105 will be lost, and the loss amount of the long channel component region LC will be greater than that of the short channel component region SC, thereby forming a load effect between the short channel component region SC and the long channel component region LC. At this time, the top of the interlayer dielectric layer 105 of the long channel component region LC will be lower than the top of the interlayer dielectric layer 105 of the short channel component region SC by h1.

[0038] Next, please refer to Figure 1 In (D), high-K dielectric and metal gate material are deposited in sequence, and the metal gate material 107 can fill the gate groove 106 .

[0039] Afterwards, please refer to Figure 1 In (E), a polishing liquid having a polishing rate selection ratio of the metal gate material 107 to the interlayer dielectric layer 105 exceeding 50:1 is generally used to perform chemical mechanical polishing (metal gate CMP, MG-CMP) on the metal gate material 107 to remove the metal gate material 107 on the top surface of the interlayer dielectric layer 105, thereby forming a metal gate.

[0040] In the above process, in order to complete the height control of the metal gate, the MG-CMP process time will be relatively long. In this process, the grinding rate of the metal gate material 107 is very fast, and the grinding rate of the interlayer dielectric layer 105 is very slow, which will cause the metal gate material 107 and the interlayer dielectric layer 105 of the long channel component area LC to drop (i.e., loss) greater than that of the short channel component area SC. Combined with the load effect brought by the DPR-ET process, after the MG-CMP is completed, the load effect between the short channel component area SC and the long channel component area LC will be further aggravated. At this time, the top of the interlayer dielectric layer 105 of the long channel component area LC will be lower than the top of the interlayer dielectric layer 105 of the short channel component area SC by h2, and h2>h1. For example

[0041]

[0042] In addition, due to the long grinding time of MG-CMP, scratch defects and other problems are easily generated on the surface of the metal gate and the interlayer dielectric layer 105 around it, which directly affects the electrical performance and yield of the semiconductor device finally formed on the substrate 100.

[0043] The inventors believe that mastering the balance between ILD0-CMP and MG-CMP is crucial to the load effect between the short channel component region SC and the long channel component region LC of the final semiconductor device, as well as the gate control capability and defect performance.

[0044] Based on this, the present invention provides a method for manufacturing a semiconductor device. On the basis of the original process, the present invention fully combines the grinding characteristics of ILD0-CMP and MG-CMP, adopts the reverse complementary method of more grinding by ILD0-CMP and less grinding by MG-CMP, and combines the adjustment of DPR-ET process time. Finally, on the basis of keeping the formed metal gate height (final gate height) unchanged, the load effect between the short channel component region SC and the long channel component region LC is greatly reduced. In addition, because MG-CMP has less grinding, problems such as scratch defects can be significantly reduced, thereby improving the electrical properties and yield of the device as a whole.

[0045] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0046] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0047] S1, forming a plurality of dummy gates on a substrate and depositing an interlayer dielectric layer on the substrate, wherein the dummy gate formed on the short channel component region of the substrate is a first dummy gate, and the dummy gate formed on the long channel component region of the substrate is a second dummy gate, the gate length of the first dummy gate is shorter than the gate length of the second dummy gate, and the interlayer dielectric layer buries each dummy gate;

[0048] S2, chemically mechanically polishing the interlayer dielectric layer until the top surface of each of the dummy gates is exposed and the top of the interlayer dielectric layer in the long channel component region is higher than the top of the interlayer dielectric layer in the short channel component region;

[0049] S3, selectively etching and removing each dummy gate to form a first gate groove at the position of the first dummy gate and a second gate groove at the position of the second dummy gate;

[0050] S4, depositing a metal gate material, wherein the metal gate material fills each of the first gate groove and the second gate groove and buries the interlayer dielectric layer therein;

[0051] S5, chemically mechanically polishing the metal gate material until the top surface of the interlayer dielectric layer in the short channel component area is exposed to form a first metal gate filled in the first gate groove and a second metal gate filled in the second gate groove, and the top of the interlayer dielectric layer in the long channel component area is not higher than the top of the interlayer dielectric layer in the short channel component area.

[0052] Please refer to Figure 3 In step (A), the substrate 100 provided in step S1 may be any suitable semiconductor substrate material, such as a silicon substrate, a silicon carbide substrate, a gallium arsenide substrate, etc. The substrate 100 has a short channel component region SC and a long channel component region LC, wherein the short channel component region SC is used to form a metal gate with a shorter gate length (i.e., a shorter channel) (e.g., Figure 3 (E) 107a), the long channel element region LC is used to form a metal gate with a longer gate length (ie, a longer channel) (eg Figure 3 (E) 107b). The process of further forming the first dummy gate 101a, the second dummy gate 101b and the interlayer dielectric layer 105 on the substrate 100 in this step includes:

[0053] First, a silicon dioxide layer (not shown), a polysilicon layer (not marked) and a hard mask layer (not marked) are sequentially covered on the substrate 100, wherein the silicon dioxide layer serves as a pseudo-gate dielectric layer and can be formed by any suitable process such as thermal oxidation, the polysilicon layer and the hard mask layer can be formed by a suitable deposition process such as chemical vapor deposition, and the hard mask layer can be a single-layer film such as silicon oxide or silicon nitride, or a multilayer film structure formed by stacking a variety of different materials such as silicon oxide and silicon nitride. As an example, the hard mask layer includes silicon nitride 102 and silicon oxide 103 sequentially deposited on the polysilicon layer.

[0054] Next, the hard mask layer is patterned by photolithography combined with dry etching process, so as to form patterns of various dummy gates in the hard mask layer.

[0055] Then, using the patterned hard mask layer as a mask, the polysilicon layer and the silicon dioxide layer are etched in sequence through any suitable etching process to form a pseudo gate including the polysilicon layer and the silicon dioxide layer. Among them, the pseudo gate formed on the short channel component area SC is the first pseudo gate 101a, and the pseudo gate formed on the long channel component area LC is the second pseudo gate 101b. At this time, the tops of the second pseudo gate 101b and the second pseudo gate 101b are basically the same height, and the height is, for example, H (defined as the original height). There is almost no load effect between the two, but the gate length of the first pseudo gate 101a is shorter than the gate length of the second pseudo gate 101b. In addition, the spacing between the first pseudo gates 101a can be equal to, less than or greater than the spacing between the second pseudo gates 101b, and the present invention does not make specific limitations on this.

[0056] Afterwards, through the deposition and etching process of a spacer material (such as a single-layer film or a multi-layer film such as silicon oxide or silicon nitride), a spacer 104 is formed on the sidewalls of the first dummy gate 101a and the second dummy gate 101b.

[0057] Next, an etch stop layer (not shown, such as silicon oxide) and an interlayer dielectric layer (i.e., ILD0) 105 are sequentially deposited on the substrate 100. The interlayer dielectric layer 105 can fill the gap between the first dummy gates 101a and the gap between the second dummy gates 101b. The material of the interlayer dielectric layer 105 can be any suitable dielectric material, such as tetraethyl orthosilicate or a low-K dielectric with a dielectric constant K lower than that of silicon dioxide.

[0058] Optionally, after forming the sidewall 104 and before depositing the interlayer dielectric layer 105, corresponding source and drain regions can be further formed in the substrate on both sides of the first dummy gate 101a and the second dummy gate 101b by common processes in the field such as source and drain ion implantation or embedded source and drain processes.

[0059] Please refer to Figure 3In step (B), in step S2, a suitable polishing liquid and a soft polishing pad are used to perform chemical mechanical polishing (i.e., ILD0-CMP process) on the interlayer dielectric layer 105. The purpose of this polishing is to remove the silicon nitride 102 and silicon oxide 103 on the top surfaces of the first dummy gate 101a and the second dummy gate 101b, and to make the top of the remaining first dummy gate 101a lower than the top of the second dummy gate 101b.

[0060] In this embodiment, by maintaining Figure 1 On the basis of keeping other process conditions unchanged, only the grinding time of chemical mechanical grinding is relatively increased. Figure 1 In the original method shown, the grinding time of ILD0-CMP is defined as the first standard grinding time. In this embodiment, the grinding time of ILD0-CMP is controlled to be extended relative to the first standard grinding time. The advantages are: (1) after removing most of the silicon nitride 102 and silicon oxide 103 and grinding to expose the top surface of the dummy gate, it is necessary to continue grinding downward. Therefore, the silicon nitride 102 and silicon oxide 103 residues can be removed by grinding to fully expose the top of the first dummy gate 101a and the second dummy gate 101b; (2) when the top surface of the dummy gate is exposed and grinding downward continues, since the grinding liquid has a relatively small selectivity for the interlayer dielectric layer 105 and polysilicon, the polysilicon grinding rate of the long channel component area LC is lower than the polysilicon grinding rate of the short channel component area SC. Therefore, the top of the second dummy gate 101b of the long channel component area LC will eventually be higher than the top of the first dummy gate 101b of the short channel component area SC. Obviously, by controlling the grinding time, the top heights of the first pseudo gate 101a and the second pseudo gate 101b can be appropriately reduced as a whole (for example, the height of the first pseudo gate 101a is reduced from the original height H to H2, and the height of the second pseudo gate 101b is reduced from the original height H to H1). However, due to the difference in grinding rates between the long channel component region LC and the short channel component region SC, a load reaction that can be reversely complementary to the grinding in the subsequent step S5 can also be brought about. Even if the top of the second pseudo gate 101b of the long channel component region LC is higher than the top of the first pseudo gate 101a of the short channel component region SC and the height difference h0=H1-H2 reaches the required level, under the effect of grinding, the top of the interlayer dielectric layer 105 of the long channel component region LC is also higher than the top of the interlayer dielectric layer 105 of the short channel component region SC (the height difference is also h0); (3) Because ILD0-CMP uses a soft grinding pad when grinding the pseudo gates, even if the grinding time is relatively long, the top of the second pseudo gate 101b of the long channel component region LC is higher than the top of the first pseudo gate 101a of the short channel component region SC. Figure 1 The lengthening of the solution will not increase the number of scratch defects.

[0061] As an example, the polishing time of step S2 (ie, ILD0-CMP) of this embodiment is 15-30% longer than the polishing time of ILD0-CMP in the prior art (ie, the first standard polishing time mentioned above).

[0062] As another example, in step S2 (i.e., ILD0-CMP) of the present embodiment, by lengthening the grinding time of ILD0-CMP relative to the prior art (i.e., the first standard grinding time mentioned above), the top height of the first pseudo gate 101a of the short channel component region SC after grinding is further reduced by 5% to 15% (i.e., H2=85%*H~95%*H), or the top height of the second pseudo gate 101b of the long channel component region LC after grinding is further reduced by 5% to 15% (i.e., H1=85%*H~95%*H), or the height difference h0 between the top height of the second pseudo gate 101b of the long channel component region LC after grinding and the top height of the first pseudo gate 101a of the short channel component region SC reaches 5% to 15% of the original height H.

[0063] Please refer to Figure 3 (C) in step S3, the first dummy gate 101a and the second dummy gate 101b are removed by any suitable selective etching process (i.e., DPR-ET process) such as wet etching or dry etching followed by wet etching, thereby forming a first gate groove 106a at the position of the first dummy gate 101a and a second gate groove 106b at the position of the second dummy gate 101b.

[0064] Optionally, in step S3, when selectively etching and removing each dummy gate, only the polysilicon layer may be removed, or the polysilicon layer and the silicon dioxide layer thereunder may be removed together.

[0065] It should be understood that due to the relative Figure 1 The ILD0-CMP in the method shown increases (i.e., prolongs) the grinding time, and there is no risk of residual silicon nitride 102, so the step S3 can be relatively Figure 1The DPR-ET in the method shown shortens the process time, for example, by eliminating the BT time mentioned above, or even further shortening the process time on the basis of eliminating the BT time. The advantages of doing so are: (1) on the basis of ensuring that the first dummy gate 101a and the second dummy gate 101b are completely removed (i.e., the first gate groove 106a and the second gate groove 106b are completely opened), the consumption of the interlayer dielectric layer 105 is reduced, so that after DPR-ET, the top of the interlayer dielectric layer 105 of the long channel component region LC is still higher than the top of the interlayer dielectric layer 105 of the short channel component region SC; (2) over-etching is avoided to cause serious damage to the surface of the substrate 100 exposed at the bottom of the first gate groove 106a and the second gate groove 106b.

[0066] Furthermore, in this step S3, the DPR-ET process time can be reasonably controlled to produce controllable consumption of the interlayer dielectric layer 105, so that after the completion of this step S3, the top of the interlayer dielectric layer 105 of the long channel component region LC is kept higher than the top of the interlayer dielectric layer 105 of the short channel component region SC, and the height difference remains unchanged or decreases compared to the height difference h0 at the end of step S2.

[0067] Please refer to Figure 3 (D) in step S4, first, any suitable high-K dielectric material with a dielectric constant K greater than silicon dioxide can be covered on the inner surface of the first gate groove 106a and the second gate groove 106b by any suitable process such as atomic layer deposition or chemical vapor deposition to form a high-K dielectric layer (not shown); then, a metal gate material 107 can be deposited on the high-K dielectric layer and the exposed device surface by any suitable process such as sputtering, evaporation, chemical vapor deposition, etc., and the metal gate material 107 fills the remaining space in the first gate groove 106a and the second gate groove 106b. The metal gate material 107 may include a work function material and a metal electrode material required for the metal gate of a PMOS transistor or an NMOS transistor.

[0068] Please refer to Figure 3 In (E), in step S5, a polishing liquid having a selectivity of more than 50:1 to the metal gate material 107 and the interlayer dielectric layer 105 can be used to perform chemical mechanical polishing (i.e., MG-CMP process) on the metal gate material 107. The main purpose of step S5 is to remove the metal gate material 107 on the top of the interlayer dielectric layer 105, so that the remaining metal gate material 107 fills the first gate groove 106a to form the first metal gate 107a, fills the second gate groove 106b to form the second metal gate 107b, and provides a flat process platform for subsequent processes.

[0069] In this step S5, the polishing rate of the polishing liquid on the metal gate material 107 is very fast, and the polishing rate on the interlayer dielectric layer 105 and the side wall 104 is very slow. In addition, in the long channel component region LC, because the density of the interlayer dielectric layer 105 is low, the overall polishing rate is fast, and in the short channel component region SC, because the density of the interlayer dielectric layer 105 is large, the overall polishing rate is slow. Therefore, in this step S5, the polishing time can be controlled to maximize the use of the difference in polishing rates between the long channel component region LC and the short channel component region SC and the load effect formed in the previous step S3. The reverse complementary effect of the height difference h0 controls the grinding to stop at the top of the interlayer dielectric layer 105 of the short channel component region SC to avoid excessive loss of the interlayer dielectric layer 105, so that the top height of the second metal gate 107b of the long channel component region LC can be relatively reduced to not higher than the top height of the first metal gate 107a of the short channel component region SC on the basis of keeping the top height of the first metal gate 107a of the short channel component region SC equal to the depth of the first gate groove 106a at the end of step S3, and the height difference between the two is less than Figure 1 h2 shown in the figure, thereby improving the load effect between the short channel component region SC and the long channel component region LC, thereby improving the overall device performance and yield.

[0070] Optionally, in step S5, during the MG-CMP process, the depth of the first gate groove of the short channel element region SC is kept unchanged, and ultimately the top height of the second metal gate 107b is made lower than the top height of the first metal gate 107a, and the height difference between the two meets the device design requirements.

[0071] As an example, the height difference between the top height of the second metal gate 107b of the long channel device region LC and the top height of the first metal gate 107a of the short channel device region SC is ultimately controlled to be no more than within the range.

[0072] It should be understood that due to the Figure 1 In the scheme shown in FIG. 1 , the ILD0-CMP grinding time is appropriately prolonged in step S2 of this embodiment, and the depth of the first gate groove 106a is relatively reduced. Therefore, in step S5, the grinding time is relatively prolonged. Figure 1 According to the solution, on the basis of the same thickness of the deposited metal gate material 107, the grinding time of MG-CMP can be relatively reduced, which can not only achieve the required metal gate height, but also significantly improve the problems such as scratch defects caused by too long grinding time.

[0073] In summary, the grinding time in step S5, the etching time in step S3, and the grinding time in step S2 may be interrelated and mutually restricted. To increase the grinding time in step S2, it is necessary to relatively reduce the etching time in step S3 and the grinding time in step S5. Therefore, by utilizing the complementary combination effect of steps S2, S3 and S5, the load effect between the short channel component region SC and the long channel component region LC can be eliminated or improved, and scratch defects can be improved at the same time, thereby ultimately improving the electrical properties and yield of the device as a whole.

[0074] It is worth noting that the present invention does not specifically limit the grinding time in step S5, the etching time in step S3, and the grinding time in step S2. When applying the method of the present invention, those skilled in the art can make reasonable adjustments based on their original process to achieve the expected technical effect.

[0075] It should be understood that after the grinding of step S2 is completed, the specific size of the height difference h0 (i.e., the load effect) between the long channel component region LC and the short channel component region SC can be obtained by the following means: (1) directly measured by some film thickness measuring equipment and means; (2) the relationship between the height difference h0 and the grinding time is obtained in advance based on historical production data, and then the height difference h0 corresponding to the grinding time is obtained according to the relationship. Similarly, the specific size of the height difference (i.e., the load effect) between the long channel component region LC and the short channel component region SC after the completion of step S3, and the specific size of the height difference (i.e., the load effect) between the long channel component region LC and the short channel component region SC after the completion of step S5 can be obtained by the above means. The present invention does not specifically limit the specific size of the height difference (i.e., the load effect) formed in these steps.

[0076] To sum up, the technical solution of the present invention, after chemical mechanical polishing (i.e., ILD0-CMP) of the interlayer dielectric layer, not only the top of the pseudo gate is exposed, but also the load effect that the top of the second pseudo gate in the long channel component area is higher than the top of the first pseudo gate in the short channel component area can be achieved. Therefore, when the deposited metal gate material is subjected to chemical mechanical polishing (i.e., MG-CMP), the reverse complementary effect of this polishing and the previous load effect can be utilized, which can not only make the first metal gate in the short channel component area maintain the original pseudo gate height, but also make the top of the second metal gate in the long channel component area not higher than the top of the first metal gate in the short channel component area, thereby achieving the effect of reducing or eliminating the load effect between the metal gates in the short channel component area and the long channel component area, thereby improving the electrical properties and yield of the device as a whole.

[0077] In addition, compared with the existing technology, the process time for chemical mechanical polishing of the interlayer dielectric layer is relatively increased, while the process time for chemical mechanical polishing of the deposited metal gate material is relatively shortened (i.e., ILD0-CMP requires more polishing, while MG-CMP requires less polishing). Therefore, the scratch defects on the surface of the metal gate and the interlayer dielectric layer finally formed can be significantly reduced, thereby further improving the electrical properties and yield of the device as a whole.

[0078] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Forming a plurality of dummy gates on a substrate and depositing an interlayer dielectric layer on the substrate, wherein the dummy gate formed on the short channel component region of the substrate is a first dummy gate, and the dummy gate formed on the long channel component region of the substrate is a second dummy gate, the gate length of the first dummy gate is shorter than the gate length of the second dummy gate, and the interlayer dielectric layer buries each dummy gate; Chemically mechanically polishing the interlayer dielectric layer until the top surface of each of the dummy gates is exposed and the top of the interlayer dielectric layer in the long channel component region is higher than the top of the interlayer dielectric layer in the short channel component region; Selectively etching and removing each dummy gate to form a first gate groove at the position of the first dummy gate and a second gate groove at the position of the second dummy gate; Depositing a metal gate material, wherein the metal gate material fills each of the first gate groove and the second gate groove and buries the interlayer dielectric layer therein; The metal gate material is chemically mechanically polished until the top surface of the interlayer dielectric layer in the short channel component area is exposed to form a first metal gate filled in the first gate groove and a second metal gate filled in the second gate groove, and the top of the interlayer dielectric layer in the long channel component area is not higher than the top of the interlayer dielectric layer in the short channel component area.

2. The manufacturing method according to claim 1, characterized in that The steps of forming a plurality of dummy gates on a substrate and burying an interlayer dielectric layer of the dummy gates include: sequentially covering the substrate with a silicon dioxide layer, a polysilicon layer and a hard mask layer; Patterning the hard mask layer by photolithography combined with etching process; Using the hard mask layer as a mask, sequentially etching the polysilicon layer and the silicon dioxide layer to form the dummy gate including the polysilicon layer and the silicon dioxide layer; forming a sidewall spacer on the sidewall of the dummy gate; An etch stop layer and the interlayer dielectric layer are sequentially deposited on the substrate, and the interlayer dielectric layer fills the space between the dummy gates.

3. The manufacturing method according to claim 2, characterized in that: After forming the sidewall spacer and before depositing the interlayer dielectric layer, source and drain regions are formed in the substrate at both sides of the dummy gate.

4. The manufacturing method according to claim 1, characterized in that: During the process of selectively etching and removing each dummy gate, the top of the interlayer dielectric layer in the long channel element region is kept higher than the top of the interlayer dielectric layer in the short channel region.

5. The manufacturing method according to claim 1, characterized in that: After each dummy gate is removed by selective etching, the height difference between the top of the interlayer dielectric layer in the long channel element region and the top of the interlayer dielectric layer in the short channel region is reduced.

6. The manufacturing method according to claim 1, characterized in that: After forming the first gate groove and the second gate groove and before depositing the metal gate material, a high-K dielectric layer having a dielectric constant K higher than that of silicon dioxide is first deposited in the first gate groove and the second gate groove.

7. The manufacturing method according to claim 1, characterized in that: The polishing liquid used in chemical mechanical polishing of the metal gate material has a selectivity ratio of more than 50:1 for the metal gate material and the interlayer dielectric layer.

8. The manufacturing method according to any one of claims 1 to 7, characterized in that: After chemical mechanical polishing of the metal gate material, the depth of the first gate groove in the short channel device region remains unchanged, and the top of the second metal gate is lower than the top of the first metal gate by a required height difference.

9. The manufacturing method according to claim 1, characterized in that: The process time of chemical mechanical polishing the interlayer dielectric layer, the process time of selectively etching and removing each dummy gate, and the process time of chemical mechanical polishing the metal gate material are interrelated.

10. The manufacturing method according to claim 9, characterized in that: It also includes increasing the process time of chemical mechanical grinding of the interlayer dielectric layer, reducing the process time of selectively etching and removing each dummy gate and the process time of chemical mechanical grinding of the metal gate material.

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