Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; a circuit pattern layer disposed on the insulating layer and including a pad; and a protective layer disposed on the insulating layer and including an opening vertically overlapping the pad, in which: the pad includes a groove recessed from an upper surface of the pad toward a lower surface of the pad; the protective layer includes a first region including an opening and vertically overlapping the pad and a second region other than the first region; the pad includes a first portion including a recess and a second portion connected to the first portion and not including the recess; the first portion of the pad includes a first sub-portion vertically overlapping the opening of the protective layer and a second sub-portion vertically overlapping the lower surface of the first region of the protective layer; and a width of the second sub-portion of the pad is greater than a width of the second portion of the pad.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] The high performance of electric / electronic products is advancing, and therefore, technologies for attaching a greater number of packages to a substrate of a limited size are being proposed and studied.

[0003] A typical semiconductor package has a structure in which a plurality of chips are arranged. In addition, the size of the semiconductor package is increasing due to the high specifications of products to which the semiconductor package is applied and the adoption of a plurality of chips such as HBM (High Bandwidth Memory). Therefore, the semiconductor package includes an interposer for connecting the plurality of chips.

[0004] In addition, semiconductor packages applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers require high performance and high reliability in line with the trend toward high integration. Here, high performance may include conditions such as high-speed transmission of signals, integration of semiconductor packages, and high allowable current of transmittable signals.

[0005] At this time, for miniaturization and integration, the size of the pad of the semiconductor package is being reduced. The pad may be a mounting pad connected to the chip, and may be a bump pad connected to various substrates. Here, the various substrates may include additional packages such as a memory substrate, an interposer connected between the chip and the circuit board, and a mainboard of an electronic device to which the semiconductor package is applied.

[0006] At this time, when the size of the pad is reduced, the integration of the semiconductor package can be improved. However, according to the conventional semiconductor package, the contact area between the pad and the solder bump is reduced in response to the reduction in the size of the pad, and therefore, there is a problem that the adhesion between the pad and the solder bump is reduced. As a result, in the manufacturing process or use environment of the semiconductor package, there is a problem of physical reliability and electrical reliability in which the solder bump is separated from the pad.

[0007] (Patent Document 1) KR 10-2152865 B Summary of the invention

[0008] Technical issues

[0009] The embodiment provides a circuit board having a novel structure and a semiconductor package including the circuit board.

[0010] In addition, the embodiment provides a circuit board having improved integration and a semiconductor package including the same.

[0011] In addition, the embodiment provides a circuit board capable of improving adhesion between a pad and a connection member and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board capable of increasing a contact area between a pad and a connection member, and a semiconductor package including the same.

[0013] Technical problems to be solved by the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the proposed embodiments belong from the following description.

[0014] Technical Solutions

[0015] According to an embodiment, a circuit board includes an insulating layer; a circuit pattern layer, which is arranged on the insulating layer and includes a pad; and a protective layer, which is arranged on the insulating layer and includes an opening that vertically overlaps the pad, wherein the pad includes a groove that is recessed from the upper surface of the pad toward the lower surface of the pad, wherein the protective layer includes a first area that includes the opening and vertically overlaps the pad and a second area that excludes the first area, wherein the pad includes a first portion that includes the groove; and a second portion that is connected to the first portion and does not have the groove, wherein the first portion of the pad includes a first sub-portion of the opening that vertically overlaps the protective layer and a second sub-portion of the lower surface of the first area that vertically overlaps the protective layer, and wherein a width of the second sub-portion of the pad is greater than a width of the second portion of the pad.

[0016] In addition, an upper surface of the second sub-portion of the pad is spaced apart from a lower surface of the first region of the protective layer, and an upper surface of the second portion of the pad is in direct contact with a lower surface of the first region of the protective layer.

[0017] In addition, the upper surface of the first portion of the pad has a concavo-convex shape.

[0018] In addition, the width of the second sub-portion of the pad satisfies a range of 2 to 50 times the width of the second portion of the pad.

[0019] In addition, a vertical distance from the lower surface of the first region of the protective layer to the upper surface of the first portion of the pad satisfies a range of 5% to 55% of a vertical distance from the lower surface of the first region of the protective layer to the lower surface of the pad.

[0020] In addition, the pad includes a side surface, and at least a portion of an upper surface of the first portion of the pad is connected to the side surface of the pad.

[0021] In addition, the groove of the pad is connected to the side surface of the pad.

[0022] In addition, the pad includes a first side surface and a second side surface opposite to the first side surface, and a width of a second sub-portion of the pad adjacent to the first side surface of the pad is different from a width of a second sub-portion of the pad adjacent to the second side surface of the pad.

[0023] In addition, the groove includes a first part provided on an upper surface of the pad; and a second part provided on a side surface of the pad and connected to the first part.

[0024] In addition, a side surface of the pad having the second member is spaced apart from the protective layer.

[0025] In addition, the opening of the protective layer includes a region whose width changes in the vertical direction.

[0026] In addition, the circuit pattern layer further includes a trace that is disposed on the insulating layer, and an upper surface of the trace is positioned higher than an upper surface of the first portion of the pad.

[0027] At the same time, according to an embodiment, a semiconductor package includes an insulating layer; a pad, which is arranged on the insulating layer and has a groove on the upper surface; a protective layer, which is arranged on the insulating layer and includes an opening that vertically overlaps the pad; and a connecting member, which is arranged to fill the opening of the protective layer and the groove of the pad, wherein an interface provided between the connecting member and the pad has a concave-convex shape, the protective layer includes a first area including the opening and vertically overlapping the pad and a second area excluding the first area, and the pad includes a first portion having the groove; and a second portion connected to the first portion and not having the groove, the first portion of the pad includes a first sub-portion of the opening of the protective layer vertically overlapping the protective layer and a second sub-portion of the lower surface of the first area vertically overlapping the protective layer, and the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.

[0028] In addition, the connection member includes a portion that is disposed in the groove and directly contacts a lower surface of the first region of the protection layer and an upper surface of the second sub-portion of the pad.

[0029] In addition, the groove is connected to at least a portion of the side surface of the pad, and the connection member includes a portion disposed in the groove connected to the side surface of the pad and in direct contact with the inner surface of the second region of the protective layer.

[0030] In addition, the groove includes a first component provided on the upper surface of the pad and a second component connected to the first component and provided on the side surface of the pad, and the connecting member includes portions that are arranged in the first component and the second component of the groove and are in contact with the lower surface of the first area of ​​the protective layer, the inner surface of the second area of ​​the protective layer, the upper surface of the first part of the pad, and the side surface of the pad, respectively.

[0031] In addition, the semiconductor package further includes a semiconductor device disposed on the connection member.

[0032] In addition, the semiconductor package further includes a substrate disposed on the connection member.

[0033] In addition, the substrate includes at least one of an interposer connected to a semiconductor device, a memory substrate on which a memory chip is disposed, a main board of an electronic device; and a bridge substrate connected between a plurality of semiconductor devices.

[0034] Beneficial Effects

[0035] The circuit board and the semiconductor package of the embodiment can improve the adhesion and bonding strength between the pad and the connection member. Therefore, the embodiment can solve the problem of cracks occurring in the connection member and thus improve the physical reliability and electrical reliability of the connection member.

[0036] To this end, the circuit board of the embodiment includes an insulating layer, a pad and a protective layer. The protective layer includes an opening that vertically overlaps at least a portion of the pad. At this time, the protective layer includes a first area adjacent to the opening and vertically overlapping the pad and a second area excluding the first area. In addition, the pad has a groove. The groove can be a recessed portion that is recessed from the upper surface of the pad toward the lower surface. The pad includes an upper surface having a concave-convex shape corresponding to the groove. At this time, the pad includes a first part including the groove and a second part that does not include the groove. At this time, the first part of the pad includes a first sub-portion of the opening of the vertically overlapping protective layer and a second sub-portion of the first area of ​​the vertically overlapping protective layer. At the same time, a connecting member is arranged on the pad. At this time, the connecting member is arranged to fill the groove of the pad. Therefore, the connecting member is not only arranged on the first sub-portion of the pad, but also arranged on the second sub-portion. In addition, a part of the connecting member arranged on the second sub-portion can have a structure located between the lower surface of the first area of ​​the protective layer and the upper surface of the second sub-portion of the pad.

[0037] Therefore, the connecting member of the embodiment includes a first component disposed on the second sub-portion. In addition, the first component of the connecting member can be used as an anchor, which improves adhesion and bonding strength with the pad. Therefore, the embodiment can solve the reliability problem of the connection member being separated from the pad. Therefore, the embodiment can improve the overall product reliability of the circuit board and the semiconductor package.

[0038] In addition, the embodiment can improve the contact area between the pad and the connecting member by the anchoring structure of the connecting member. Therefore, the embodiment does not need to increase the size of the pad to improve the contact area. Therefore, the embodiment can reduce the size of the pad, thereby improving the circuit integration. In addition, the embodiment can reduce the overall volume of the circuit board and the semiconductor package.

[0039] Meanwhile, the groove provided in the pad of the embodiment can include a plurality of parts. For example, the groove can include a first part provided on the upper surface of the pad and a second part connected to the first part and provided on the side surface of the pad.

[0040] Therefore, at least a portion of the side surface of the pad cannot contact the protective layer through the second part of the groove. In addition, the connecting member can be arranged in the second part of the groove of the pad. The connecting member can be arranged in the first part of the groove and can contact the lower surface of the first area of ​​the protective layer and the upper surface of the pad. In addition, the connecting member can be positioned in the second part of the groove to contact the inner surface of the second area of ​​the protective layer and the side surface of the pad. Therefore, the embodiment can further increase the contact area between the pad and the connecting member. Therefore, the embodiment can further improve the adhesion and bonding strength between the pad and the connecting member. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1a is a cross-sectional view showing a circuit board according to a comparative example.

[0042] Figure 1b It is shown Figure 1a A scanning electron microscope view of the actual product.

[0043] Figure 2a 2 is a view showing a semiconductor package according to a first embodiment.

[0044] Figure 2b is a view showing a semiconductor package according to a second embodiment.

[0045] Figure 2c is a view showing a semiconductor package according to a third embodiment.

[0046] Figure 2d is a view showing a semiconductor package according to a fourth embodiment.

[0047] Figure 2e 2 is a view showing a semiconductor package according to a fifth embodiment.

[0048] Figure 2f is a view showing a semiconductor package according to a sixth embodiment.

[0049] Figure 3is a cross-sectional view showing a circuit board according to an embodiment.

[0050] Figure 4a is an enlarged cross-sectional view of a portion of the circuit board according to the first embodiment.

[0051] Figure 4b yes Figure 4a A plan view of a circuit board.

[0052] Figure 4c is shown in which the connecting member is arranged Figure 4a A cross-sectional view of the state of the circuit board.

[0053] Figure 5a It is shown Figure 4a FIG. 1 is a view of a first modified example of a circuit board.

[0054] Figure 5b It is shown Figure 4a FIG. 1 is a view of a second modified example of a circuit board.

[0055] Figure 6 is a cross-sectional view showing a circuit board of the second embodiment.

[0056] Figure 7 is a cross-sectional view showing a circuit board of the third embodiment.

[0057] Figure 8a is a diagram showing a circuit board according to a fourth embodiment.

[0058] Figure 8b is shown in which the connecting member is arranged Figure 8a A cross-sectional view of the state of the circuit board.

[0059] Fig. 9 is a cross-sectional view showing a circuit board according to a fifth embodiment.

[0060] Figures 10a to 10d It is used to explain in the order of process. Figure 3 A cross-sectional view of a method for manufacturing a circuit board as illustrated in FIG. DETAILED DESCRIPTION

[0061] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0062] However, the spirit and scope of the present disclosure are not limited to the described part of the embodiments and can be implemented in various other forms, and one or more elements in the embodiments can be selectively combined and rearranged within the spirit and scope of the present disclosure.

[0063] In addition, unless otherwise clearly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present disclosure may be understood to have the same meaning as that generally understood by a person of ordinary skill in the art to which the present disclosure belongs, and the terms defined in common dictionaries may be interpreted as having a meaning consistent with that in the context of the relevant field. In addition, the terms used in the embodiments of the present disclosure are only used to describe the embodiments and are not used to limit the present disclosure.

[0064] In the present specification, unless explicitly stated in a phrase, a singular form may also include a plural form, and may include at least one of all possible combinations of A, B, and C when described in “at least one (or more) of A (and), B, and C”. In addition, when describing elements of an embodiment of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0065] These terms are only used to distinguish an element from other elements and are not limited to the nature, order or sequence of the elements. In addition, when an element is described as being "connected", "coupled" or "in contact with" another element, it can include not only when the element is directly "connected", "coupled" or "in contact with" the other element, but also when the element is "connected", "coupled" or "in contact with" another element between the element and the other element.

[0066] In addition, when described as being formed or disposed “on (above)” or “below (below)” of each element, the “on (above)” or “below (below)” may include not only when two elements are directly connected but also when one or more other elements are formed or disposed between the two elements. Furthermore, when expressed as “on (above)” or “below (below)”, it may include not only an upper direction but also a lower direction based on one element.

[0067] -Comparative example (Structure of the prior art and problems of the prior art)-

[0068] Figure 1a is a cross-sectional view showing a circuit board according to a comparative example, and Figure 1b It is shown Figure 1a A scanning electron microscope view of the actual product.

[0069] refer to Figure 1a , the circuit board of the comparative example includes an insulating layer 10 , a pad 20 , a protective layer 30 , and a connecting member 40 .

[0070] The circuit board of the comparative example includes a pad 20 provided on the insulating layer 10. The pad 20 is one of a first pad on which a chip is mounted and a second pad coupled to an external substrate.

[0071] In addition, the protective layer 30 includes an opening vertically overlapping the pad 20, and is disposed on the insulating layer 10. The protective layer 30 includes an opening formed to correspond to a region where the connection member 40 is disposed.

[0072] The connection member 40 is disposed on the pad 20. Specifically, the connection member 40 is disposed on the pad 20 vertically overlapping the opening of the protection layer 30.

[0073] At this time, the contact area between the connection member 40 of the comparative example and the pad 20 corresponds to the area of ​​the opening of the protective layer 30 .

[0074] Specifically, the contact area between the connection member 40 and the pad 20 of the comparative example is determined by the area where the opening of the protection layer 30 vertically overlaps with the pad 20. The contact area between the connection member 40 and the pad 20 is equal to the area where the opening of the protection layer 30 vertically overlaps with the pad 20.

[0075] Therefore, the comparative example increases the area of ​​the opening of the protective layer 30 to increase the contact area between the connection member 40 and the pad 20. However, when the area of ​​the opening of the protective layer 30 increases, the size of the pad 20 must also be increased accordingly. In addition, when the size of the pad 20 increases, there is a problem of reduced circuit integration.

[0076] Meanwhile, in the comparative example, the size of the pad 20 is reduced to improve circuit integration, and the opening area of ​​the protective layer 30 is also reduced accordingly.

[0077] However, when the area of ​​the opening of the protective layer 30 is reduced, the contact area between the connecting member 40 and the pad 20 is also reduced accordingly. In addition, when the contact area between the connecting member 40 and the pad 20 is reduced, problems with the physical reliability or electrical reliability of the connecting member 40 may occur in the manufacturing environment of the semiconductor package or the use environment of the semiconductor package.

[0078] Specifically, refer to Figure 1b When the contact area between the connection member 40 and the pad 20 is reduced, there is a problem that cracks occur at the interface CR between the connection member 40 and the pad 20. In addition, the connection member 40 may be separated from the pad 20 through the crack, and therefore, physical reliability and electrical reliability problems of the semiconductor package may occur.

[0079] For example, thermal stress may occur in a use environment or a manufacturing environment of a semiconductor package, and the thermal stress may be concentrated on the interface between the connection member 40 and the pad 20. In addition, when the thermal stress is concentrated on the interface, the crack occurrence rate at the interface may increase.

[0080] -Electronic Devices-

[0081] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. In addition, various semiconductor devices can be installed in the semiconductor package.

[0082] Semiconductor devices may include active devices and / or passive devices and have various functions. Active devices may be semiconductor devices in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into a single chip. Semiconductor devices may be logic chips, memory chips, and the like. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may be an application processor (AP) semiconductor device including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application specific IC (ASIC), and the like, or a chipset including a specific combination of those listed so far.

[0083] The memory chip may be a stack memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (eg, DRAM), a nonvolatile memory (eg, ROM), or a flash memory.

[0084] Product groups of semiconductor packages to which the embodiments are applied include CSP (Chip Scale Package), FC-CSP (Flip Chip - Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package on Package), and SIP (System in Package), but are not limited thereto.

[0085] In addition, the electronic device may include a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a display, a tablet, a laptop, a netbook, a television, a video game, a smart watch, a car, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0086] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board described later.

[0087] Figure 2a 2 is a view showing a semiconductor package according to a first embodiment.

[0088] refer to Figure 2a , the semiconductor package of the first embodiment includes a first substrate 100 .

[0089] The first substrate 100 may mean a package substrate.

[0090] For example, the first substrate 100 may provide a space to which at least one external substrate is coupled. For example, the first substrate 100 may provide a space to which a main board included in the electronic device is coupled.

[0091] As described below, the first substrate 100 may include at least one insulating layer, a circuit pattern layer disposed on the at least one insulating layer, a through electrode penetrating the at least one insulating layer, and a protection layer protecting the insulating layer and the circuit pattern layer.

[0092] The first substrate 100 may include a plurality of pads. Here, the plurality of pads may mean a portion of a circuit pattern layer disposed on the outermost layer of the first substrate 100. For example, a pad may mean a portion of a circuit pattern layer disposed on the uppermost side of the first substrate 100. For example, a pad may mean a portion of a circuit pattern layer disposed on the lowermost side of the first substrate 100. In addition, the protective layer may include an opening that exposes a surface (e.g., an upper surface or a lower surface) of the pad.

[0093] Meanwhile, the semiconductor package may include a plurality of connection members.

[0094] For example, the first substrate 100 may include a plurality of pads, and a plurality of connection members may be disposed on the plurality of pads, respectively.

[0095] Specifically, the first substrate 100 may include a plurality of first pads. In addition, the semiconductor package may include a first connection member 110 disposed on the plurality of first pads.

[0096] In addition, the first substrate 100 may include a plurality of second pads. In addition, the semiconductor package may include a second connection member 140 disposed on the plurality of second pads.

[0097] In addition, the first substrate 100 may include a plurality of third pads. In addition, the semiconductor package may include a third connection member 160 disposed on the plurality of third pads.

[0098] At this time, the first pad may be disposed on the upper surface of the first substrate 100. In addition, the second and third pads may be disposed on the lower surface of the first substrate 100.

[0099] Meanwhile, a semiconductor package may include a plurality of semiconductor devices.

[0100] For example, the semiconductor package may include a first semiconductor device 120 disposed on a first connection member 110. At this time, the first pads of the first substrate 100 may be divided into a plurality of groups. In addition, the first connection member 110 may be disposed on each of the first pads of the plurality of groups. In addition, the first semiconductor device 120 may be mounted on each of the first pads of the plurality of groups. Therefore, the first semiconductor device 120 can be mounted on the upper side of the first substrate 100 at predetermined intervals from each other. At this time, the first semiconductor device 120 may refer to a semiconductor device mounted on the upper side of the first substrate 100. In addition, a plurality of first semiconductor devices can be disposed on the upper side of the first substrate 100 at predetermined intervals from each other.

[0101] In addition, the semiconductor package may include a second semiconductor device 140 disposed under the second connection member 140. The second semiconductor device 140 may refer to a semiconductor device mounted on the lower side of the first substrate 100 among the semiconductor devices included in the semiconductor package. In addition, a plurality of second semiconductor devices can be disposed on the lower side of the first substrate 100 at predetermined intervals from each other.

[0102] At this time, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a logic chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an application processor chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an analog-to-digital converter or an ASIC (Application Specific IC). For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a memory chip. The memory chip may be a stack memory such as HBM. For example, the memory chip may include a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.

[0103] In addition, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include at least one of a driver IC chip, a diode chip, a power IC chip, a touch sensor IC chip, an MLCC (Multilayer Ceramic Capacitor) chip, a BGA (Ball Grid Array) chip, and a chip capacitor.

[0104] In addition, the semiconductor package may include a third connection member 160. The third connection member 160 may be positioned below the third pad of the first substrate 100. The third connection member 160 may be connected between the first substrate 100 and the main board of the electronic device. The third connection member 160 may have a larger diameter than the first connection member 110 and the second connection member 140. For example, the diameter of the third connection member 160 may satisfy a range of 10 to 200 times the diameter of at least one of the first connection member 110 and the second connection member 140. For example, the diameter of the third connection member 160 may satisfy a range of 20 to 180 times the diameter of at least one of the first connection member 110 and the second connection member 140. For example, the diameter of the third connection member 160 may satisfy a range of 40 to 150 times the diameter of at least one of the first connection member 110 and the second connection member 140. That is, the third connection member 160 is connected to the main board of the electronic device and may have a larger diameter than the other connection members to correspond to the width of the pad part of the main board. In addition, the first connection members 110 and the second connection members 140 are connected to the semiconductor device and may have a smaller diameter than the third connection member 160 to correspond to terminals of the semiconductor device.

[0105] The semiconductor package may include a molding layer.

[0106] For example, the semiconductor package may include a first molding layer 130 disposed on the first substrate 100. The first molding layer 130 may mold components disposed on the outermost layer of the first substrate 100. For example, the first molding layer 130 can mold the surface of the protective layer, the surface of the circuit pattern layer, and the surface of the insulating layer disposed on the uppermost side of the first substrate 100. In addition, the first molding layer 130 can mold the first connection member 110 and the first semiconductor device 120 disposed on the first substrate 100. At this time, the semiconductor package can further include an underfill (not shown) surrounding the first connection member 110 and the first semiconductor device 120. In addition, when the semiconductor package includes an underfill, the first molding layer 130 can mold the periphery of the underfill.

[0107] In addition, the semiconductor package may include a second mold layer 170 disposed under the first substrate 100. The second mold layer 170 may mold a surface of a protection layer, a surface of a circuit pattern layer, and a surface of an insulating layer disposed on a lowermost side of the first substrate 100. In addition, the second mold layer 170 may mold a second connection member 140 and a second semiconductor device 140 disposed under the first substrate 100. In addition, the second mold layer 170 may mold a third connection member 160.

[0108] At this time, the second mold layer 170 may expose at least a portion of the lower surface of the second semiconductor device 140. For example, the lower surface of the second mold layer 170 may be positioned not lower than the lower surface of the second semiconductor device 140. For example, the lower surface of the second mold layer 170 may be positioned on the same plane as the lower surface of the second semiconductor device 140.

[0109] In addition, the second mold layer 170 may be positioned not lower than the lower surface of the third connection member 160. For example, the lower surface of the second mold layer 170 may be positioned on the same plane as the lower surface of the third connection member 160 or on a plane higher than the lower surface of the third connection member 160. Therefore, the lower surface of the third connection member 160 may not be covered by the second mold layer 170. In addition, at least a portion of the third connection member 160 may protrude downward from the second mold layer 170.

[0110] The first mold layer 130 and the second mold layer 170 may be EMC (epoxy mold compound), but are not limited thereto. The first mold layer 130 and the second mold layer 170 may have a low dielectric constant. For example, the dielectric constant (Dk) of the first mold layer 130 and the second mold layer 170 may be 0.2 to 10. For example, the dielectric constant (Dk) of the first mold layer 130 and the second mold layer 170 may be 0.5 to 8. For example, the dielectric constant (Dk) of the first mold layer 130 and the second mold layer 170 may be 0.8 to 5. Therefore, in this embodiment, by making the first mold layer 130 and the second mold layer 170 have a low dielectric constant, the heat dissipation characteristics of the heat generated from the first semiconductor device 120 and the second semiconductor device 140 can be improved. The semiconductor package of the first embodiment may have a double-sided molding structure as described above.

[0111] That is, the semiconductor package of the first embodiment may have a structure in which at least one first semiconductor device 120 and a second semiconductor device 140 are mounted on the upper and lower sides of the first substrate 100 , respectively.

[0112] Figure 2b is a view showing a semiconductor package according to a second embodiment.

[0113] refer to Figure 2b , the semiconductor package according to the second embodiment can be used with Figure 1a The semiconductor package of the first embodiment is different in that the semiconductor package has a single-sided mold structure.

[0114] For example, the semiconductor package of the second embodiment may include a first substrate 100 , a first connection member 110 , a first semiconductor device 120 , a first mold layer 130 , and a third connection member 160 .

[0115] In addition, the semiconductor package of the second embodiment may have a structure in which the semiconductor device is mounted only on the upper side of the first substrate 100. Therefore, the mold layer of the semiconductor package of the second embodiment may be provided only on the upper side of the first substrate 100.

[0116] Figure 2c is a view showing a semiconductor package according to a third embodiment.

[0117] refer to Figure 2c , according to the third embodiment of the semiconductor package and Figure 1b The semiconductor package of the second embodiment is different in that the semiconductor package further includes an additional package.

[0118] The semiconductor package of the third embodiment may further include a fourth pad disposed on the upper side of the first substrate 100. That is, the circuit pattern layer is disposed on the upper surface of the first substrate 100. In addition, a portion of the circuit pattern layer may be used as a first pad on which the first semiconductor device 120 is mounted, and another portion may be used as a fourth pad.

[0119] The semiconductor package of the third embodiment may further include a fourth connection member 180 disposed on the fourth pad.

[0120] The upper surface of the fourth connection member 180 may not be covered with the first mold layer 130 .

[0121] The semiconductor package of the third embodiment may further include a second substrate 200 disposed on the fourth connection member 180. The second substrate 200 may be a memory substrate, but is not limited thereto.

[0122] The semiconductor package of the third embodiment may include a third semiconductor device 210 mounted on a second substrate 200. The third semiconductor device 210 may be a memory chip, but is not limited thereto.

[0123] In addition, the semiconductor package of the third embodiment may further include a connection member 220 connecting the second substrate 200 and the third semiconductor device 210. That is, Figure 2c The semiconductor package of the third embodiment may have a package-on-package structure.

[0124] Figure 2d is a view showing a semiconductor package according to a fourth embodiment.

[0125] refer to Figure 2d , according to the fourth embodiment of the semiconductor package and Figure 2cThe semiconductor package of the third embodiment is different in that the first semiconductor device 120 includes a plurality of logic chips and an additional third substrate 190 is disposed on the first substrate 100 .

[0126] For example, a plurality of logic chips may be disposed on the first substrate 100. For example, a plurality of logic chips of the same type may be disposed on the first substrate 100, or, alternatively, a plurality of logic chips of different types may be disposed.

[0127] At this time, a connection member may be disposed on the first substrate 100 to connect the plurality of first semiconductor devices 120. The connection member may mean a third substrate 190.

[0128] The third substrate 190 may be a bridge substrate. The third substrate 190 may include a redistribution layer. The third substrate 190 is disposed on the first substrate 100. In addition, the third substrate 190 is capable of electrically connecting a plurality of first semiconductor devices 120 corresponding to a plurality of logic chips. At this time, although the drawings show that the third substrate 190 is embedded in the first substrate 100, the embodiment is not limited thereto. For example, the third substrate 190 may be disposed on the first substrate 100.

[0129] The third substrate 190 may be a silicon bridge substrate. Alternatively, the third substrate 190 may be an organic bridge including an organic material.

[0130] Figure 2e 2 is a view showing a semiconductor package according to a fifth embodiment.

[0131] refer to Figure 2e The semiconductor package according to the fifth embodiment is different from the semiconductor packages of the previous embodiments in that a fourth substrate 300 is disposed between the first substrate and the first semiconductor device.

[0132] The semiconductor package according to the fifth embodiment may include a fourth substrate 300 disposed on the first substrate 100 .

[0133] To this end, a first connection member 110 connecting the first substrate 100 and the fourth substrate 300 may be disposed on the first substrate 100 .

[0134] In addition, the semiconductor package according to the fifth embodiment may include a fifth connection member 320 disposed on the fourth substrate 300. In addition, the semiconductor package according to the fifth embodiment may include a semiconductor device 320 disposed on the fifth connection member 320. The semiconductor device 320 may be provided as one, or the semiconductor device 320 may be provided in plurality.

[0135] Meanwhile, the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may perform a function of connecting the first substrate 100 and the semiconductor device 320. In addition, the fourth substrate 300 may perform a function of connecting a plurality of semiconductor devices 320.

[0136] At this time, the fourth substrate 300 may also be referred to as an interposer connecting the first substrate 100 and the semiconductor device 320 .

[0137] In one embodiment, the fourth substrate 300 may be an active interposer used as a semiconductor device. When the fourth substrate 300 is used as a semiconductor device, the package of the fifth embodiment can have a structure in which a plurality of logic chips having a vertical stacking structure are mounted on the first substrate 100. In addition, the first logic chip corresponding to the active interposer among the logic chips can perform the function of the corresponding logic chip while performing a signal transmission function between the second logic chip disposed on the upper side thereof and the first substrate 100.

[0138] According to another embodiment, the fourth substrate 300 may be a passive interposer. For example, the fourth substrate 300 may perform a signal relay function between the semiconductor device 320 and the first substrate 100. For example, due to reasons such as 5G, Internet of Things (IOT), increase in image quality, and increase in communication speed, the number of terminals in the semiconductor device 320 is gradually increasing. That is, the number of terminals provided in the semiconductor device 320 is increasing, and thus the width of the terminal or the spacing between the plurality of terminals is decreasing. At this time, the first substrate 100 is connected to the main board of the electronic device. Therefore, in order to make the pads provided on the first substrate 100 have a width and spacing respectively connected to the semiconductor device 320 and the main board, there is a problem that the thickness of the first substrate 100 increases or the layer structure of the first substrate 100 becomes complicated. Therefore, the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may include pads having a tiny width and spacing corresponding to the terminals of the semiconductor device 320.

[0139] Figure 2f is a view showing a semiconductor package according to a sixth embodiment.

[0140] refer to Figure 2f The semiconductor package according to the sixth embodiment is different from the semiconductor package according to the fifth embodiment in that a fifth substrate 330 is additionally disposed on the fourth substrate 300 .

[0141] A plurality of semiconductor devices 320 horizontally spaced apart from each other may be disposed on the fourth substrate 300. In addition, the plurality of semiconductor devices 320 may be active devices of different types or the same type. For example, the plurality of semiconductor devices 320 may mean different types of AP chips. In addition, one of the plurality of semiconductor devices 320 may be an AP chip, and another chip may be a memory chip.

[0142] In addition, the semiconductor package of the sixth embodiment further includes a fifth substrate 330. The fifth substrate 330 may be embedded in the fourth substrate 300, but is not limited thereto. For example, the fifth substrate 330 may be disposed on the fourth substrate 300 and may perform a function of connecting a plurality of semiconductor devices 320.

[0143] The fifth substrate 330 may include a redistribution layer. For example, the fifth substrate 330 may be a bridge. The fifth substrate 330 may include a silicon bridge. Alternatively, the fifth substrate 330 may be an organic bridge including an organic material.

[0144] Meanwhile, each of the semiconductor packages of the first to sixth embodiments includes the connection member as described above.

[0145] At this time, the connection part may be a member that plays a role of electrically connecting a plurality of components using at least one bonding method of wire bonding, solder bonding, and direct metal bonding.

[0146] That is, since the connection part has a function of electrically connecting a plurality of components, when direct metal bonding is used, the connection part may be understood as a part for electrical connection, rather than solder or a wire.

[0147] The wire bonding method may mean electrically connecting multiple components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect multiple components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal bonding method may mean directly bonding multiple components by applying heat and pressure between multiple components without a member such as solder, wire, or conductive adhesive to recrystallize the multiple components. In addition, the direct bonding method between metals may mean a connecting member connecting a substrate and a semiconductor device. At this time, the connecting member of the direct bonding method may mean a metal layer formed between multiple components by recrystallization.

[0148] Hereinafter, a circuit board of the embodiment will be described.

[0149] Before describing a circuit board of the embodiment, the circuit board described below may mean any one of a plurality of substrates included in a previous semiconductor package.

[0150] For example, the circuit board described below may refer to Figure 2a to Figure 2cIn addition, when the circuit board refers to the first substrate 100, the pad described below may refer to any one of a first pad on which the first connection member 110 is disposed, a second pad on which the second connection member 140 is disposed, and a third pad on which the third connection member 160 is disposed.

[0151] In addition, the circuit board described below may refer to Figure 2d The first substrate 100 included in the semiconductor package of the present invention may, alternatively, mean the second substrate 200 , or alternatively, may mean the third substrate 190 .

[0152] In addition, the circuit board described below may refer to Figure 2e The first substrate 100 included in the semiconductor package of the present invention and, alternatively, may mean a fourth substrate 300 .

[0153] In addition, the circuit board described below may refer to Figure 2f The first substrate 100 included in the semiconductor package of the present invention may refer to the fourth substrate 300 , or may refer to the fifth substrate 330 , alternatively.

[0154] That is, the circuit board of the embodiment is characterized by the structure of the pad on which the connecting member is arranged. In one embodiment, the pad on which the connecting member is arranged may be a pad connected to a semiconductor device. In another embodiment, the pad on which the connecting member is arranged may be a pad connected to a mainboard of an electronic device. In another embodiment, the pad on which the connecting member is arranged may mean a pad connected to the fourth substrate 300. In another embodiment, the pad on which the connecting member is arranged may mean a pad connected to the fifth substrate 330.

[0155] In summary, the pads of the circuit board described below may mean one or more of the plurality of pads included in the first substrate 100. Alternatively, the pads of the circuit board described below may mean one or more of the plurality of pads included in the second substrate 200. Alternatively, the pads of the circuit board described below may mean one or more of the plurality of pads included in the third substrate 190. Alternatively, the pads of the circuit board described below may mean one or more of the plurality of pads included in the fourth substrate 300. Alternatively, the pads of the circuit board described below may mean one or more of the plurality of pads included in the fifth substrate 330.

[0156] Hereinafter, the circuit board of the embodiment is described as Figure 2c FIG. 1 is a diagram showing a first substrate 100 of a semiconductor package according to a third embodiment of the present invention.

[0157] Accordingly, as an example, a pad described below may mean a first pad connected to the first semiconductor device 120 , and a connection member described below may mean a first connection member 110 connected between the first semiconductor device 120 and the first pad.

[0158] As another example, a pad described below may mean a second pad connected to the second substrate 200 , and a connecting member described below may mean a fourth connecting member 180 connected between the second substrate 200 and the second pad.

[0159] As another example, the pad described below may mean a third pad connected to a main board of the electronic device, and the connecting member described below may mean a third connecting member 160 connected between the main board and the third pad.

[0160] Figure 3 is a cross-sectional view showing a circuit board according to an embodiment.

[0161] refer to Figure 3 , the circuit board 400 includes an insulating layer 410 .

[0162] The insulating layer 410 may have one or more layers. Preferably, the insulating layer 410 may have a multi-layer structure.

[0163] However, although the insulating layer 410 of the circuit board 400 is illustrated as having a single-layer structure in the figure, the embodiment is not limited thereto. For example, the insulating layer 410 may have a structure in which a plurality of layers are laminated in a vertical direction. Preferably, the circuit board 400 may have a multilayer structure of at least two or more layers.

[0164] For convenience of explanation, the following description will be made assuming that the insulating layer of the circuit board 400 consists of one layer.

[0165] The insulating layer 410 may be rigid or flexible.

[0166] For example, the insulating layer 410 may include a prepreg. For example, the insulating layer 410 may be a prepreg in which glass fibers are impregnated in a resin. The resin may be an epoxy resin, but is not limited thereto.

[0167] In addition, the insulating layer 410 may include chemically strengthened / semi-strengthened glass, such as soda-lime glass or aluminosilicate glass. For example, the insulating layer 410 may include strengthened or flexible plastics, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 410 may include sapphire. For example, the insulating layer 410 may include an optically isotropic film. For example, the insulating layer 410 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 410 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 410 may have a structure in which an inorganic filler of silicon dioxide or aluminum oxide is disposed in a thermosetting resin or a thermoplastic resin. For example, the insulating layer 410 may use ABF (Ajinomoto stacked film), FR-4, BT (bismaleimide triazine), PID (photoimageable dielectric resin), BT, etc. For example, the insulating layer 410 may include RCC (resin coated copper).

[0168] The insulating layer 410 may have a thickness in the range of 10 μm to 60 μm. For example, when the insulating layer 410 includes a plurality of layers, each of the plurality of layers may have a thickness in the range of 10 μm to 60 μm. Preferably, the insulating layer 410 may have a thickness in the range of 15 μm to 55 μm. More preferably, the insulating layer 410 may have a thickness in the range of 18 μm to 52 μm.

[0169] The thickness of the insulating layer 410 may mean a vertical distance between a plurality of circuit pattern layers disposed adjacent to each other in a thickness direction. For example, the thickness of the insulating layer 410 may mean a vertical distance between a first circuit pattern layer 420 and a second circuit pattern layer 430. For example, the thickness of the insulating layer 410 may mean a vertical distance between a lower surface of the first circuit pattern layer 420 and an upper surface of the second circuit pattern layer 430.

[0170] If the thickness of the insulating layer 410 is less than 10 μm, the warpage characteristics of the circuit board 400 may be deteriorated. For example, if the thickness of the insulating layer 410 is less than 10 μm, the first circuit pattern layer 420 and the second circuit pattern layer 430 disposed on the surface of the insulating layer 410 may not be stably protected, and therefore, electrical reliability and / or physical reliability problems may occur. In addition, if the thickness of the insulating layer 410 is less than 10 μm, workability in a process of forming the first circuit pattern layer 420 or the second circuit pattern layer 430 on the insulating layer 410 may be deteriorated.

[0171] In addition, if the thickness of the insulating layer 410 exceeds 60 μm, the overall thickness of the circuit board 400 may increase, and thus the thickness of the semiconductor package may increase. In addition, if the thickness of the insulating layer 410 exceeds 60 μm, it may be difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 430. For example, if the thickness of the insulating layer 410 exceeds 60 μm, it may be difficult to form the width of the first circuit pattern layer and / or the second circuit pattern layer 430 and the spacing between adjacent patterns to 12 μm or less, 10 μm or less, 8 μm or less, or 6 μm or less. In addition, if it is difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 430, the circuit integration may be reduced, and therefore, the signal transmission distance may increase, which may increase the signal transmission loss.

[0172] Meanwhile, if the circuit board 400 of the embodiment has a multilayer structure, at least one of the plurality of insulating layers may include an insulating material different from the material of at least one other insulating layer. For example, when the circuit board 400 includes a plurality of insulating layers, at least one insulating layer may be an insulating layer including reinforcing fibers, and at least one other insulating layer may be an insulating layer not including reinforcing fibers. In addition, the insulating layer including reinforcing fibers may be a core layer. Therefore, the circuit board 400 may be a core substrate including a core layer, but is not limited thereto.

[0173] In addition, when the circuit board 400 is a core substrate, the thickness of the insulating layer 410 described above may mean the thickness of the insulating layer excluding the reinforcing fiber.

[0174] The circuit board 400 includes a circuit pattern layer disposed on an insulating layer 410 .

[0175] For example, the circuit board 400 includes a first circuit pattern layer 420 disposed on an upper surface of the insulating layer 410. In addition, the circuit board 400 includes a second circuit pattern layer 430 disposed on a lower surface of the insulating layer 410.

[0176] The first circuit pattern layer 420 may be divided into a plurality of circuit patterns according to position or function. For example, the first circuit pattern layer 420 may include at least one pad. For example, the first circuit pattern layer 420 may include a pad on which a semiconductor device is mounted. For example, the first circuit pattern layer 420 may include a pad to which an external substrate is coupled. As an example, the first circuit pattern layer 420 may include a pad coupled to an interposer. As another example, the first circuit pattern layer 420 may include a pad coupled to a bridge substrate. As another example, the first circuit pattern layer 420 may include a pad coupled to a memory substrate including a memory chip.

[0177] The first circuit pattern layer 420 may refer to a first outermost circuit pattern layer of the circuit board 400. Specifically, when the circuit board 400 has a multilayer structure including a plurality of insulating layers, the first circuit pattern layer 420 may refer to a circuit pattern layer on an upper surface of an insulating layer disposed at an uppermost side among the plurality of insulating layers.

[0178] The first circuit pattern layer 420 may include a plurality of metal layers. For example, the first circuit pattern layer 420 may include a first metal layer disposed on the upper surface of the insulating layer 410 and a second metal layer disposed on the first metal layer. The first metal layer of the first circuit pattern layer 420 may be a seed layer for electroplating the second metal layer of the first circuit pattern layer 420. The thickness of the first metal layer of the first circuit pattern layer 420 may satisfy the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer of the first circuit pattern layer 420 may satisfy the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer of the first circuit pattern layer 420 may satisfy the range of 0.5 μm to 2.5 μm.

[0179] If the thickness of the first metal layer of the first circuit pattern layer 420 is less than 0.2 μm, the first metal layer of the first circuit pattern layer 420 may not function as a seed layer. If the thickness of the first metal layer of the first circuit pattern layer 420 is less than 0.2 μm, it may be difficult to form a first metal layer having a uniform thickness on the upper surface of the insulating layer 410.

[0180] In addition, if the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, the process time for forming the first metal layer of the first circuit pattern layer 420 may increase, and thus the yield may decrease. In addition, if the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, the etching time of the first metal layer may increase in the formation process of the first circuit pattern layer 420. In addition, if the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, when etching the first metal layer of the first circuit pattern layer 420, deformation of the second metal layer of the first circuit pattern layer 420 may occur. Here, the deformation of the second metal layer of the first circuit pattern layer 420 may mean that when etching the first metal layer, as the side of the second metal layer is also etched, the difference between the width of the upper surface and the width of the lower surface of the second metal layer increases. For example, the deformation of the second metal layer of the first circuit pattern layer 420 may mean that the shape of the vertical cross section of the second metal layer changes from a square to a trapezoid.

[0181] In addition, if the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, the etching amount in the etching process of the first metal layer increases, and therefore, the depth of the dent (e.g., undercut) formed on the side of the first metal layer and the side of the second metal layer may increase. For example, if the etching amount in the etching process of the first metal layer increases, the difference between the width of the first metal layer and the width of the second metal layer may increase. In addition, if the difference between the width of the first metal layer and the width of the second metal layer increases, the electrical characteristics may deteriorate due to the increase in signal transmission loss. In addition, if the difference between the width of the first metal layer and the width of the second metal layer increases, dendrites may be formed by electromigration, and thus the electrical characteristics and / or physical characteristics of the first circuit pattern layer 420 may deteriorate.

[0182] The second metal layer of the first circuit pattern layer 420 may be an electroplated layer in which the first metal layer is electroplated as a seed layer. The second metal layer of the first circuit pattern layer 420 may be formed on the first metal layer with a predetermined thickness. The second metal layer of the first circuit pattern layer 420 may include the same metal as the first metal layer of the first circuit pattern layer 420, but is not limited thereto. For example, the first metal layer and the second metal layer of the first circuit pattern layer 420 may both include copper.

[0183] The thickness of the second metal layer of the first circuit pattern layer 420 may be greater than the thickness of the first metal layer of the first circuit pattern layer 420 .

[0184] The thickness of the second metal layer of the first circuit pattern layer 420 may be within a range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer of the first circuit pattern layer 420 may be within a range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer of the first circuit pattern layer 420 may be within a range of 4.5 μm to 22 μm.

[0185] If the thickness of the second metal layer of the first circuit pattern layer 420 is less than 3.5 μm, etching of the second metal layer may also be performed during the etching process of the first metal layer. If the thickness of the second metal layer of the first circuit pattern layer 420 is less than 3.5 μm, the allowed current of the signal transmitted through the first circuit pattern layer may be reduced, and thus the electrical characteristics may be degraded. If the thickness of the second metal layer of the first circuit pattern layer 420 exceeds 25 μm, it may be difficult to miniaturize the first circuit pattern layer 420. For example, if the thickness of the second metal layer of the first circuit pattern layer 420 exceeds 25 μm, the width and spacing of the pattern constituting the first circuit pattern layer 420 may not meet the required conditions. As a result, the circuit integration may be reduced, or the volume of the circuit board and the semiconductor package may increase.

[0186] The circuit board 400 of the embodiment may include a second circuit pattern layer 430 disposed on the lower surface of the insulating layer 410. The second circuit pattern layer 430 may have a structure corresponding to the first circuit pattern layer 420. The second circuit pattern layer 430 may include at least one pad. For example, the second circuit pattern layer 430 may include a pad on which a semiconductor device is mounted. For example, the second circuit pattern layer 430 may include a pad coupled to an external substrate. As an example, the second circuit pattern layer 430 may include a pad coupled to a mainboard of an electronic device.

[0187] The second circuit pattern layer 430 may mean the second outermost circuit pattern layer of the circuit board 400. For example, when the circuit board 400 has a multilayer structure including a plurality of insulating layers, the second circuit pattern layer 430 may refer to a circuit pattern layer on a lower surface of an insulating layer disposed at a lowermost side among the plurality of insulating layers.

[0188] Each of the first circuit pattern layer 420 and the second circuit pattern layer 430 may include a groove.

[0189] For example, the first circuit pattern layer 420 may include a first groove 420 - 1 .

[0190] Specifically, the first circuit pattern layer 420 includes a pad and a trace connected to the pad. In addition, the pad of the first circuit pattern layer 420 has a first groove 420-1. The first groove 420-1 can be formed concavely from the upper surface of the pad of the first circuit pattern layer 420 toward the lower surface of the pad of the first circuit pattern layer 420.

[0191] The first groove 420 - 1 may refer to a concave portion formed on an upper surface of the pad of the first circuit pattern layer 420 .

[0192] The first groove 420-1 may have different depths along the horizontal direction. For example, the bottom surface of the first groove 420-1 may have a concavo-convex shape. Therefore, the upper surface of the pad of the first circuit pattern layer 420 may have a concavo-convex shape corresponding to the bottom surface of the first groove 420-1.

[0193] At this time, the first groove 420 - 1 may be completely provided on the upper surface of the pad of the first circuit pattern layer 420 , or differently, may be provided on a portion of the upper surface of the pad of the first circuit pattern layer 420 .

[0194] At least a portion of the first groove 420-1 vertically overlaps with the first protective layer 450 disposed on the insulating layer 410. Therefore, at least a portion of the upper surface of the pad of the first circuit pattern layer 420 may vertically overlap with the first protective layer 450 and not contact the first protective layer 450. For example, a crack corresponding to the first groove 420-1 may be provided between the upper surface of the pad of the first circuit pattern layer 420 and the lower surface of the first protective layer 450.

[0195] Meanwhile, the first circuit pattern layer 420 includes a pattern other than a pad. At this time, the pad of the first circuit pattern layer 420 may mean a pattern in the first circuit pattern layer 420 that vertically overlaps the opening 440-1 of the first protective layer 450, which will be described below. For example, the pad of the first circuit pattern layer 420 may mean a pattern in the first circuit pattern layer 420 that includes an area vertically overlapping the opening 440-1 of the first protective layer 450.

[0196] In addition, the pattern other than the pad of the first circuit pattern layer 420 may mean a pattern in the first circuit pattern layer 420 that does not vertically overlap with the opening 440-1 of the first protective layer 450. For example, the upper surface of the pattern other than the pad of the first circuit pattern layer 420 may be completely covered by the first protective layer 450. In addition, the pattern other than the pad of the first circuit pattern layer 420 may include a trace.

[0197] In addition, the first groove may not be provided on the upper surface of the trace of the first circuit pattern layer 420. That is, the first groove 420-1 may be formed by processing a portion of the first circuit pattern layer 420 exposed through the opening 440-1 of the first protective layer 450 while forming the first protective layer 450. At this time, the trace of the first circuit pattern layer 420 is not exposed through the opening 440-1 of the first protective layer 450. That is, the trace of the first circuit pattern layer 420 may be completely covered by the first protective layer 450. Therefore, the first groove may not be formed on the upper surface of the trace of the first circuit pattern layer 420.

[0198] Therefore, the first circuit pattern layer 420 may include patterns having different heights. For example, at least a portion of the upper surface of the pad of the first circuit pattern layer 420 may be positioned lower than the upper surface of the trace of the first circuit pattern layer 420. For example, the upper surface of the pad of the first circuit pattern layer 420 provided with the first groove 420-1 may be positioned lower than the upper surface of the trace not provided with the first groove. For example, the upper surface of the pad of the first circuit pattern layer 420 may be positioned lower than the upper surface of the trace of the first circuit pattern layer 420 by the depth of the first groove 420-1.

[0199] In addition, the second circuit pattern layer 430 may include a second groove 430 - 1 .

[0200] Specifically, the second circuit pattern layer 430 includes a pad and a trace connected to the pad. In addition, the pad of the second circuit pattern layer 430 has a second groove 430-1. The second groove 430-1 can be formed protrudingly from the lower surface of the pad of the second circuit pattern layer 430 toward the upper surface of the pad of the second circuit pattern layer 430.

[0201] The second groove 430 - 1 may mean a convex portion formed on the lower surface of the pad of the second circuit pattern layer 430 .

[0202] The second groove 430-1 may have different depths along the horizontal direction. For example, the bottom surface of the second groove 430-1 may have a concavo-convex shape. Accordingly, the lower surface of the pad of the second circuit pattern layer 430 may have a concavo-convex shape corresponding to the bottom surface of the second groove 430-1.

[0203] At this time, the second groove 430 - 1 may be entirely provided on the lower surface of the pad of the second circuit pattern layer 430 , or alternatively, may be provided on a portion of the lower surface of the pad of the second circuit pattern layer 430 .

[0204] At least a portion of the second groove 430-1 vertically overlaps with the second protective layer 460 disposed below the insulating layer 410. Therefore, at least a portion of the lower surface of the pad of the second circuit pattern layer 430 may vertically overlap with the second protective layer 460 and may not contact the second protective layer 460. For example, a crack corresponding to the second groove 430-1 may be provided between the lower surface of the pad of the second circuit pattern layer 430 and the upper surface of the second protective layer 460.

[0205] Meanwhile, the second circuit pattern layer 430 includes a pattern other than a pad. At this time, the pad of the second circuit pattern layer 430 may mean a pattern in the second circuit pattern layer 430 that vertically overlaps with an opening 460-1 of a second protective layer 460 to be described below. For example, the pad of the second circuit pattern layer 430 may mean a pattern in the second circuit pattern layer 430 that includes an area vertically overlapping with an opening 460-1 of the second protective layer 460.

[0206] In addition, the pattern other than the pad of the second circuit pattern layer 430 may mean a pattern in the second circuit pattern layer 430 that does not vertically overlap with the opening 460-1 of the second protective layer 460. For example, the lower surface of the pattern other than the pad of the second circuit pattern layer 430 may be completely covered by the second protective layer 460. In addition, the pattern other than the pad of the second circuit pattern layer 430 may include a trace.

[0207] In addition, the second groove may not be formed on the lower surface of the trace of the second circuit pattern layer 430. That is, the second groove 430-1 may be formed by processing a portion of the second circuit pattern layer 430 exposed through the opening of the second protective layer 460 while forming the second protective layer 460. At this time, the trace of the second circuit pattern layer 430 is not exposed through the opening 460-1 of the second protective layer 460. That is, the trace of the second circuit pattern layer 430 may be completely covered by the second protective layer 460. Therefore, the second groove may not be formed on the lower surface of the trace of the second circuit pattern layer 430.

[0208] Therefore, the second circuit pattern layer 430 may include patterns having different heights. For example, at least a portion of the lower surface of the pad of the second circuit pattern layer 430 may be positioned higher than the lower surface of the trace of the second circuit pattern layer 430. For example, the lower surface of the pad of the second circuit pattern layer 430 provided with the second groove 430-1 may be positioned higher than the lower surface of the trace not provided with the second groove. For example, the lower surface of the pad of the second circuit pattern layer 430 may be positioned lower than the lower surface of the trace of the second circuit pattern layer 430 by the depth of the second groove 430-1.

[0209] The groove formed in each pad of the first circuit pattern layer 420 and the second circuit pattern layer 430 will be described in more detail below.

[0210] The circuit board 400 of the embodiment may include a through electrode 440. The through electrode 440 may penetrate the insulating layer 410. Preferably, the through electrode 440 can penetrate the insulating layer 410 to electrically connect between the first circuit pattern layer 420 and the second circuit pattern layer 430. At this time, when the circuit board 400 has a multi-layer structure, the through electrode 440 can electrically connect between adjacent circuit pattern layers while being spaced apart in the vertical direction.

[0211] The through electrode 440 can be formed by filling the inside of a through hole penetrating the insulating layer 410 with a conductive material.

[0212] The through hole can be formed by any one of mechanical, laser, and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. In addition, when the through hole is formed by laser processing, UV or CO2 laser methods can be used. In addition, when the through hole is formed by chemical processing, chemical agents including aminosilane, ketones, etc. can be used.

[0213] The through-electrode 440 includes a plurality of metal layers.

[0214] The through electrode 440 may include a first metal layer and a second metal layer corresponding to the first circuit pattern layer 420 and the second circuit pattern layer 430 .

[0215] Meanwhile, above, since the first and second circuit pattern layers 420 and 430 of the embodiment are manufactured through the SAP process, the first and second circuit pattern layers 420 and 430 of the embodiment are described as including the first and second metal layers, but are not limited thereto.

[0216] For example, the first circuit pattern layer 420 and the second circuit pattern layer 430 may be manufactured by the MSAP process. Therefore, each of the first circuit pattern layer 420 and the second circuit pattern layer 430 may additionally have a third metal layer disposed between the first metal layer and the insulating layer. The third metal layer may refer to a copper layer attached during lamination of the insulating layer, but is not limited thereto.

[0217] Meanwhile, each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may include a conductive material. For example, each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0218] The first circuit pattern layer 420 , the second circuit pattern layer 430 , and the through-electrode 440 can all be manufactured using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed descriptions thereof are omitted herein.

[0219] Meanwhile, the circuit board 400 of the embodiment may include a protection layer.

[0220] For example, the circuit board 400 may include a first protective layer 450 disposed on the insulating layer 410. For example, the circuit board 400 may include a second protective layer 460 disposed under the insulating layer 410.

[0221] The first protective layer 450 and the second protective layer 460 may be resist layers. Preferably, the first protective layer 450 and the second protective layer 460 may be solder resist layers comprising organic polymer materials. For example, the first protective layer 450 and the second protective layer 460 may comprise epoxy acrylate series resins. Specifically, the first protective layer 450 and the second protective layer 460 may comprise resins, curing agents, pigments, solvents, fillers, additives, acrylic acid series monomers, etc.

[0222] The total thickness of each of the first and second protective layers 450 and 460 may be greater than the thickness of each of the first and second circuit pattern layers 420 and 430. The total thickness may mean a vertical distance between lower and upper surfaces of the first and second protective layers 450 and 460.

[0223] The total thickness of the first protective layer 450 may be within a range of 6.7 μm to 35.0 μm. Preferably, the total thickness of the first protective layer 450 may be within a range of 7.3 μm to 32 μm. More preferably, the total thickness of the first protective layer 450 may be within a range of 8.0 μm to 30 μm.

[0224] If the total thickness of the first protective layer 450 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package may increase. In addition, if the total thickness of the first protective layer 450 is less than 6.7 μm, the first circuit pattern layer may not be stably protected, and thus, electrical reliability or physical reliability may be deteriorated.

[0225] In addition, the second protective layer 460 may have a thickness corresponding to that of the first protective layer 450 , but is not limited thereto.

[0226] The first protective layer 450 and the second protective layer 460 may each include an opening.

[0227] For example, the first protective layer 450 may include a first opening 450-1. The first opening 450-1 may vertically overlap at least a portion of the first circuit pattern layer 420. Therefore, the first opening 450-1 of the first protective layer 450 may expose at least a portion of the upper surface of the first circuit pattern layer 420. Preferably, the first protective layer 450 may include a first opening 450-1 vertically overlapping a pad of the first circuit pattern layer 420. In this case, the width of the first opening 450-1 may be smaller than the width of the pad of the first circuit pattern layer 420. Therefore, at least a portion of the pad of the first circuit pattern layer 420 may vertically overlap with the first opening 450-1 of the first protective layer 450, and the remaining portion of the pad of the first circuit pattern layer 420 may not vertically overlap with the first opening 450-1 of the first protective layer 450.

[0228] At least a portion 450 of the first protective layer may vertically overlap with the pad of the first circuit pattern layer 420 and not contact the pad of the first circuit pattern layer 420. For example, the first protective layer 450 may include an overlapping region vertically overlapping with the pad of the first circuit pattern layer 420. In addition, at least a portion of the lower surface of the overlapping region of the first protective layer 450 may not contact the pad of the first circuit pattern layer 420. For example, at least a portion of the lower surface of the overlapping region of the first protective layer 450 may vertically overlap with the first groove 420-1 formed on the upper surface of the pad of the first circuit pattern layer 420. Therefore, a crack may be provided between at least a portion of the lower surface of the overlapping region of the first protective layer 450 and the upper surface of the pad of the first circuit pattern layer 420.

[0229] In addition, the second protective layer 460 may include a second opening 460-1. The second opening 460-1 may vertically overlap with at least a portion of the second circuit pattern layer 430. Through this, the second opening 460-1 of the second protective layer 460 may expose at least a portion of the lower surface of the second circuit pattern layer 430. Preferably, the second protective layer 460 may include a second opening 460-1 vertically overlapping with the pad of the second circuit pattern layer 430. The width of the second opening 460-1 may be smaller than the width of the pad of the second circuit pattern layer 430. Therefore, at least a portion of the pad of the first circuit pattern layer 430 may vertically overlap with the second opening 460-1 of the second protective layer 460, and the remaining portion of the pad of the first circuit pattern layer 430 may not vertically overlap with the second opening 460-1 of the second protective layer 460.

[0230] At least a portion of the second protective layer 460 may vertically overlap with the pad of the second circuit pattern layer 430 and may not contact the pad of the second circuit pattern layer 430. For example, the second protective layer 460 may include an overlapping region that vertically overlaps the pad of the second circuit pattern layer 430. In addition, at least a portion of the upper surface of the overlapping region of the second protective layer 460 may not contact the pad of the second circuit pattern layer 430. For example, at least a portion of the upper surface of the overlapping region of the second protective layer 460 may vertically overlap with the second groove 430-1 formed on the lower surface of the pad of the second circuit pattern layer 430. Therefore, a crack may be provided between at least a portion of the upper surface of the overlapping region of the second protective layer 460 and the lower surface of the pad of the second circuit pattern layer 430.

[0231] Figure 4a is an enlarged cross-sectional view of a portion of a circuit board according to the first embodiment, Figure 4b yes Figure 4a A plan view of the circuit board, and Figure 4c is shown in which the connecting member is arranged Figure 4a A cross-sectional view of the state of the circuit board.

[0232] In the following, reference Figures 4a to 4c , specifically describing the pads provided on the circuit board of the first embodiment, the grooves formed on the pads, and the protective layer including the openings.

[0233] A pad described below may mean a pad of the first circuit pattern layer 420, or differently, a pad of the second circuit pattern layer 430. However, for convenience of explanation, a description is given by assigning a drawing symbol of the pad to that of the first circuit pattern layer 420.

[0234] The circuit board of the first embodiment includes an insulating layer 410 and a pad 420 disposed on the insulating layer 410. The pad 420 may mean a pad of one of the circuit pattern layers of the first circuit pattern layer and the second circuit pattern layer.

[0235] The pad 420 is disposed on the insulating layer 410. An upper surface of the pad 420 may have a step.

[0236] For example, the pad 420 may have a recessed groove 420-1 formed from the upper surface of the pad 420 toward the lower surface of the pad 420. The recess 420-1 may also be referred to as a recessed trench from the upper surface of the pad 420 toward the lower surface of the pad 420.

[0237] The groove 420-1 may be provided on a portion of the upper surface of the pad 420. For example, the pad 420 may include a first portion P1 including the groove 420-1 and a second portion P2 not including the groove 420-1.

[0238] The upper surface of the first portion P1 of the pad 420 may be positioned lower than the upper surface of the second portion P2 of the pad 420. For example, the upper surface of the first portion P1 of the pad 420 may be positioned lower than the upper surface of the second portion P2 of the pad 420 by a depth corresponding to the groove 420-1.

[0239] The pad 420 may have a first thickness T1. Here, the first thickness T1 may mean the thickness of the portion having the largest thickness among the entire area of ​​the pad 420. For example, the first thickness T1 of the pad 420 may mean the thickness of the second portion P2 of the pad 420. For example, the first thickness T1 of the pad 420 may mean the value of the sum of the thickness of the first portion P1 of the pad 420 and the depth of the groove 420-1.

[0240] The first thickness T1 of the pad 420 may satisfy the range of 3.7 μm to 28 μm. For example, the first thickness T1 of the pad 420 may satisfy the range of 4.3 μm to 25.8 μm. For example, the first thickness T1 of the pad 420 may satisfy the range of 5 μm to 24.5 μm. Preferably, the first thickness T1 of the pad 420 may mean the sum of the thicknesses of the first metal layer and the second metal layer of the above-mentioned first circuit pattern layer 420. In addition, if the first thickness T1 of the pad 420 exceeds the above-mentioned range, the previously described problems may occur.

[0241] At this time, the groove 420 - 1 may be provided with a certain depth on the upper surface of the first portion P1 of the pad 420 .

[0242] The groove 420-1 may have a first depth T2. The first depth T2 may mean the difference between the thickness of the first portion P1 of the pad 420 and the thickness of the second portion P2. At this time, the first portion P1 of the pad 420 has a concave-convex shape. Therefore, the first portion P1 of the pad 420 has different thicknesses or heights in the horizontal direction. Therefore, the thickness of the first portion P1 of the pad 420 may mean the thickness of the area with the smallest thickness among the entire area of ​​the first portion P1. Alternatively, the thickness of the first portion P1 of the pad 420 may mean the average thickness of the entire area of ​​the first portion P1.

[0243] In addition, the first depth T2 of the groove 420-1 and the difference may mean a vertical spacing distance from the lower surface of the first region R1 of the protective layer 450 described below to the upper surface of the first portion P1 of the pad 420. The vertical spacing distance may mean a maximum vertical spacing distance. For example, the vertical spacing distance may mean a vertical distance from the upper surface of the first portion P1 of the pad 420 having the lowest height to the lower surface of the first region R1 of the protective layer 450. However, the embodiment is not limited thereto, and the vertical spacing distance may mean an average spacing distance.

[0244] Therefore, the first depth T2 of the groove 420 - 1 may have the same meaning as the thickness difference and the vertical spacing distance between the first portion P1 and the second portion P2 of the pad 420 .

[0245] The first depth T2 may have a range of 5% to 55% of the first thickness T1. Preferably, the first depth T2 may have a range of 7% to 52% of the first thickness T1. More preferably, the first depth T2 may have a range of 8% to 50% of the first thickness T1.

[0246] If the first depth T2 is less than 5% of the first thickness T1, the effect that may be derived from the groove 420-1 may not be significant. That is, the groove 420-1 is provided to improve the bonding strength and adhesion between the connection member 500 and the pad 420. At this time, if the first depth T2 is less than 5% of the first thickness T1, the effect of improving the bonding strength or adhesion may not be significant. As a result, cracks may occur in the connection member 500, or physical and / or electrical reliability problems may occur in which the connection member 500 is separated from the pad 420.

[0247] If the first depth T2 exceeds 55% of the first thickness T1, the amount of the connecting member 500 filled in the groove 420-1 may increase. In addition, if the amount of the connecting member 500 increases, the rigidity of the connecting member 500 may be weakened, and thus cracks may occur. In addition, if the first depth T2 exceeds 55% of the first thickness T1, the thickness deviation of the connecting member 500 may increase, and thus the connection reliability may deteriorate. In addition, if the first depth T2 exceeds 55% of the first thickness T1, the thickness deviation of the pad 420 for each region increases, and electrical reliability problems may occur accordingly. For example, if the thickness deviation for each region increases, the transmission loss of the signal flowing through the pad 420 may increase, or the allowable current of the signal that can be provided by the pad 420 may decrease.

[0248] The protective layer 450 may include a plurality of regions.

[0249] For example, the protective layer 450 includes a first region R1 adjacent to the opening 450-1. That is, the protective layer 450 includes the first region R1 including the opening 450-1 and vertically overlapping the pad 420. In addition, the protective layer 450 may include a second region excluding the first region R1.

[0250] In addition, the lower surface of the first region R1 of the protective layer 450 can be divided into a plurality of lower surfaces. For example, the lower surface of the first region R1 of the protective layer 450 can include a first lower surface not contacting the upper surface of the pad 420 and a second lower surface contacting the upper surface of the pad 420 .

[0251] Specifically, the lower surface of the first region R1 of the protection layer 450 includes a first lower surface that vertically overlaps the first portion P1 of the pad 420 and does not contact the first portion P1 of the pad 420 through the groove 420 - 1 .

[0252] In addition, the lower surface of the first region R1 of the protection layer 450 includes a second lower surface vertically overlapping the second portion P2 of the pad 420 and contacting the upper surface of the second portion P2 .

[0253] That is, the groove 420-1 may form a crack between the upper surface of the first portion P1 of the pad 420 and the first lower surface of the first region R1 of the protective layer 450. In addition, the upper surface of the second portion P2 of the pad 420 and the second lower surface of the first region R1 of the protective layer 450 may directly contact each other.

[0254] The protective layer 450 may have a third thickness T3. At this time, the third thickness T3 may mean a thickness of the first region R1 of the protective layer 450.

[0255] Preferably, the third thickness T3 of the protection layer 450 may mean a vertical distance between an upper surface of the pad 420 and an upper surface of the protection layer 450 .

[0256] The third thickness T3 of the protective layer 450 can satisfy the range of 1 μm to 25 μm. Preferably, the third thickness T3 of the protective layer 450 can satisfy the range of 3 μm to 18.5 μm. More preferably, the third thickness T3 of the protective layer 450 can satisfy the range of 3 μm to 16.5 μm. In addition, if the third thickness T3 of the protective layer 450 exceeds the above range, as described above, the circuit pattern layer may not be stably protected or the overall thickness of the circuit board may increase.

[0257] Meanwhile, the first portion P1 of the pad 420 may be divided into a plurality of sub-portions. This may be divided based on a plurality of regions of the protective layer 450.

[0258] In addition, the upper surface of the first portion P1 of the pad 420 does not contact the protective layer 450. However, the upper surface of the first portion P1 of the pad 420 may include a first subportion P1-1 that does not vertically overlap the first protective layer 450, and a second subportion P1-2 that is connected to the first subportion P1-1 and does not vertically overlap the first portion P1.

[0259] That is, the first subportion P1-1 of the pad 420 may vertically overlap the opening 450-1 provided in the protective layer 450. In addition, the second subportion P1-2 of the pad 420 may vertically overlap the first region R1 of the protective layer 450 adjacent to the opening 450-1.

[0260] In other words, pad 420 includes first subportion P1-1 of first portion P1 vertically overlapping opening 450-1 of protective layer 460. Also, pad 420 includes second portion P2 vertically overlapping first region R1 of protective layer 450 and second subportion P1-2 of first portion P1.

[0261] At this time, the second sub-portion P1-2 and the second portion P2 of the first portion P1 vertically overlap with the first region R1 of the protective layer 450. At this time, the second sub-portion P1-2 of the first portion P1 has a groove 420-1. Therefore, the upper surface of the second sub-portion P1-2 of the first portion P1 does not contact the lower surface of the first region R1 of the protective layer 450. In addition, the second portion P2 of the pad 420 does not have the groove 420-1. Therefore, the upper surface of the second portion P2 of the pad 420 is in direct contact with the lower surface of the first region R1 of the protective layer 450.

[0262] In summary, second sub-portion P1-2 and second portion P2 of pad 420 of the embodiment vertically overlap first region R1 of protective layer 450. At this time, second sub-portion P1-2 of pad 420 is spaced apart from protective layer 450, and second portion P2 of pad 420 directly contacts protective layer 450.

[0263] At this time, the width W1 of the second sub-portion P1-2 of the pad 420 may be different from the width W2 of the second portion P2 of the pad 420. Preferably, the width W1 of the second sub-portion P1-2 of the pad 420 may be greater than the width W2 of the second portion P2 of the pad 420.

[0264] The width W1 of the second sub-portion P1-2 of the pad 420 may be within a range of 2 to 50 times the width W2 of the second portion P2 of the pad 420. Preferably, the width W1 of the second sub-portion P1-2 of the pad 420 may be within a range of 3 to 48 times the width W2 of the second portion P2 of the pad 420. More preferably, the width W1 of the second sub-portion P1-2 of the pad 420 may be within a range of 5 to 40 times the width W2 of the second portion P2 of the pad 420.

[0265] If width W1 of second subportion P1-2 of pad 420 is less than twice width W2 of second portion P2 of pad 420, the effect of increasing bonding strength and adhesion of connecting member 500 is insufficient, and thus, a reliability problem in which connecting member 500 is separated from pad 420 may occur.

[0266] In addition, if the width W1 of the second sub-portion P1-2 of the pad 420 exceeds 50 times the width W2 of the second portion P2 of the pad 420, the overall width of the pad 420 may be increased accordingly. In addition, if the overall width of the pad 420 increases, the circuit integration may decrease, and therefore, the overall volume of the circuit board may increase.

[0267] At the same time, if the center of the opening 450-1 of the protective layer 450 in the vertical direction is aligned with the center of the pad 420 in the vertical direction, the second sub-portion P1-2 of the pad 420 may have widths corresponding to each other in the entire region. In addition, the second portion P2 of the pad 420 may also have widths corresponding to each other in the entire region. Here, having a corresponding width may mean that the width deviation in the entire region is 30% or less, 20% or less, 15% or less, 10% or less, 5% or less, or 2% or less. For example, having a corresponding width may mean that the difference between the maximum width and the minimum width in the entire region is 3μm or less, 2μm or less, 1μm or less, or 0.5μm or less.

[0268] In contrast, if the center in the vertical direction of the opening 450-1 of the protective layer 450 is not aligned with the center in the vertical direction of the pad 420, the second sub-portion P1-2 and the second portion P2 of the pad 420 may have different widths in the entire region. In this case, the width W1 of the second sub-portion P1-2 and the width W2 of the second portion P2 may mean the width in one side portion adjacent to each other based on a vertical cross section.

[0269] For example, the width W1 of the second subportion P1-2 may mean the width of the area adjacent to the first side of the first subportion P1-1 in the vertical cross section, and the width W2 of the second portion P2 may mean the width of the area adjacent to the first side of the second subportion P1-2.

[0270] Meanwhile, the connection member 500 is disposed in the groove 420 - 1 and the opening 450 - 1 .

[0271] Therefore, the connection member 500 may be divided into a plurality of parts.

[0272] For example, the connection member 500 may include a first component disposed in the groove 420-1 of the pad 420. At this time, the first component of the connection member 500 may be positioned between the first region R1 of the first protection layer 450 and the first portion P1 of the pad 420. Therefore, the first component of the connection member 500 may contact the component 450LS of the lower surface of the first region R1 of the protection layer 450 and the upper surface of the first portion P1 of the pad 420.

[0273] In addition, the connection member 500 may include a component positioned on the first component and disposed in the opening 450-1 of the protective layer 450. The second component of the connection member 500 may have a shape corresponding to the shape of the opening 450-1. The second component of the connection member 500 may contact the inner surface 450IS of the first region R1 of the protective layer 450 forming the opening 450-1. At this time, the width of the opening 450-1 at the portion adjacent to the upper surface of the protective layer 450 and the width of the opening 450-1 at the portion adjacent to the lower surface of the protective layer 450 may be the same. Therefore, the second component of the connection member 500 may have a column shape in which the upper surface and the lower surface have the same width.

[0274] The connecting member 500 may include a third component disposed on the second component. The third component of the connecting member 500 may protrude on the upper surface of the protective layer 450. The upper surface of the third component of the connecting member 500 may have a curved surface convex in the upward direction. At least a portion of the third component of the connecting member 500 may be positioned on the first region R1 of the protective layer 450. Therefore, the third component of the connecting member 500 may contact the upper surface 450US of the first region R1 of the protective layer 450.

[0275] That is, an interface having a concavo-convex shape may be provided between the connection member 500 and the pad 420. At this time, the interface having a concavo-convex shape may mean the lower surface of the connection member 500. On the contrary, the interface having a concavo-convex shape may correspond to the upper surface of the first portion P1 of the pad 420. Therefore, the interface having a concavo-convex shape may have a structure of the first sub-portion P1-1 and the second sub-portion P1-2 of the first portion P1 of the pad 420.

[0276] The embodiment provides the groove 420-1 in the pad 420 as described above. In addition, the provided groove 420-1 can be used to improve the adhesion between the pad 420 and the connecting member 500. Specifically, the embodiment provides the connecting member 500 with an anchor structure, and is coupled to the pad 420 by using the groove 420-1. Therefore, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board.

[0277] Meanwhile, although the groove 420-1 is described above as being applied to all pads of the first circuit pattern layer 420 and the second circuit pattern layer 430, the embodiment is not limited thereto. For example, only some pads having a relatively small size or having low adhesion to the connection member 500 may have an anchor structure including the groove 420-1.

[0278] The circuit board and semiconductor package of this embodiment can improve the adhesion and bonding strength between the pad and the connection member. Therefore, this embodiment can solve the problem of cracks occurring in the connection member and thus improve the physical reliability and electrical reliability of the connection member.

[0279] To this end, the circuit board of this embodiment includes an insulating layer, a pad and a protective layer. The protective layer includes an opening that vertically overlaps at least a portion of the pad. At this time, the protective layer includes a first area adjacent to the opening and vertically overlapping the pad and a second area excluding the first area. In addition, the pad has a groove. The groove can be a recessed portion that is recessed from the upper surface of the pad toward the lower surface. The pad includes an upper surface having a concave-convex shape corresponding to the groove. At this time, the pad includes a first part including the groove and a second part that does not include the groove. At this time, the first part of the pad includes a first sub-portion of the opening of the vertically overlapping protective layer and a second sub-portion of the first area of ​​the vertically overlapping protective layer. At the same time, a connecting member is arranged on the pad. At this time, the connecting member is arranged to fill the groove of the pad. Therefore, the connecting member is not only arranged on the first sub-portion of the pad, but also arranged on the second sub-portion. In addition, a part of the connecting member arranged on the second sub-portion can have a structure located between the lower surface of the first area of ​​the protective layer and the upper surface of the second sub-portion of the pad.

[0280] Therefore, the connecting member of the embodiment includes a first component disposed on the second sub-portion. In addition, the first component of the connecting member can be used as an anchor, which improves adhesion and bonding strength with the pad. Therefore, the embodiment can solve the reliability problem of the connection member being separated from the pad. Therefore, the embodiment can improve the overall product reliability of the circuit board and the semiconductor package.

[0281] In addition, the embodiment can improve the contact area between the pad and the connecting member through the anchoring structure of the connecting member. Therefore, the embodiment does not need to increase the size of the pad to improve the contact area. Therefore, the embodiment can reduce the size of the pad, thereby improving the circuit integration. In addition, the embodiment can reduce the overall volume of the circuit board and the semiconductor package.

[0282] Figure 5a It is shown Figure 4a A view of a first modified example of a circuit board, and Figure 5b It is shown Figure 4a FIG. 1 is a view of a second modified example of a circuit board.

[0283] In the following, reference will be made to Figure 5a and Figure 5b A first modified example and a second modified example of the circuit board of the first embodiment are described. Meanwhile, in describing the first modified example and the second modified example, description of substantially the same structure as that of the circuit board of the first embodiment will be omitted.

[0284] The protective layer 450 of the circuit board of the first embodiment includes an opening 450-1 vertically overlapping with the pad 420. At this time, the opening 450-1 has a shape with no change in width in the vertical direction. For example, the width of the opening 450-1 adjacent to the upper surface of the protective layer 450 is the same as the width of the opening 450-1 adjacent to the lower surface of the protective layer 450.

[0285] Different from this, the opening of the protective layer 450 may have a width that changes in the vertical direction. For example, the opening of the protective layer 450 is formed by an exposure and development process. At this time, the shape in which the width of the opening is changed may vary according to the exposure conditions. For example, the exposure conditions include positive conditions and negative conditions. In addition, the opening of the protective layer 450 may have different shapes depending on the exposure conditions.

[0286] refer to Figure 5a , the protection layer 450 may include an opening 450 - 1 a .

[0287] The opening 450 - 1 a of the protective layer 450 may include a region where its width changes.

[0288] For example, the opening 450-1a of the protective layer 450 may vary in width from an area adjacent to an upper surface of the protective layer 450 to an area adjacent to a lower surface of the protective layer 450. For example, the opening 450-1a of the protective layer 450 may have a width that decreases from an area adjacent to an upper surface of the protective layer 450 to an area adjacent to a lower surface of the protective layer 450.

[0289] In addition, the pad 420 in the first modified example includes a first portion P1 including the groove 420-1 and a second portion P2 not including the groove. In addition, the first portion P1 of the pad 420 includes a first sub-portion P1-1 and a second sub-portion P1-2.

[0290] At this time, the width of the opening 450 - 1 a changes in the vertical direction. Therefore, the distinction between the first sub-portion P1 - 1 and the second sub-portion P1 - 2 of the pad 420 in the first modified example may be made based on the lower surface of the first region R1 of the protective layer 450 .

[0291] The second sub-portion P1-2 of the pad 420 may mean a portion including the groove 420-1 and vertically overlapping with the lower surface of the first region R1 of the protective layer 450. In addition, the first sub-portion P1-1 of the pad 420 may mean a portion vertically overlapping with the opening 450-1a of the protective layer 450 and not vertically overlapping with the lower surface of the first region R1 of the protective layer 450.

[0292] refer to Figure 5b , the protection layer 450 may include an opening 450 - 1 b .

[0293] The opening 450 - 1 b of the protective layer 450 may include a region where its width changes.

[0294] For example, the opening 450-1b of the protective layer 450 may change in width from an area adjacent to the upper surface of the protective layer 450 to an area adjacent to the lower surface of the protective layer 450. For example, the opening 450-1b of the protective layer 450 may increase in width from an area adjacent to the upper surface of the protective layer 450 to an area adjacent to the lower surface of the protective layer 450.

[0295] In addition, in the second modified example, the pad 420 includes a first portion P1 including the groove 420-1 and a second portion P2 not including the groove. In addition, the first portion P1 of the pad 420 includes a first sub-portion P1-1 and a second sub-portion P1-2.

[0296] At this time, the opening 450 - 1 a vertically changes in width. Therefore, the first sub-portion P1 - 1 and the second sub-portion P1 - 2 of the pad 420 in the first modified example can be distinguished based on the lower surface of the first region R1 of the protective layer 450 .

[0297] The second sub-portion P1-2 of the pad 420 can mean a portion including the groove 420-1 and vertically overlapping with the lower surface of the first region R1 of the protective layer 450. In addition, the first sub-portion P1-1 of the pad 420 can mean a portion vertically overlapping with the opening 450-1b of the protective layer 450 and not vertically overlapping with the lower surface of the first region R1 of the protective layer 450.

[0298] Hereinafter, a circuit board of another embodiment will be described.

[0299] The circuit board described below has a similar structure to that of the first embodiment, and may differ in the recesses provided in the pads.

[0300] Figure 6 is a cross-sectional view showing a circuit board of the second embodiment.

[0301] refer to Figure 6 , the circuit board of the second embodiment includes an insulating layer 410 , a pad 420 a disposed on the insulating layer 410 , and a protection layer 450 disposed on the insulating layer 410 and including an opening 450 - 1 .

[0302] At this time, the pad 420a includes a groove 420-1a.

[0303] The groove 420 - 1 a may be completely provided on the upper surface of the pad 420 a .

[0304] That is, the pad 420 of the circuit board of the first embodiment includes a first portion P1 having a groove and a second portion P1 having no groove.

[0305] In contrast, the pad 420 a of the circuit board of the second embodiment may include only the first portion P1 having the groove 420 - 1 a .

[0306] Therefore, the pad 420 a may include a first sub-portion P1 - 1 vertically overlapping the opening 450 - 1 of the protective layer 450 and a second sub-portion P1 - 2 vertically overlapping the lower surface of the first region R1 of the protective layer 450 .

[0307] In addition, the lower surface of the first region R1 of the protective layer 450 may vertically overlap with the pad 420 a and may not contact the pad 420 a .

[0308] For example, the entire area of ​​the upper surface of the pad 420 a may not contact the protection layer 450 .

[0309] Figure 7 is a cross-sectional view showing a circuit board of the third embodiment.

[0310] refer to Figure 7 The circuit board of the third embodiment includes an insulating layer 410 , a pad 420 b disposed on the insulating layer 410 , and a protection layer 450 disposed on the insulating layer 410 and including an opening 450 - 1 .

[0311] At this time, the pad 420b includes a groove 420-1b.

[0312] The groove 420 - 1 b may be partially provided on the upper surface of the pad 420 b .

[0313] The pad 420b includes a first portion P1 having the groove 420-1b and a second portion P2 having no groove 420-1b. At this time, the second portion P2 of the pad 420b may be located only on one side of the first portion P1 of the pad 420b.

[0314] For example, the pad 420b may include a first side surface 420b and a second side surface opposite to the first side surface.

[0315] In addition, the second portion P2 of the pad 420b may not exist in the area adjacent to the first side surface of the pad 420b. For example, only the first portion P1 of the pad 420b may be located in the area adjacent to the first side surface of the pad 420b. For example, the first side surface of the pad 420b may be connected to the groove 420-1b. For example, the first side surface of the pad 420b may be directly connected to the second sub-portion P1-2 of the first portion P1 of the pad 420b. In other words, the second portion P2 may not be located between the first side surface of the pad 420b and the second sub-portion P1-2.

[0316] In contrast, the second portion P2 of the pad 420b may exist in an area adjacent to the second side surface opposite to the first side surface of the pad 420b. For example, the second portion P2 of the second sub-portion P1-2 connected to the pad 420b may exist in an area adjacent to the second side surface of the pad 420b. Therefore, the second side surface of the pad may not be connected to the groove 420-1b. For example, the second side surface of the pad 420b may not be directly connected to the first portion P1 of the pad 420b.

[0317] Figure 8a is a diagram showing a circuit board according to a fourth embodiment, and Figure 8b is shown in which the connecting member is arranged Figure 8a A cross-sectional view of the state of the circuit board.

[0318] refer to Figure 8a and 8b , the circuit board of the fourth embodiment includes an insulating layer 410 , a pad 420 c disposed on the insulating layer 410 , and a protection layer 450 disposed on the insulating layer 410 and including an opening 450 - 1 .

[0319] At this time, the pad 420c includes a groove.

[0320] The groove may be completely provided on the upper surface of the pad 420c.

[0321] That is, the groove may include the first part 420 - 1 c 1 provided entirely on the upper surface of the pad 420 c .

[0322] Differently, the pad 420c of the circuit board of the fourth embodiment includes the first part 420-1c1 of the groove, and therefore, the pad 420c may include only the first portion P1. Therefore, the upper surface of the pad 420c may not completely contact the lower surface of the first region R1 of the protective layer 450.

[0323] Meanwhile, the groove may include a second part 420 - 1c2 connected to the first part 420 - 1c1 .

[0324] The second part 420 - 1 c 2 may be formed on the side surface of the pad 420 c while being connected to the first part 420 - 1 c 1 .

[0325] In other words, the groove of the previous embodiment is provided only on the upper surface of the pad.

[0326] Differently, the groove of the fourth embodiment includes a first part 420 - 1 c 1 provided on an upper surface of a pad 420 c and a second part 420 - 1 c 2 provided on a side surface of the pad 420 c .

[0327] At this time, the groove of the fourth embodiment may be completely provided on the entire area of ​​the side surface of the pad 420c.

[0328] Therefore, at least a portion of the side surface of the pad 420 c may not contact the first region R1 and the second region R2 of the protective layer 450 through the second part 420 - 1 c 2 of the groove, respectively.

[0329] In addition, the connection member 500 is disposed in the first part 420-1c1 and the second part 420-1c2 of the groove 420-1b, respectively. The connection member 500 may contact the upper surface of the pad 420c and at least a portion of the side surface of the pad 420c.

[0330] That is, the connection member 500 may be in contact with the upper surface of the pad 420c and the lower surface of the first region R1 of the protective layer 450. In addition, the connection member 500 can be in contact with the side surface of the pad 420c and the inner surface of the second region R2 of the protective layer 450. Through this, the embodiment can further improve the adhesion and bonding strength between the pad and the connection member.

[0331] Meanwhile, the groove provided in the pad of the embodiment may include a plurality of parts. For example, the groove can include a first part provided on the upper surface of the pad and a second part connected to the first part and provided on the side surface of the pad.

[0332] Therefore, at least a portion of the side surface of the pad cannot contact the protective layer through the second part of the groove. In addition, the connecting member can be arranged in the second part of the groove of the pad. The connecting member can be arranged in the first part of the groove and can contact the lower surface of the first area of ​​the protective layer and the upper surface of the pad. In addition, the connecting member can be positioned in the second part of the groove to contact the inner surface of the second area of ​​the protective layer and the side surface of the pad. Therefore, the embodiment can further increase the contact area between the pad and the connecting member. Therefore, the embodiment can further improve the adhesion and bonding strength between the pad and the connecting member.

[0333] Fig. 9is a cross-sectional view showing a circuit board according to a fifth embodiment.

[0334] refer to Fig. 9 The circuit board of the fifth embodiment includes an insulating layer 410 , a pad 420 d disposed on the insulating layer 410 , and a protection layer 450 disposed on the insulating layer 410 and including an opening 450 - 1 .

[0335] At this time, the pad 420d includes a groove.

[0336] A groove may be partially provided on an upper surface of the pad 420d.

[0337] In addition, a groove may be provided on a side surface of the pad 420d.

[0338] That is, the pad 420d may include a first part 420-1d1 partially provided on an upper surface of the pad 420d, and a second part 420-1d2 connected to the first part 420-1d1 and provided on a side surface of the pad 420d.

[0339] Meanwhile, the circuit board of the embodiment may be provided with a plurality of pads, and the plurality of pads may be provided with grooves having different shapes. For example, the circuit board of the embodiment may include grooves having different shapes described in at least two of the first to fifth embodiments. For example, the circuit board may include a first pad and a second pad. In addition, the first pad of the circuit board may be provided with the groove 420-1 of the first embodiment, and the second pad may be provided with the grooves 420-1d1 and 420-1d2 of the fifth embodiment.

[0340] Hereinafter, a method for manufacturing a circuit board according to the embodiment will be described in order of processes.

[0341] Figures 10a to 10d It is used to explain the order of processes in manufacturing. Figure 3 A cross-sectional view of a method for manufacturing a circuit board is illustrated in FIG.

[0342] refer to Fig.10a , the insulating layer 410 is prepared in the embodiment.

[0343] Thereafter, the embodiment forms a via hole VH penetrating the upper and lower surfaces of the insulating layer 410 .

[0344] Next, refer to Fig.10a , the embodiment can form a through electrode 440 filling the through hole VH on the insulating layer 410. In addition, the embodiment can form a first circuit pattern layer 420 including at least one pad on the upper surface of the insulating layer 410. In addition, the embodiment can form a second circuit pattern layer 430 including at least one pad on the lower surface of the insulating layer 420.

[0345] Afterwards, refer to Fig.10c , the embodiment can form the first protection layer 450 on the upper surface of the insulating layer 410. In addition, the embodiment can form the second protection layer 460 on the lower surface of the insulating layer 410.

[0346] Next, refer to Fig.10d , the embodiment can expose and develop each of the first protective layer 450 and the second protective layer 460. Through this, the embodiment can form the opening 450-1 in the first protective layer 450 vertically overlapping with the pad of the first circuit pattern layer 420. In addition, the embodiment can form the opening 460-1 in the second protective layer 460 vertically overlapping with the pad of the second circuit pattern layer 430.

[0347] On the other hand, when a circuit board having the above-mentioned characteristics of the present invention is used in IT equipment or household appliances such as smart phones, server computers, TVs, etc., functions such as signal transmission or power supply can be stably performed. For example, when a circuit board having the characteristics of the present invention performs a semiconductor packaging function, it can play a role in safely protecting the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit between terminals, and electrical open circuit of terminals supplied to the semiconductor chip. In addition, when responsible for the function of signal transmission, the noise problem can be solved. Through this, the circuit board having the above-mentioned characteristics of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and the circuit board applying the present invention can achieve functional unification or technical interlocking with each other.

[0348] When the circuit board having the characteristics of the present invention described above is used in transportation equipment such as a vehicle, the problem of distortion of signals transmitted to the transportation equipment can be solved, or alternatively, the safety of the transportation equipment can be further improved by safely protecting the semiconductor chip controlling the transportation equipment from external influences and solving the problem of leakage current or electrical short circuit between terminals or electrical open circuit of terminals supplied to the semiconductor chip. Therefore, the transportation equipment and the circuit board to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0349] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. In addition, the characteristics, structures, and effects described in each embodiment can be combined or modified for other embodiments by those skilled in the art to which the embodiments belong. Therefore, the contents related to such combinations and changes should be interpreted as being included in the scope of the embodiments.

[0350] In the above, the embodiment is mainly described, but this is only an example and does not limit the embodiment, and the ordinary technicians in the field to which the embodiment belongs will appreciate that various modifications and applications not described above are possible without departing from the essential characteristics of the present embodiment. For example, each component specifically shown in the embodiment can be implemented by modification. In addition, the differences related to these modifications and applications should be interpreted as being included in the scope of the embodiment proposed in the appended claims.

Claims

1. A circuit board, comprising: Insulation layer; a circuit pattern layer disposed on the insulating layer and including a pad; and a protective layer disposed on the insulating layer and comprising an opening vertically overlapping the pad, The pad includes a groove that is recessed from the upper surface of the pad toward the lower surface of the pad. The protective layer includes a first area including the opening and vertically overlapping the pad and a second area excluding the first area. wherein the pad includes a first portion including the groove and a second portion connected to the first portion and not having the groove, The first portion of the pad includes a first sub-portion vertically overlapping the opening of the protective layer and a second sub-portion vertically overlapping the lower surface of the first region of the protective layer, and Wherein, the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.

2. The circuit board according to claim 1, wherein: An upper surface of the second sub-portion of the pad is spaced apart from a lower surface of the first region of the protection layer, and Wherein, an upper surface of the second portion of the pad is in direct contact with a lower surface of the first region of the protection layer.

3. The circuit board according to claim 1, wherein: An upper surface of the first portion of the pad has a concavo-convex shape.

4. The circuit board according to claim 1, wherein: The width of the second sub-portion of the pad satisfies a range of 2 to 50 times the width of the second portion of the pad.

5. The circuit board according to claim 1, wherein: A vertical distance from a lower surface of the first region of the protective layer to an upper surface of the first portion of the pad satisfies a range of 5% to 55% of a vertical distance from a lower surface of the first region of the protective layer to a lower surface of the pad.

6. The circuit board according to any one of claims 1 to 5, wherein: The pad includes a side surface, and Wherein, at least a portion of the upper surface of the first portion of the pad is connected to the side surface of the pad.

7. The circuit board according to any one of claims 1 to 5, wherein: The groove of the pad is connected to a side surface of the pad.

8. The circuit board according to any one of claims 1 to 5, wherein: The pad includes a first side surface and a second side surface opposite to the first side surface, and The width of the second sub-portion of the pad adjacent to the first side surface of the pad is different from the width of the second sub-portion of the pad adjacent to the second side surface of the pad.

9. The circuit board according to any one of claims 1 to 5, wherein: The groove comprises: a first component provided on an upper surface of the pad; and A second component is provided on a side surface of the pad and is connected to the first component.

10. The circuit board according to claim 9, wherein: A side surface of the pad having the second member is spaced apart from the protection layer.

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