Capacitor chip production process
By etching bottle-like trenches in a silicon-based MIS capacitor chip, depositing silicon particles to form a raised electrode, and forming a heat dissipation and isolation structure in the capacitor gap, the problems of low capacitance density, poor heat dissipation and reliability of traditional capacitor chips are solved, and the combination of high-density capacitors and good heat dissipation performance is achieved.
Patent Information
- Application Number
- CN202411678250.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-03-07
AI Technical Summary
The capacitance density of traditional silicon-based MIS capacitors is low, which cannot meet the demand for high-density capacitors in high-frequency circuits. The high-density distribution leads to high power density and poor heat dissipation effect, which is prone to reliability problems such as breakdown and short circuit.
By etching on the silicon substrate, forming bottle-shaped grooves with narrow upper and wide upper lower lower, depositing hemispherical silicon particles to form convex electrodes, filling conductive materials to form conductive layers, and forming a heat dissipation and isolation structure in adjacent capacitor gaps to improve capacitance value and heat dissipation performance.
Without changing the capacitance density, the capacitance value and heat dissipation performance are improved, the stability and integration density of the capacitor chip are improved, and the problem of large size caused by additional space occupation is avoided.
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Figure CN119584554A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a production process of a capacitor chip. Background Art
[0002] Traditional discrete devices are large in size and have obvious parasitic effects, which cannot meet the requirements of future integration. Integrated chip embedded capacitors have become a key technology to solve the miniaturization and high integration of systems. Embedded Metal Insulator Semiconductor (MIS) has a wide range of application prospects in filter circuits and decoupling circuits due to its low parasitic impedance and inductance. Especially in advanced packaging integrated systems, MIS has become a more ideal choice.
[0003] However, the capacitance density of traditional silicon-based MIS capacitors is relatively low, and cannot meet the demand for high-density capacitors in high-frequency circuits. The existing technology usually uses a deep silicon etching process to prepare a silicon pore structure with a high aspect ratio on a planar silicon wafer, and form a capacitor structure in the silicon pore structure, thereby increasing the capacitance density of the MIS capacitor. However, due to the high-density distribution, the power density is high, which leads to local overheating and poor heat dissipation of the device. In addition, the distance between the capacitor structures is relatively close, which is prone to reliability problems in high-temperature and high-pressure environments, causing breakdown and leakage. In addition, its high-density distribution and easy short-circuiting limit the possibility of further increase in capacitance. As shown in the attached figure Figure 1-2 The figure shows a cross-sectional view and a top view of an existing silicon hole capacitor chip structure. There is a gap space A between adjacent trench silicon hole capacitors 1. The gap space is a heat dissipation space and an isolation space between the capacitors. If the gap space A is too large, the capacitance density will be reduced; if the gap space A is too small, it is easy to cause a breakdown short circuit.
[0004] Therefore, in order to improve the above-mentioned problems of the trench MIS capacitor chip, it is necessary to provide a capacitor chip preparation process that can improve the heat dissipation, stability and capacitance value of the chip. Summary of the invention
[0005] In order to solve the heat dissipation problem, breakdown leakage problem and the problem of how to further improve the capacitance value of the trench type MIS capacitor chip existing in the prior art, the present invention provides a production process of chip capacitors, and the technical solution is as follows:
[0006] A production process for a capacitor chip, characterized in that it comprises the following steps:
[0007] providing a substrate;
[0008] Etching the substrate to form a plurality of upper grooves;
[0009] Extendedly etching the bottoms of the plurality of upper grooves to form ellipsoidal lower grooves;
[0010] The upper groove and the lower groove form a bottle-shaped groove that is narrow at the top and wide at the bottom;
[0011] Depositing silicon particles on the sidewalls of the upper trench and the lower trench, wherein the silicon particles are hemispherical;
[0012] Performing ion implantation to form a lower electrode;
[0013] Depositing a dielectric layer on the surface of the lower electrode, and etching the dielectric layer to form an intermediate dielectric layer;
[0014] Filling a conductive material in the hollow structure surrounded by the intermediate dielectric layer to form a conductive layer, and etching to form an upper electrode of the capacitor, wherein the lower electrode, the intermediate dielectric layer and the upper electrode constitute a trench capacitor;
[0015] The gaps between three adjacent trench capacitors are etched to form heat dissipation isolation.
[0016] A capacitor chip, which is prepared using the above-mentioned capacitor chip production process, is characterized by:
[0017] It includes a substrate, a plurality of trench capacitors, and a heat dissipation isolation structure;
[0018] Wherein, the plurality of trench capacitors are arranged in a staggered array; the heat dissipation isolation structure is located between three adjacent staggered trench capacitors;
[0019] The trench capacitor comprises an upper electrode and a lower electrode, and the upper electrode and the lower electrode have a convex structure;
[0020] The trench capacitor comprises a cylindrical upper part and an ellipsoidal lower part;
[0021] The heat dissipation isolation structure comprises a cylindrical upper part and a conical lower part;
[0022] The heat dissipation isolation structure has excellent thermal conductivity and electrical insulation properties.
[0023] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:
[0024] 1. Etch silicon to form holes, and deposit materials with excellent thermal conductivity and electrical insulation properties in the holes to form a heat dissipation isolation structure, thereby improving the heat dissipation performance of the capacitor chip and further improving the electrical insulation performance between trench capacitors.
[0025] 2. Etch the gap silicon substrate between three adjacent capacitor silicon holes to form a heat dissipation isolation structure, which fully utilizes the gap space between the silicon holes, improves chip performance without changing the capacitance density, avoids setting up a heat dissipation isolation structure to occupy additional space and cause the size to be too large, and further improves the chip integration density.
[0026] 3. By depositing silicon grains and forming a depression in the intermediate dielectric layer, the convex shape of the upper and lower electrodes of the capacitor is formed, thereby increasing the electrode area and increasing the capacitance value without changing the capacitance density and chip size;
[0027] 4. Through two etching processes, a groove bottle-shaped structure with a narrow top and a wide bottom is formed, which can further increase the electrode area of the capacitor chip and improve the capacitance value. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0029] Figure 1 It is a schematic cross-sectional view of the existing capacitor chip structure;
[0030] Figure 2 It is a top view schematic diagram of the existing capacitor chip structure;
[0031] Figure 3-13 The invention discloses a production process of a capacitor chip.
[0032] Reference numerals:
[0033] A-interstitial space;
[0034] 1- Trench silicon hole capacitor;
[0035] 301 - substrate; 302 - first hard mask; 303 - upper trench;
[0036] 402-mask; 403-lower trench;
[0037] 501-silicon particles;
[0038] 601-lower electrode;
[0039] 701- medium layer;
[0040] 801-intermediate dielectric layer;
[0041] 901-conductive layer;
[0042] 1001 - a second hard mask;
[0043] 1002-upper electrode;
[0044] 1003- Trench capacitor;
[0045] 1102-hole;
[0046] 1202- heat dissipation insulation layer;
[0047] 1302-Heat dissipation isolation. DETAILED DESCRIPTION
[0048] The technical solution of the present invention is described below in conjunction with the accompanying drawings.
[0049] In order to better understand the spirit of the present application, it is further described below in conjunction with some preferred embodiments of the present application. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar figure marks. The embodiments of the accompanying drawings described herein are illustrative and graphical and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.
[0050] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.
[0051] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.
[0052] Example 1
[0053] This embodiment describes a production process of a capacitor chip, which is as follows:
[0054] like Figure 3 As shown, a substrate 301 is first provided. The substrate 301 is a silicon substrate. According to actual device function requirements, transistors or other active devices can be formed and buried inside the substrate 301 at the same time.
[0055] A hard mask layer is deposited on the upper surface of the substrate 301. Generally, boron-doped silicon oxide (BSG) with a fast wet etching rate is used as the hard mask material. The hard mask layer is photolithographically processed to form a first hard mask 302 having an opening.
[0056] Then, the substrate 301 is etched by deep reactive ion etching to form an upper groove 303 . The depth of the upper groove 303 is 1 / 2-3 / 5 of the thickness of the substrate 301 .
[0057] In the specific etching process, by alternately introducing etching gas and passivation gas, the generation of side wall burrs can be reduced while ensuring the etching rate. The burrs on the hole wall in deep silicon etching will form an electric field concentration, causing the capacitor to fail prematurely. By adjusting the etching and passivation time, a relatively smooth side wall morphology can be controlled to further improve the breakdown voltage of the high-density capacitor. The etching gas is preferably SF 6 The passivating gas is preferably C 4 F 8
[0058] The first hard mask 302 is cleaned and removed, and a mask 402 is formed after drying. Figure 4 The mask 402 can be formed by sequentially depositing silicon oxide and silicon nitride using a CVD method.
[0059] Afterwards, the bottom of the upper trench 303 is etched by isotropic etching such as chemical dry etching. In this etching step, the etching is extended along the bottom of the upper trench 303 to form an ellipsoidal lower trench 403. The depth of the lower trench 403 is 2 / 5-1 / 2 of the thickness of the substrate 301.
[0060] The traditional trench capacitor structure uses a deposited metal layer as the lower electrode. However, in a high aspect ratio trench capacitor, conventional metal sputtering and evaporation processes cannot completely cover the sidewalls of the high aspect ratio through-holes, and reliability problems such as voids and detachment are very likely to occur. In this embodiment, a silicon doping process is used to prepare the lower electrode, which has a high sidewall coverage rate and good capacitor stability. Figure 5-6 Shown is the lower electrode preparation process.
[0061] exist Figure 5 In the embodiment, a layer of hemispherical silicon particles 501 with a diameter of about 20-40 nm is deposited on the sidewalls of the upper trench 303 and the lower trench 403 by low pressure chemical vapor deposition (LPCVD).
[0062] Next, a doping process is used to introduce doping gas into the sidewalls of the upper trench 303 and the lower trench 403, and after annealing and diffusion, a lower electrode 601 having a convex shape is formed on the trench sidewalls and the silicon particles 501. The doping process is in-situ phosphorus doping, and the doping gas is phosphine.
[0063] Compared with the metal deposition sidewall method, the semiconductor electrode structure formed by silicon doping has a high sidewall coverage rate, and the resistivity can be controlled by adjusting the proportion and type of doping impurities, with better capacitance stability and greater flexibility. In addition, by setting up hemispherical silicon particles, the electrode coverage area is increased, and the capacitance value is further increased without changing the chip size and capacitance density.
[0064] Then, refer to Figure 7 A dielectric layer 701 is deposited on the lower electrode 601 by LPCVD.
[0065] Specifically, the deposition process is a two-step deposition process. First, a layer of silicon oxide is deposited by LPCVD. Since silicon oxide is relatively dense, it can well cover the gaps between silicon particles 501. The thickness of the silicon oxide dielectric layer is between 70nm and 100nm to ensure complete coverage of the silicon particles 501. Then, a layer of silicon nitride is deposited by LPCVD. Since silicon nitride has a large dielectric constant, the capacitance density can be further increased. In an optional embodiment, the dielectric layer can also be silicon oxide / silicon nitride / silicon oxide, which can achieve the technical effect of improving the contact tightness between the dielectric layer and the lower electrode.
[0066] Then, if Figure 8 As shown, etching is performed on the surface of the dielectric layer 701 to form an intermediate dielectric layer 801. Specifically, the surface of the dielectric layer formed after etching is a hemispherical concave shape, which can increase the surface area of the subsequently deposited upper electrode to further increase the capacitance value.
[0067] Afterwards, refer to Fig. 9 As shown, a conductive material is filled in the cavity of the intermediate dielectric layer 801 to form a conductive layer 901. The conductive material completely fills the cavity and covers part of the mask layer surface. The conductive material can be a metal material, which can be one or more of copper, aluminum, tungsten, titanium, platinum or tantalum, preferably copper.
[0068] Furthermore, the conductive layer 901 is deposited on the dielectric layer surface and the hemispherical concave rear sidewall forms a convex structure. The convex shape increases the surface area of the upper electrode and improves the capacitance value.
[0069] Then, mechanical polishing or other means are used to remove the structure on the upper surface of the substrate 301, and after cleaning and drying, the capacitor upper electrode 1002 is formed. Fig.10 A second hard mask 1001 is shown.
[0070] The second hard mask 1001 has an opening, and the opening is located between three adjacent silicon hole trench capacitors. Figure 2 In area A shown in .
[0071] Then, the second hard mask 1001 is used as a mask to perform etching according to the opening position to form a hole 1102. The hole 1102 gradually narrows at the intersection of the upper trench 303 and the lower trench 403, and the overall shape is wide at the top and narrow at the bottom, forming a hole structure with a cylindrical top and a conical bottom.
[0072] Next, a heat dissipation insulating material is deposited in the hole 1102 to form a heat dissipation insulating layer 1202 . The heat dissipation insulating layer 1202 is flush with the upper surface of the second hard mask 1001 .
[0073] Next, mechanical polishing or other means are used to remove the structure on the upper surface of the substrate 301, and the heat dissipation insulating layer 1202 inside the substrate 301 is retained to form a heat dissipation isolation 1302, which is located between each three adjacent staggered trench capacitors 1003. After cleaning and drying, a capacitor chip with multiple trench capacitors 1103 is formed.
[0074] Preferably, the heat dissipation insulating layer material is one or more of aluminum nitride, boron nitride or aluminum oxide, or other materials having both excellent thermal conductivity and electrical insulation properties.
[0075] In this embodiment, by forming heat dissipation isolation 1302 in the gap space A between the silicon hole capacitors, the heat dissipation performance of the trench capacitor chip is improved in the environment of high-density capacitor layout and high-power operation, and this method does not need to increase additional heat dissipation space, thereby ensuring the chip integration density. At the same time, the heat dissipation isolation structure has excellent electrical insulation performance, which can increase the capacitor breakdown voltage and prevent leakage and short circuit.
[0076] Example 2
[0077] This embodiment describes a capacitor chip structure prepared according to the process of Embodiment 1, which is as follows:
[0078] The capacitor chip structure includes a substrate 301, a plurality of trench capacitors 1003, and heat dissipation isolation 1302;
[0079] The capacitors 1003 are arranged in a staggered array; the heat dissipation isolation 1302 is located between three adjacent staggered trench capacitors 1003;
[0080] Furthermore, the trench capacitor 1003 has an upper electrode and a lower electrode, and the upper electrode and the lower electrode have a convex structure;
[0081] Further, the trench capacitor 1003 includes a cylindrical upper part and an ellipsoidal lower part;
[0082] Furthermore, the heat dissipation isolation 1302 includes a cylindrical upper part and a conical lower part;
[0083] Furthermore, the material of the heat dissipation isolation 1302 has excellent thermal conductivity and electrical insulation properties.
[0084] In summary of the above embodiments, the present invention mainly provides a production process for a capacitor chip, which forms a bottle-shaped groove structure by etching a silicon substrate, and forms a capacitor upper electrode and a capacitor lower electrode with a convex shape in the groove by depositing silicon grains, ion implantation, forming an intermediate dielectric layer, etching the intermediate dielectric layer, and depositing a conductive layer; hole etching is performed in the gaps between three adjacent groove capacitors, and heat dissipation insulating materials are deposited to form a heat dissipation isolation structure. The present invention forms a bottle-shaped groove by two etching processes, combined with the convex structure of the electrode, to further improve the chip capacitance value; in addition, the present invention forms a heat dissipation isolation structure to improve the chip integration density, improve the heat dissipation performance of the capacitor chip, and further improve the electrical insulation performance between capacitors.
[0085] The above is only a preferred embodiment of the present invention. Professional and technical personnel in this field, without departing from the scope of the technical solution of the present invention, when using the above technical content to make equivalent embodiments with slight changes, still fall within the scope of the technical solution of the present invention.
Claims
1. A production process for a capacitor chip, characterized in that The following steps are involved: Providing a substrate (301); Etching the substrate (301) to form a plurality of upper grooves (303); Extendedly etching the bottom of the upper groove (303) to form an ellipsoidal lower groove (403); The upper groove (303) and the lower groove (403) form a bottle-shaped groove that is narrow at the top and wide at the bottom; Depositing silicon particles (501) on the sidewalls of the upper trench (303) and the lower trench (403), wherein the silicon particles (501) are hemispherical; Performing diffusion doping to form a lower electrode (601); Depositing a dielectric layer (701) on the surface of the lower electrode (601), and etching the dielectric layer (701) to form an intermediate dielectric layer (801); Filling a conductive material in the hollow structure surrounded by the intermediate dielectric layer (801) to form a conductive layer (901), and etching to form an upper electrode (1002), wherein the lower electrode (601), the intermediate dielectric layer (801), and the upper electrode (1002) constitute a trench capacitor (1003); The gaps between three adjacent trench capacitors (1003) are etched to form heat dissipation isolation (1302).
2. The production process of the capacitor chip according to claim 1, characterized in that: The etching is plasma etching, and is completed by alternately introducing etching gas and passivation gas.
3. The production process of the capacitor chip according to claim 1, characterized in that: The diffusion doping is an in-situ phosphorus doping process.
4. The production process of the capacitor chip according to claim 3, characterized in that: The doping gas in the in-situ phosphorus doping process is phosphine.
5. The production process of the capacitor chip according to claim 1, characterized in that: A silicon oxide layer and a silicon nitride layer are deposited on the surface of the lower electrode (601) in sequence by using a low pressure chemical vapor deposition (LPCVD) process to form the dielectric layer (701).
6. The production process of the capacitor chip according to claim 5, characterized in that: The silicon oxide layer completely covers the silicon particles (501).
7. The production process of the capacitor chip according to claim 6, further comprising: The silicon nitride layer is etched to form a hemispherical recessed structure.
8. The production process of the capacitor chip according to claim 7, further comprising: The side wall of the upper electrode (1002) has a convex shape.
9. The production process of the capacitor chip according to claim 8, further comprising: The gaps between three adjacent trench capacitors (1003) are etched to form holes (1102), and heat dissipation insulating material is deposited in the holes (1102) to form the heat dissipation isolation (1302).
10. A capacitor chip, the capacitor chip being manufactured using the production process of the capacitor chip according to any one of claims 1 to 9, characterized in that: It includes a substrate (301), a plurality of trench capacitors (1003), and heat dissipation isolation (1302); Wherein, the plurality of trench capacitors (1003) are arranged in a multi-row staggered array; the heat dissipation isolation (1302) is located between three adjacent staggered trench capacitors (1003); The trench capacitor (1003) has an upper electrode and a lower electrode, and the upper electrode and the lower electrode have a convex structure; The trench capacitor (1003) comprises a cylindrical upper part and an ellipsoidal lower part; The heat dissipation isolation (1302) comprises a cylindrical upper part and a conical lower part; The heat dissipation isolation (1302) has excellent thermal conductivity and electrical insulation properties.